1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * cs42l42.c -- CS42L42 ALSA SoC audio driver 4 * 5 * Copyright 2016 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * Author: Brian Austin <brian.austin@cirrus.com> 9 * Author: Michael White <michael.white@cirrus.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/version.h> 15 #include <linux/kernel.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/i2c.h> 19 #include <linux/gpio.h> 20 #include <linux/regmap.h> 21 #include <linux/slab.h> 22 #include <linux/platform_device.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/gpio/consumer.h> 25 #include <linux/of.h> 26 #include <linux/of_gpio.h> 27 #include <linux/of_device.h> 28 #include <linux/pm_runtime.h> 29 #include <sound/core.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/soc.h> 33 #include <sound/soc-dapm.h> 34 #include <sound/initval.h> 35 #include <sound/tlv.h> 36 #include <dt-bindings/sound/cs42l42.h> 37 38 #include "cs42l42.h" 39 40 static const struct reg_default cs42l42_reg_defaults[] = { 41 { CS42L42_FRZ_CTL, 0x00 }, 42 { CS42L42_SRC_CTL, 0x10 }, 43 { CS42L42_MCLK_STATUS, 0x02 }, 44 { CS42L42_MCLK_CTL, 0x02 }, 45 { CS42L42_SFTRAMP_RATE, 0xA4 }, 46 { CS42L42_I2C_DEBOUNCE, 0x88 }, 47 { CS42L42_I2C_STRETCH, 0x03 }, 48 { CS42L42_I2C_TIMEOUT, 0xB7 }, 49 { CS42L42_PWR_CTL1, 0xFF }, 50 { CS42L42_PWR_CTL2, 0x84 }, 51 { CS42L42_PWR_CTL3, 0x20 }, 52 { CS42L42_RSENSE_CTL1, 0x40 }, 53 { CS42L42_RSENSE_CTL2, 0x00 }, 54 { CS42L42_OSC_SWITCH, 0x00 }, 55 { CS42L42_OSC_SWITCH_STATUS, 0x05 }, 56 { CS42L42_RSENSE_CTL3, 0x1B }, 57 { CS42L42_TSENSE_CTL, 0x1B }, 58 { CS42L42_TSRS_INT_DISABLE, 0x00 }, 59 { CS42L42_TRSENSE_STATUS, 0x00 }, 60 { CS42L42_HSDET_CTL1, 0x77 }, 61 { CS42L42_HSDET_CTL2, 0x00 }, 62 { CS42L42_HS_SWITCH_CTL, 0xF3 }, 63 { CS42L42_HS_DET_STATUS, 0x00 }, 64 { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 65 { CS42L42_MCLK_SRC_SEL, 0x00 }, 66 { CS42L42_SPDIF_CLK_CFG, 0x00 }, 67 { CS42L42_FSYNC_PW_LOWER, 0x00 }, 68 { CS42L42_FSYNC_PW_UPPER, 0x00 }, 69 { CS42L42_FSYNC_P_LOWER, 0xF9 }, 70 { CS42L42_FSYNC_P_UPPER, 0x00 }, 71 { CS42L42_ASP_CLK_CFG, 0x00 }, 72 { CS42L42_ASP_FRM_CFG, 0x10 }, 73 { CS42L42_FS_RATE_EN, 0x00 }, 74 { CS42L42_IN_ASRC_CLK, 0x00 }, 75 { CS42L42_OUT_ASRC_CLK, 0x00 }, 76 { CS42L42_PLL_DIV_CFG1, 0x00 }, 77 { CS42L42_ADC_OVFL_STATUS, 0x00 }, 78 { CS42L42_MIXER_STATUS, 0x00 }, 79 { CS42L42_SRC_STATUS, 0x00 }, 80 { CS42L42_ASP_RX_STATUS, 0x00 }, 81 { CS42L42_ASP_TX_STATUS, 0x00 }, 82 { CS42L42_CODEC_STATUS, 0x00 }, 83 { CS42L42_DET_INT_STATUS1, 0x00 }, 84 { CS42L42_DET_INT_STATUS2, 0x00 }, 85 { CS42L42_SRCPL_INT_STATUS, 0x00 }, 86 { CS42L42_VPMON_STATUS, 0x00 }, 87 { CS42L42_PLL_LOCK_STATUS, 0x00 }, 88 { CS42L42_TSRS_PLUG_STATUS, 0x00 }, 89 { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, 90 { CS42L42_MIXER_INT_MASK, 0x0F }, 91 { CS42L42_SRC_INT_MASK, 0x0F }, 92 { CS42L42_ASP_RX_INT_MASK, 0x1F }, 93 { CS42L42_ASP_TX_INT_MASK, 0x0F }, 94 { CS42L42_CODEC_INT_MASK, 0x03 }, 95 { CS42L42_SRCPL_INT_MASK, 0xFF }, 96 { CS42L42_VPMON_INT_MASK, 0x01 }, 97 { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, 98 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, 99 { CS42L42_PLL_CTL1, 0x00 }, 100 { CS42L42_PLL_DIV_FRAC0, 0x00 }, 101 { CS42L42_PLL_DIV_FRAC1, 0x00 }, 102 { CS42L42_PLL_DIV_FRAC2, 0x00 }, 103 { CS42L42_PLL_DIV_INT, 0x40 }, 104 { CS42L42_PLL_CTL3, 0x10 }, 105 { CS42L42_PLL_CAL_RATIO, 0x80 }, 106 { CS42L42_PLL_CTL4, 0x03 }, 107 { CS42L42_LOAD_DET_RCSTAT, 0x00 }, 108 { CS42L42_LOAD_DET_DONE, 0x00 }, 109 { CS42L42_LOAD_DET_EN, 0x00 }, 110 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, 111 { CS42L42_WAKE_CTL, 0xC0 }, 112 { CS42L42_ADC_DISABLE_MUTE, 0x00 }, 113 { CS42L42_TIPSENSE_CTL, 0x02 }, 114 { CS42L42_MISC_DET_CTL, 0x03 }, 115 { CS42L42_MIC_DET_CTL1, 0x1F }, 116 { CS42L42_MIC_DET_CTL2, 0x2F }, 117 { CS42L42_DET_STATUS1, 0x00 }, 118 { CS42L42_DET_STATUS2, 0x00 }, 119 { CS42L42_DET_INT1_MASK, 0xE0 }, 120 { CS42L42_DET_INT2_MASK, 0xFF }, 121 { CS42L42_HS_BIAS_CTL, 0xC2 }, 122 { CS42L42_ADC_CTL, 0x00 }, 123 { CS42L42_ADC_VOLUME, 0x00 }, 124 { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, 125 { CS42L42_DAC_CTL1, 0x00 }, 126 { CS42L42_DAC_CTL2, 0x02 }, 127 { CS42L42_HP_CTL, 0x0D }, 128 { CS42L42_CLASSH_CTL, 0x07 }, 129 { CS42L42_MIXER_CHA_VOL, 0x3F }, 130 { CS42L42_MIXER_ADC_VOL, 0x3F }, 131 { CS42L42_MIXER_CHB_VOL, 0x3F }, 132 { CS42L42_EQ_COEF_IN0, 0x22 }, 133 { CS42L42_EQ_COEF_IN1, 0x00 }, 134 { CS42L42_EQ_COEF_IN2, 0x00 }, 135 { CS42L42_EQ_COEF_IN3, 0x00 }, 136 { CS42L42_EQ_COEF_RW, 0x00 }, 137 { CS42L42_EQ_COEF_OUT0, 0x00 }, 138 { CS42L42_EQ_COEF_OUT1, 0x00 }, 139 { CS42L42_EQ_COEF_OUT2, 0x00 }, 140 { CS42L42_EQ_COEF_OUT3, 0x00 }, 141 { CS42L42_EQ_INIT_STAT, 0x00 }, 142 { CS42L42_EQ_START_FILT, 0x00 }, 143 { CS42L42_EQ_MUTE_CTL, 0x00 }, 144 { CS42L42_SP_RX_CH_SEL, 0x04 }, 145 { CS42L42_SP_RX_ISOC_CTL, 0x04 }, 146 { CS42L42_SP_RX_FS, 0x8C }, 147 { CS42l42_SPDIF_CH_SEL, 0x0E }, 148 { CS42L42_SP_TX_ISOC_CTL, 0x04 }, 149 { CS42L42_SP_TX_FS, 0xCC }, 150 { CS42L42_SPDIF_SW_CTL1, 0x3F }, 151 { CS42L42_SRC_SDIN_FS, 0x40 }, 152 { CS42L42_SRC_SDOUT_FS, 0x40 }, 153 { CS42L42_SPDIF_CTL1, 0x01 }, 154 { CS42L42_SPDIF_CTL2, 0x00 }, 155 { CS42L42_SPDIF_CTL3, 0x00 }, 156 { CS42L42_SPDIF_CTL4, 0x42 }, 157 { CS42L42_ASP_TX_SZ_EN, 0x00 }, 158 { CS42L42_ASP_TX_CH_EN, 0x00 }, 159 { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, 160 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, 161 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, 162 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, 163 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, 164 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, 165 { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 166 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, 167 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, 168 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, 169 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, 170 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, 171 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, 172 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, 173 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, 174 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, 175 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, 176 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, 177 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, 178 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, 179 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, 180 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, 181 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, 182 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, 183 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, 184 { CS42L42_SUB_REVID, 0x03 }, 185 }; 186 187 static bool cs42l42_readable_register(struct device *dev, unsigned int reg) 188 { 189 switch (reg) { 190 case CS42L42_PAGE_REGISTER: 191 case CS42L42_DEVID_AB: 192 case CS42L42_DEVID_CD: 193 case CS42L42_DEVID_E: 194 case CS42L42_FABID: 195 case CS42L42_REVID: 196 case CS42L42_FRZ_CTL: 197 case CS42L42_SRC_CTL: 198 case CS42L42_MCLK_STATUS: 199 case CS42L42_MCLK_CTL: 200 case CS42L42_SFTRAMP_RATE: 201 case CS42L42_I2C_DEBOUNCE: 202 case CS42L42_I2C_STRETCH: 203 case CS42L42_I2C_TIMEOUT: 204 case CS42L42_PWR_CTL1: 205 case CS42L42_PWR_CTL2: 206 case CS42L42_PWR_CTL3: 207 case CS42L42_RSENSE_CTL1: 208 case CS42L42_RSENSE_CTL2: 209 case CS42L42_OSC_SWITCH: 210 case CS42L42_OSC_SWITCH_STATUS: 211 case CS42L42_RSENSE_CTL3: 212 case CS42L42_TSENSE_CTL: 213 case CS42L42_TSRS_INT_DISABLE: 214 case CS42L42_TRSENSE_STATUS: 215 case CS42L42_HSDET_CTL1: 216 case CS42L42_HSDET_CTL2: 217 case CS42L42_HS_SWITCH_CTL: 218 case CS42L42_HS_DET_STATUS: 219 case CS42L42_HS_CLAMP_DISABLE: 220 case CS42L42_MCLK_SRC_SEL: 221 case CS42L42_SPDIF_CLK_CFG: 222 case CS42L42_FSYNC_PW_LOWER: 223 case CS42L42_FSYNC_PW_UPPER: 224 case CS42L42_FSYNC_P_LOWER: 225 case CS42L42_FSYNC_P_UPPER: 226 case CS42L42_ASP_CLK_CFG: 227 case CS42L42_ASP_FRM_CFG: 228 case CS42L42_FS_RATE_EN: 229 case CS42L42_IN_ASRC_CLK: 230 case CS42L42_OUT_ASRC_CLK: 231 case CS42L42_PLL_DIV_CFG1: 232 case CS42L42_ADC_OVFL_STATUS: 233 case CS42L42_MIXER_STATUS: 234 case CS42L42_SRC_STATUS: 235 case CS42L42_ASP_RX_STATUS: 236 case CS42L42_ASP_TX_STATUS: 237 case CS42L42_CODEC_STATUS: 238 case CS42L42_DET_INT_STATUS1: 239 case CS42L42_DET_INT_STATUS2: 240 case CS42L42_SRCPL_INT_STATUS: 241 case CS42L42_VPMON_STATUS: 242 case CS42L42_PLL_LOCK_STATUS: 243 case CS42L42_TSRS_PLUG_STATUS: 244 case CS42L42_ADC_OVFL_INT_MASK: 245 case CS42L42_MIXER_INT_MASK: 246 case CS42L42_SRC_INT_MASK: 247 case CS42L42_ASP_RX_INT_MASK: 248 case CS42L42_ASP_TX_INT_MASK: 249 case CS42L42_CODEC_INT_MASK: 250 case CS42L42_SRCPL_INT_MASK: 251 case CS42L42_VPMON_INT_MASK: 252 case CS42L42_PLL_LOCK_INT_MASK: 253 case CS42L42_TSRS_PLUG_INT_MASK: 254 case CS42L42_PLL_CTL1: 255 case CS42L42_PLL_DIV_FRAC0: 256 case CS42L42_PLL_DIV_FRAC1: 257 case CS42L42_PLL_DIV_FRAC2: 258 case CS42L42_PLL_DIV_INT: 259 case CS42L42_PLL_CTL3: 260 case CS42L42_PLL_CAL_RATIO: 261 case CS42L42_PLL_CTL4: 262 case CS42L42_LOAD_DET_RCSTAT: 263 case CS42L42_LOAD_DET_DONE: 264 case CS42L42_LOAD_DET_EN: 265 case CS42L42_HSBIAS_SC_AUTOCTL: 266 case CS42L42_WAKE_CTL: 267 case CS42L42_ADC_DISABLE_MUTE: 268 case CS42L42_TIPSENSE_CTL: 269 case CS42L42_MISC_DET_CTL: 270 case CS42L42_MIC_DET_CTL1: 271 case CS42L42_MIC_DET_CTL2: 272 case CS42L42_DET_STATUS1: 273 case CS42L42_DET_STATUS2: 274 case CS42L42_DET_INT1_MASK: 275 case CS42L42_DET_INT2_MASK: 276 case CS42L42_HS_BIAS_CTL: 277 case CS42L42_ADC_CTL: 278 case CS42L42_ADC_VOLUME: 279 case CS42L42_ADC_WNF_HPF_CTL: 280 case CS42L42_DAC_CTL1: 281 case CS42L42_DAC_CTL2: 282 case CS42L42_HP_CTL: 283 case CS42L42_CLASSH_CTL: 284 case CS42L42_MIXER_CHA_VOL: 285 case CS42L42_MIXER_ADC_VOL: 286 case CS42L42_MIXER_CHB_VOL: 287 case CS42L42_EQ_COEF_IN0: 288 case CS42L42_EQ_COEF_IN1: 289 case CS42L42_EQ_COEF_IN2: 290 case CS42L42_EQ_COEF_IN3: 291 case CS42L42_EQ_COEF_RW: 292 case CS42L42_EQ_COEF_OUT0: 293 case CS42L42_EQ_COEF_OUT1: 294 case CS42L42_EQ_COEF_OUT2: 295 case CS42L42_EQ_COEF_OUT3: 296 case CS42L42_EQ_INIT_STAT: 297 case CS42L42_EQ_START_FILT: 298 case CS42L42_EQ_MUTE_CTL: 299 case CS42L42_SP_RX_CH_SEL: 300 case CS42L42_SP_RX_ISOC_CTL: 301 case CS42L42_SP_RX_FS: 302 case CS42l42_SPDIF_CH_SEL: 303 case CS42L42_SP_TX_ISOC_CTL: 304 case CS42L42_SP_TX_FS: 305 case CS42L42_SPDIF_SW_CTL1: 306 case CS42L42_SRC_SDIN_FS: 307 case CS42L42_SRC_SDOUT_FS: 308 case CS42L42_SPDIF_CTL1: 309 case CS42L42_SPDIF_CTL2: 310 case CS42L42_SPDIF_CTL3: 311 case CS42L42_SPDIF_CTL4: 312 case CS42L42_ASP_TX_SZ_EN: 313 case CS42L42_ASP_TX_CH_EN: 314 case CS42L42_ASP_TX_CH_AP_RES: 315 case CS42L42_ASP_TX_CH1_BIT_MSB: 316 case CS42L42_ASP_TX_CH1_BIT_LSB: 317 case CS42L42_ASP_TX_HIZ_DLY_CFG: 318 case CS42L42_ASP_TX_CH2_BIT_MSB: 319 case CS42L42_ASP_TX_CH2_BIT_LSB: 320 case CS42L42_ASP_RX_DAI0_EN: 321 case CS42L42_ASP_RX_DAI0_CH1_AP_RES: 322 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: 323 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: 324 case CS42L42_ASP_RX_DAI0_CH2_AP_RES: 325 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: 326 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: 327 case CS42L42_ASP_RX_DAI0_CH3_AP_RES: 328 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: 329 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: 330 case CS42L42_ASP_RX_DAI0_CH4_AP_RES: 331 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: 332 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: 333 case CS42L42_ASP_RX_DAI1_CH1_AP_RES: 334 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: 335 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: 336 case CS42L42_ASP_RX_DAI1_CH2_AP_RES: 337 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: 338 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: 339 case CS42L42_SUB_REVID: 340 return true; 341 default: 342 return false; 343 } 344 } 345 346 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 347 { 348 switch (reg) { 349 case CS42L42_DEVID_AB: 350 case CS42L42_DEVID_CD: 351 case CS42L42_DEVID_E: 352 case CS42L42_MCLK_STATUS: 353 case CS42L42_TRSENSE_STATUS: 354 case CS42L42_HS_DET_STATUS: 355 case CS42L42_ADC_OVFL_STATUS: 356 case CS42L42_MIXER_STATUS: 357 case CS42L42_SRC_STATUS: 358 case CS42L42_ASP_RX_STATUS: 359 case CS42L42_ASP_TX_STATUS: 360 case CS42L42_CODEC_STATUS: 361 case CS42L42_DET_INT_STATUS1: 362 case CS42L42_DET_INT_STATUS2: 363 case CS42L42_SRCPL_INT_STATUS: 364 case CS42L42_VPMON_STATUS: 365 case CS42L42_PLL_LOCK_STATUS: 366 case CS42L42_TSRS_PLUG_STATUS: 367 case CS42L42_LOAD_DET_RCSTAT: 368 case CS42L42_LOAD_DET_DONE: 369 case CS42L42_DET_STATUS1: 370 case CS42L42_DET_STATUS2: 371 return true; 372 default: 373 return false; 374 } 375 } 376 377 static const struct regmap_range_cfg cs42l42_page_range = { 378 .name = "Pages", 379 .range_min = 0, 380 .range_max = CS42L42_MAX_REGISTER, 381 .selector_reg = CS42L42_PAGE_REGISTER, 382 .selector_mask = 0xff, 383 .selector_shift = 0, 384 .window_start = 0, 385 .window_len = 256, 386 }; 387 388 static const struct regmap_config cs42l42_regmap = { 389 .reg_bits = 8, 390 .val_bits = 8, 391 392 .readable_reg = cs42l42_readable_register, 393 .volatile_reg = cs42l42_volatile_register, 394 395 .ranges = &cs42l42_page_range, 396 .num_ranges = 1, 397 398 .max_register = CS42L42_MAX_REGISTER, 399 .reg_defaults = cs42l42_reg_defaults, 400 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), 401 .cache_type = REGCACHE_RBTREE, 402 }; 403 404 static DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 100, false); 405 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); 406 407 static const char * const cs42l42_hpf_freq_text[] = { 408 "1.86Hz", "120Hz", "235Hz", "466Hz" 409 }; 410 411 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 412 CS42L42_ADC_HPF_CF_SHIFT, 413 cs42l42_hpf_freq_text); 414 415 static const char * const cs42l42_wnf3_freq_text[] = { 416 "160Hz", "180Hz", "200Hz", "220Hz", 417 "240Hz", "260Hz", "280Hz", "300Hz" 418 }; 419 420 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 421 CS42L42_ADC_WNF_CF_SHIFT, 422 cs42l42_wnf3_freq_text); 423 424 static const char * const cs42l42_wnf05_freq_text[] = { 425 "280Hz", "315Hz", "350Hz", "385Hz", 426 "420Hz", "455Hz", "490Hz", "525Hz" 427 }; 428 429 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL, 430 CS42L42_ADC_WNF_CF_SHIFT, 431 cs42l42_wnf05_freq_text); 432 433 static const struct snd_kcontrol_new cs42l42_snd_controls[] = { 434 /* ADC Volume and Filter Controls */ 435 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL, 436 CS42L42_ADC_NOTCH_DIS_SHIFT, true, false), 437 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL, 438 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), 439 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL, 440 CS42L42_ADC_INV_SHIFT, true, false), 441 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL, 442 CS42L42_ADC_DIG_BOOST_SHIFT, true, false), 443 SOC_SINGLE_SX_TLV("ADC Volume", CS42L42_ADC_VOLUME, 444 CS42L42_ADC_VOL_SHIFT, 0xA0, 0x6C, adc_tlv), 445 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL, 446 CS42L42_ADC_WNF_EN_SHIFT, true, false), 447 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL, 448 CS42L42_ADC_HPF_EN_SHIFT, true, false), 449 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum), 450 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum), 451 SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum), 452 453 /* DAC Volume and Filter Controls */ 454 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1, 455 CS42L42_DACA_INV_SHIFT, true, false), 456 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1, 457 CS42L42_DACB_INV_SHIFT, true, false), 458 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2, 459 CS42L42_DAC_HPF_EN_SHIFT, true, false), 460 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL, 461 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, 462 0x3f, 1, mixer_tlv) 463 }; 464 465 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { 466 /* Playback Path */ 467 SND_SOC_DAPM_OUTPUT("HP"), 468 SND_SOC_DAPM_DAC("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1), 469 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), 470 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH1_SHIFT, 0), 471 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, CS42L42_ASP_RX_DAI0_EN, CS42L42_ASP_RX0_CH2_SHIFT, 0), 472 473 /* Playback Requirements */ 474 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), 475 476 /* Capture Path */ 477 SND_SOC_DAPM_INPUT("HS"), 478 SND_SOC_DAPM_ADC("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1), 479 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), 480 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), 481 482 /* Capture Requirements */ 483 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), 484 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), 485 486 /* Playback/Capture Requirements */ 487 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), 488 }; 489 490 static const struct snd_soc_dapm_route cs42l42_audio_map[] = { 491 /* Playback Path */ 492 {"HP", NULL, "DAC"}, 493 {"DAC", NULL, "MIXER"}, 494 {"MIXER", NULL, "SDIN1"}, 495 {"MIXER", NULL, "SDIN2"}, 496 {"SDIN1", NULL, "Playback"}, 497 {"SDIN2", NULL, "Playback"}, 498 499 /* Playback Requirements */ 500 {"SDIN1", NULL, "ASP DAI0"}, 501 {"SDIN2", NULL, "ASP DAI0"}, 502 {"SDIN1", NULL, "SCLK"}, 503 {"SDIN2", NULL, "SCLK"}, 504 505 /* Capture Path */ 506 {"ADC", NULL, "HS"}, 507 { "SDOUT1", NULL, "ADC" }, 508 { "SDOUT2", NULL, "ADC" }, 509 { "Capture", NULL, "SDOUT1" }, 510 { "Capture", NULL, "SDOUT2" }, 511 512 /* Capture Requirements */ 513 { "SDOUT1", NULL, "ASP DAO0" }, 514 { "SDOUT2", NULL, "ASP DAO0" }, 515 { "SDOUT1", NULL, "SCLK" }, 516 { "SDOUT2", NULL, "SCLK" }, 517 { "SDOUT1", NULL, "ASP TX EN" }, 518 { "SDOUT2", NULL, "ASP TX EN" }, 519 }; 520 521 static int cs42l42_component_probe(struct snd_soc_component *component) 522 { 523 struct cs42l42_private *cs42l42 = 524 (struct cs42l42_private *)snd_soc_component_get_drvdata(component); 525 526 cs42l42->component = component; 527 528 return 0; 529 } 530 531 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = { 532 .probe = cs42l42_component_probe, 533 .dapm_widgets = cs42l42_dapm_widgets, 534 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), 535 .dapm_routes = cs42l42_audio_map, 536 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), 537 .controls = cs42l42_snd_controls, 538 .num_controls = ARRAY_SIZE(cs42l42_snd_controls), 539 .idle_bias_on = 1, 540 .endianness = 1, 541 .non_legacy_dai_naming = 1, 542 }; 543 544 struct cs42l42_pll_params { 545 u32 sclk; 546 u8 mclk_div; 547 u8 mclk_src_sel; 548 u8 sclk_prediv; 549 u8 pll_div_int; 550 u32 pll_div_frac; 551 u8 pll_mode; 552 u8 pll_divout; 553 u32 mclk_int; 554 u8 pll_cal_ratio; 555 }; 556 557 /* 558 * Common PLL Settings for given SCLK 559 * Table 4-5 from the Datasheet 560 */ 561 static const struct cs42l42_pll_params pll_ratio_table[] = { 562 { 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 }, 563 { 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 }, 564 { 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 }, 565 { 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 }, 566 { 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 }, 567 { 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 }, 568 { 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 }, 569 { 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 }, 570 { 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 }, 571 { 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 }, 572 { 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 }, 573 { 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 }, 574 { 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 }, 575 { 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 }, 576 { 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 } 577 }; 578 579 static int cs42l42_pll_config(struct snd_soc_component *component) 580 { 581 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 582 int i; 583 u32 fsync; 584 585 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { 586 if (pll_ratio_table[i].sclk == cs42l42->sclk) { 587 /* Configure the internal sample rate */ 588 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, 589 CS42L42_INTERNAL_FS_MASK, 590 ((pll_ratio_table[i].mclk_int != 591 12000000) && 592 (pll_ratio_table[i].mclk_int != 593 24000000)) << 594 CS42L42_INTERNAL_FS_SHIFT); 595 /* Set the MCLK src (PLL or SCLK) and the divide 596 * ratio 597 */ 598 snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL, 599 CS42L42_MCLK_SRC_SEL_MASK | 600 CS42L42_MCLKDIV_MASK, 601 (pll_ratio_table[i].mclk_src_sel 602 << CS42L42_MCLK_SRC_SEL_SHIFT) | 603 (pll_ratio_table[i].mclk_div << 604 CS42L42_MCLKDIV_SHIFT)); 605 /* Set up the LRCLK */ 606 fsync = cs42l42->sclk / cs42l42->srate; 607 if (((fsync * cs42l42->srate) != cs42l42->sclk) 608 || ((fsync % 2) != 0)) { 609 dev_err(component->dev, 610 "Unsupported sclk %d/sample rate %d\n", 611 cs42l42->sclk, 612 cs42l42->srate); 613 return -EINVAL; 614 } 615 /* Set the LRCLK period */ 616 snd_soc_component_update_bits(component, 617 CS42L42_FSYNC_P_LOWER, 618 CS42L42_FSYNC_PERIOD_MASK, 619 CS42L42_FRAC0_VAL(fsync - 1) << 620 CS42L42_FSYNC_PERIOD_SHIFT); 621 snd_soc_component_update_bits(component, 622 CS42L42_FSYNC_P_UPPER, 623 CS42L42_FSYNC_PERIOD_MASK, 624 CS42L42_FRAC1_VAL(fsync - 1) << 625 CS42L42_FSYNC_PERIOD_SHIFT); 626 /* Set the LRCLK to 50% duty cycle */ 627 fsync = fsync / 2; 628 snd_soc_component_update_bits(component, 629 CS42L42_FSYNC_PW_LOWER, 630 CS42L42_FSYNC_PULSE_WIDTH_MASK, 631 CS42L42_FRAC0_VAL(fsync - 1) << 632 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 633 snd_soc_component_update_bits(component, 634 CS42L42_FSYNC_PW_UPPER, 635 CS42L42_FSYNC_PULSE_WIDTH_MASK, 636 CS42L42_FRAC1_VAL(fsync - 1) << 637 CS42L42_FSYNC_PULSE_WIDTH_SHIFT); 638 snd_soc_component_update_bits(component, 639 CS42L42_ASP_FRM_CFG, 640 CS42L42_ASP_5050_MASK, 641 CS42L42_ASP_5050_MASK); 642 /* Set the frame delay to 1.0 SCLK clocks */ 643 snd_soc_component_update_bits(component, CS42L42_ASP_FRM_CFG, 644 CS42L42_ASP_FSD_MASK, 645 CS42L42_ASP_FSD_1_0 << 646 CS42L42_ASP_FSD_SHIFT); 647 /* Set the sample rates (96k or lower) */ 648 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN, 649 CS42L42_FS_EN_MASK, 650 (CS42L42_FS_EN_IASRC_96K | 651 CS42L42_FS_EN_OASRC_96K) << 652 CS42L42_FS_EN_SHIFT); 653 /* Set the input/output internal MCLK clock ~12 MHz */ 654 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK, 655 CS42L42_CLK_IASRC_SEL_MASK, 656 CS42L42_CLK_IASRC_SEL_12 << 657 CS42L42_CLK_IASRC_SEL_SHIFT); 658 snd_soc_component_update_bits(component, 659 CS42L42_OUT_ASRC_CLK, 660 CS42L42_CLK_OASRC_SEL_MASK, 661 CS42L42_CLK_OASRC_SEL_12 << 662 CS42L42_CLK_OASRC_SEL_SHIFT); 663 if (pll_ratio_table[i].mclk_src_sel == 0) { 664 /* Pass the clock straight through */ 665 snd_soc_component_update_bits(component, 666 CS42L42_PLL_CTL1, 667 CS42L42_PLL_START_MASK, 0); 668 } else { 669 /* Configure PLL per table 4-5 */ 670 snd_soc_component_update_bits(component, 671 CS42L42_PLL_DIV_CFG1, 672 CS42L42_SCLK_PREDIV_MASK, 673 pll_ratio_table[i].sclk_prediv 674 << CS42L42_SCLK_PREDIV_SHIFT); 675 snd_soc_component_update_bits(component, 676 CS42L42_PLL_DIV_INT, 677 CS42L42_PLL_DIV_INT_MASK, 678 pll_ratio_table[i].pll_div_int 679 << CS42L42_PLL_DIV_INT_SHIFT); 680 snd_soc_component_update_bits(component, 681 CS42L42_PLL_DIV_FRAC0, 682 CS42L42_PLL_DIV_FRAC_MASK, 683 CS42L42_FRAC0_VAL( 684 pll_ratio_table[i].pll_div_frac) 685 << CS42L42_PLL_DIV_FRAC_SHIFT); 686 snd_soc_component_update_bits(component, 687 CS42L42_PLL_DIV_FRAC1, 688 CS42L42_PLL_DIV_FRAC_MASK, 689 CS42L42_FRAC1_VAL( 690 pll_ratio_table[i].pll_div_frac) 691 << CS42L42_PLL_DIV_FRAC_SHIFT); 692 snd_soc_component_update_bits(component, 693 CS42L42_PLL_DIV_FRAC2, 694 CS42L42_PLL_DIV_FRAC_MASK, 695 CS42L42_FRAC2_VAL( 696 pll_ratio_table[i].pll_div_frac) 697 << CS42L42_PLL_DIV_FRAC_SHIFT); 698 snd_soc_component_update_bits(component, 699 CS42L42_PLL_CTL4, 700 CS42L42_PLL_MODE_MASK, 701 pll_ratio_table[i].pll_mode 702 << CS42L42_PLL_MODE_SHIFT); 703 snd_soc_component_update_bits(component, 704 CS42L42_PLL_CTL3, 705 CS42L42_PLL_DIVOUT_MASK, 706 pll_ratio_table[i].pll_divout 707 << CS42L42_PLL_DIVOUT_SHIFT); 708 snd_soc_component_update_bits(component, 709 CS42L42_PLL_CAL_RATIO, 710 CS42L42_PLL_CAL_RATIO_MASK, 711 pll_ratio_table[i].pll_cal_ratio 712 << CS42L42_PLL_CAL_RATIO_SHIFT); 713 } 714 return 0; 715 } 716 } 717 718 return -EINVAL; 719 } 720 721 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 722 { 723 struct snd_soc_component *component = codec_dai->component; 724 u32 asp_cfg_val = 0; 725 726 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 727 case SND_SOC_DAIFMT_CBS_CFM: 728 asp_cfg_val |= CS42L42_ASP_MASTER_MODE << 729 CS42L42_ASP_MODE_SHIFT; 730 break; 731 case SND_SOC_DAIFMT_CBS_CFS: 732 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << 733 CS42L42_ASP_MODE_SHIFT; 734 break; 735 default: 736 return -EINVAL; 737 } 738 739 /* interface format */ 740 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 741 case SND_SOC_DAIFMT_I2S: 742 case SND_SOC_DAIFMT_LEFT_J: 743 break; 744 default: 745 return -EINVAL; 746 } 747 748 /* Bitclock/frame inversion */ 749 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 750 case SND_SOC_DAIFMT_NB_NF: 751 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 752 break; 753 case SND_SOC_DAIFMT_NB_IF: 754 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; 755 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 756 break; 757 case SND_SOC_DAIFMT_IB_NF: 758 break; 759 case SND_SOC_DAIFMT_IB_IF: 760 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; 761 break; 762 } 763 764 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | 765 CS42L42_ASP_SCPOL_MASK | 766 CS42L42_ASP_LCPOL_MASK, 767 asp_cfg_val); 768 769 return 0; 770 } 771 772 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, 773 struct snd_pcm_hw_params *params, 774 struct snd_soc_dai *dai) 775 { 776 struct snd_soc_component *component = dai->component; 777 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 778 unsigned int channels = params_channels(params); 779 unsigned int width = (params_width(params) / 8) - 1; 780 unsigned int val = 0; 781 782 cs42l42->srate = params_rate(params); 783 784 switch(substream->stream) { 785 case SNDRV_PCM_STREAM_CAPTURE: 786 if (channels == 2) { 787 val |= CS42L42_ASP_TX_CH2_AP_MASK; 788 val |= width << CS42L42_ASP_TX_CH2_RES_SHIFT; 789 } 790 val |= width << CS42L42_ASP_TX_CH1_RES_SHIFT; 791 792 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, 793 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | 794 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); 795 break; 796 case SNDRV_PCM_STREAM_PLAYBACK: 797 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; 798 /* channel 1 on low LRCLK */ 799 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, 800 CS42L42_ASP_RX_CH_AP_MASK | 801 CS42L42_ASP_RX_CH_RES_MASK, val); 802 /* Channel 2 on high LRCLK */ 803 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; 804 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, 805 CS42L42_ASP_RX_CH_AP_MASK | 806 CS42L42_ASP_RX_CH_RES_MASK, val); 807 break; 808 default: 809 break; 810 } 811 812 return cs42l42_pll_config(component); 813 } 814 815 static int cs42l42_set_sysclk(struct snd_soc_dai *dai, 816 int clk_id, unsigned int freq, int dir) 817 { 818 struct snd_soc_component *component = dai->component; 819 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 820 821 cs42l42->sclk = freq; 822 823 return 0; 824 } 825 826 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 827 { 828 struct snd_soc_component *component = dai->component; 829 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component); 830 unsigned int regval; 831 u8 fullScaleVol; 832 833 if (mute) { 834 /* Mute the headphone */ 835 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 836 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 837 CS42L42_HP_ANA_AMUTE_MASK | 838 CS42L42_HP_ANA_BMUTE_MASK, 839 CS42L42_HP_ANA_AMUTE_MASK | 840 CS42L42_HP_ANA_BMUTE_MASK); 841 842 cs42l42->stream_use &= ~(1 << stream); 843 if(!cs42l42->stream_use) { 844 /* 845 * Switch to the internal oscillator. 846 * SCLK must remain running until after this clock switch. 847 * Without a source of clock the I2C bus doesn't work. 848 */ 849 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH, 850 CS42L42_SCLK_PRESENT_MASK, 0); 851 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 852 CS42L42_PLL_START_MASK, 0); 853 } 854 } else { 855 if (!cs42l42->stream_use) { 856 /* SCLK must be running before codec unmute */ 857 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, 858 CS42L42_PLL_START_MASK, 1); 859 860 /* Mark SCLK as present, turn off internal oscillator */ 861 snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH, 862 CS42L42_SCLK_PRESENT_MASK, 863 CS42L42_SCLK_PRESENT_MASK); 864 } 865 cs42l42->stream_use |= 1 << stream; 866 867 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 868 /* Read the headphone load */ 869 regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT); 870 if (((regval & CS42L42_RLA_STAT_MASK) >> CS42L42_RLA_STAT_SHIFT) == 871 CS42L42_RLA_STAT_15_OHM) { 872 fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK; 873 } else { 874 fullScaleVol = 0; 875 } 876 877 /* Un-mute the headphone, set the full scale volume flag */ 878 snd_soc_component_update_bits(component, CS42L42_HP_CTL, 879 CS42L42_HP_ANA_AMUTE_MASK | 880 CS42L42_HP_ANA_BMUTE_MASK | 881 CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol); 882 } 883 } 884 885 return 0; 886 } 887 888 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 889 SNDRV_PCM_FMTBIT_S24_LE |\ 890 SNDRV_PCM_FMTBIT_S32_LE ) 891 892 893 static const struct snd_soc_dai_ops cs42l42_ops = { 894 .hw_params = cs42l42_pcm_hw_params, 895 .set_fmt = cs42l42_set_dai_fmt, 896 .set_sysclk = cs42l42_set_sysclk, 897 .mute_stream = cs42l42_mute_stream, 898 }; 899 900 static struct snd_soc_dai_driver cs42l42_dai = { 901 .name = "cs42l42", 902 .playback = { 903 .stream_name = "Playback", 904 .channels_min = 1, 905 .channels_max = 2, 906 .rates = SNDRV_PCM_RATE_8000_192000, 907 .formats = CS42L42_FORMATS, 908 }, 909 .capture = { 910 .stream_name = "Capture", 911 .channels_min = 1, 912 .channels_max = 2, 913 .rates = SNDRV_PCM_RATE_8000_192000, 914 .formats = CS42L42_FORMATS, 915 }, 916 .ops = &cs42l42_ops, 917 }; 918 919 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) 920 { 921 unsigned int hs_det_status; 922 unsigned int int_status; 923 924 /* Mask the auto detect interrupt */ 925 regmap_update_bits(cs42l42->regmap, 926 CS42L42_CODEC_INT_MASK, 927 CS42L42_PDN_DONE_MASK | 928 CS42L42_HSDET_AUTO_DONE_MASK, 929 (1 << CS42L42_PDN_DONE_SHIFT) | 930 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 931 932 /* Set hs detect to automatic, disabled mode */ 933 regmap_update_bits(cs42l42->regmap, 934 CS42L42_HSDET_CTL2, 935 CS42L42_HSDET_CTRL_MASK | 936 CS42L42_HSDET_SET_MASK | 937 CS42L42_HSBIAS_REF_MASK | 938 CS42L42_HSDET_AUTO_TIME_MASK, 939 (2 << CS42L42_HSDET_CTRL_SHIFT) | 940 (2 << CS42L42_HSDET_SET_SHIFT) | 941 (0 << CS42L42_HSBIAS_REF_SHIFT) | 942 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 943 944 /* Read and save the hs detection result */ 945 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status); 946 947 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> 948 CS42L42_HSDET_TYPE_SHIFT; 949 950 /* Set up button detection */ 951 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || 952 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { 953 /* Set auto HS bias settings to default */ 954 regmap_update_bits(cs42l42->regmap, 955 CS42L42_HSBIAS_SC_AUTOCTL, 956 CS42L42_HSBIAS_SENSE_EN_MASK | 957 CS42L42_AUTO_HSBIAS_HIZ_MASK | 958 CS42L42_TIP_SENSE_EN_MASK | 959 CS42L42_HSBIAS_SENSE_TRIP_MASK, 960 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 961 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 962 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 963 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 964 965 /* Set up hs detect level sensitivity */ 966 regmap_update_bits(cs42l42->regmap, 967 CS42L42_MIC_DET_CTL1, 968 CS42L42_LATCH_TO_VP_MASK | 969 CS42L42_EVENT_STAT_SEL_MASK | 970 CS42L42_HS_DET_LEVEL_MASK, 971 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 972 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 973 (cs42l42->bias_thresholds[0] << 974 CS42L42_HS_DET_LEVEL_SHIFT)); 975 976 /* Set auto HS bias settings to default */ 977 regmap_update_bits(cs42l42->regmap, 978 CS42L42_HSBIAS_SC_AUTOCTL, 979 CS42L42_HSBIAS_SENSE_EN_MASK | 980 CS42L42_AUTO_HSBIAS_HIZ_MASK | 981 CS42L42_TIP_SENSE_EN_MASK | 982 CS42L42_HSBIAS_SENSE_TRIP_MASK, 983 (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 984 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 985 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 986 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 987 988 /* Turn on level detect circuitry */ 989 regmap_update_bits(cs42l42->regmap, 990 CS42L42_MISC_DET_CTL, 991 CS42L42_DETECT_MODE_MASK | 992 CS42L42_HSBIAS_CTL_MASK | 993 CS42L42_PDN_MIC_LVL_DET_MASK, 994 (0 << CS42L42_DETECT_MODE_SHIFT) | 995 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 996 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 997 998 msleep(cs42l42->btn_det_init_dbnce); 999 1000 /* Clear any button interrupts before unmasking them */ 1001 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1002 &int_status); 1003 1004 /* Unmask button detect interrupts */ 1005 regmap_update_bits(cs42l42->regmap, 1006 CS42L42_DET_INT2_MASK, 1007 CS42L42_M_DETECT_TF_MASK | 1008 CS42L42_M_DETECT_FT_MASK | 1009 CS42L42_M_HSBIAS_HIZ_MASK | 1010 CS42L42_M_SHORT_RLS_MASK | 1011 CS42L42_M_SHORT_DET_MASK, 1012 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1013 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1014 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1015 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1016 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1017 } else { 1018 /* Make sure button detect and HS bias circuits are off */ 1019 regmap_update_bits(cs42l42->regmap, 1020 CS42L42_MISC_DET_CTL, 1021 CS42L42_DETECT_MODE_MASK | 1022 CS42L42_HSBIAS_CTL_MASK | 1023 CS42L42_PDN_MIC_LVL_DET_MASK, 1024 (0 << CS42L42_DETECT_MODE_SHIFT) | 1025 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1026 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1027 } 1028 1029 regmap_update_bits(cs42l42->regmap, 1030 CS42L42_DAC_CTL2, 1031 CS42L42_HPOUT_PULLDOWN_MASK | 1032 CS42L42_HPOUT_LOAD_MASK | 1033 CS42L42_HPOUT_CLAMP_MASK | 1034 CS42L42_DAC_HPF_EN_MASK | 1035 CS42L42_DAC_MON_EN_MASK, 1036 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1037 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1038 (0 << CS42L42_HPOUT_CLAMP_SHIFT) | 1039 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1040 (0 << CS42L42_DAC_MON_EN_SHIFT)); 1041 1042 /* Unmask tip sense interrupts */ 1043 regmap_update_bits(cs42l42->regmap, 1044 CS42L42_TSRS_PLUG_INT_MASK, 1045 CS42L42_RS_PLUG_MASK | 1046 CS42L42_RS_UNPLUG_MASK | 1047 CS42L42_TS_PLUG_MASK | 1048 CS42L42_TS_UNPLUG_MASK, 1049 (1 << CS42L42_RS_PLUG_SHIFT) | 1050 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1051 (0 << CS42L42_TS_PLUG_SHIFT) | 1052 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1053 } 1054 1055 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) 1056 { 1057 /* Mask tip sense interrupts */ 1058 regmap_update_bits(cs42l42->regmap, 1059 CS42L42_TSRS_PLUG_INT_MASK, 1060 CS42L42_RS_PLUG_MASK | 1061 CS42L42_RS_UNPLUG_MASK | 1062 CS42L42_TS_PLUG_MASK | 1063 CS42L42_TS_UNPLUG_MASK, 1064 (1 << CS42L42_RS_PLUG_SHIFT) | 1065 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1066 (1 << CS42L42_TS_PLUG_SHIFT) | 1067 (1 << CS42L42_TS_UNPLUG_SHIFT)); 1068 1069 /* Make sure button detect and HS bias circuits are off */ 1070 regmap_update_bits(cs42l42->regmap, 1071 CS42L42_MISC_DET_CTL, 1072 CS42L42_DETECT_MODE_MASK | 1073 CS42L42_HSBIAS_CTL_MASK | 1074 CS42L42_PDN_MIC_LVL_DET_MASK, 1075 (0 << CS42L42_DETECT_MODE_SHIFT) | 1076 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1077 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1078 1079 /* Set auto HS bias settings to default */ 1080 regmap_update_bits(cs42l42->regmap, 1081 CS42L42_HSBIAS_SC_AUTOCTL, 1082 CS42L42_HSBIAS_SENSE_EN_MASK | 1083 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1084 CS42L42_TIP_SENSE_EN_MASK | 1085 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1086 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1087 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1088 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1089 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1090 1091 /* Set hs detect to manual, disabled mode */ 1092 regmap_update_bits(cs42l42->regmap, 1093 CS42L42_HSDET_CTL2, 1094 CS42L42_HSDET_CTRL_MASK | 1095 CS42L42_HSDET_SET_MASK | 1096 CS42L42_HSBIAS_REF_MASK | 1097 CS42L42_HSDET_AUTO_TIME_MASK, 1098 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1099 (2 << CS42L42_HSDET_SET_SHIFT) | 1100 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1101 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1102 1103 regmap_update_bits(cs42l42->regmap, 1104 CS42L42_DAC_CTL2, 1105 CS42L42_HPOUT_PULLDOWN_MASK | 1106 CS42L42_HPOUT_LOAD_MASK | 1107 CS42L42_HPOUT_CLAMP_MASK | 1108 CS42L42_DAC_HPF_EN_MASK | 1109 CS42L42_DAC_MON_EN_MASK, 1110 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | 1111 (0 << CS42L42_HPOUT_LOAD_SHIFT) | 1112 (1 << CS42L42_HPOUT_CLAMP_SHIFT) | 1113 (1 << CS42L42_DAC_HPF_EN_SHIFT) | 1114 (1 << CS42L42_DAC_MON_EN_SHIFT)); 1115 1116 /* Power up HS bias to 2.7V */ 1117 regmap_update_bits(cs42l42->regmap, 1118 CS42L42_MISC_DET_CTL, 1119 CS42L42_DETECT_MODE_MASK | 1120 CS42L42_HSBIAS_CTL_MASK | 1121 CS42L42_PDN_MIC_LVL_DET_MASK, 1122 (0 << CS42L42_DETECT_MODE_SHIFT) | 1123 (3 << CS42L42_HSBIAS_CTL_SHIFT) | 1124 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1125 1126 /* Wait for HS bias to ramp up */ 1127 msleep(cs42l42->hs_bias_ramp_time); 1128 1129 /* Unmask auto detect interrupt */ 1130 regmap_update_bits(cs42l42->regmap, 1131 CS42L42_CODEC_INT_MASK, 1132 CS42L42_PDN_DONE_MASK | 1133 CS42L42_HSDET_AUTO_DONE_MASK, 1134 (1 << CS42L42_PDN_DONE_SHIFT) | 1135 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1136 1137 /* Set hs detect to automatic, enabled mode */ 1138 regmap_update_bits(cs42l42->regmap, 1139 CS42L42_HSDET_CTL2, 1140 CS42L42_HSDET_CTRL_MASK | 1141 CS42L42_HSDET_SET_MASK | 1142 CS42L42_HSBIAS_REF_MASK | 1143 CS42L42_HSDET_AUTO_TIME_MASK, 1144 (3 << CS42L42_HSDET_CTRL_SHIFT) | 1145 (2 << CS42L42_HSDET_SET_SHIFT) | 1146 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1147 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1148 } 1149 1150 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) 1151 { 1152 /* Mask button detect interrupts */ 1153 regmap_update_bits(cs42l42->regmap, 1154 CS42L42_DET_INT2_MASK, 1155 CS42L42_M_DETECT_TF_MASK | 1156 CS42L42_M_DETECT_FT_MASK | 1157 CS42L42_M_HSBIAS_HIZ_MASK | 1158 CS42L42_M_SHORT_RLS_MASK | 1159 CS42L42_M_SHORT_DET_MASK, 1160 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1161 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1162 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1163 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1164 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1165 1166 /* Ground HS bias */ 1167 regmap_update_bits(cs42l42->regmap, 1168 CS42L42_MISC_DET_CTL, 1169 CS42L42_DETECT_MODE_MASK | 1170 CS42L42_HSBIAS_CTL_MASK | 1171 CS42L42_PDN_MIC_LVL_DET_MASK, 1172 (0 << CS42L42_DETECT_MODE_SHIFT) | 1173 (1 << CS42L42_HSBIAS_CTL_SHIFT) | 1174 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); 1175 1176 /* Set auto HS bias settings to default */ 1177 regmap_update_bits(cs42l42->regmap, 1178 CS42L42_HSBIAS_SC_AUTOCTL, 1179 CS42L42_HSBIAS_SENSE_EN_MASK | 1180 CS42L42_AUTO_HSBIAS_HIZ_MASK | 1181 CS42L42_TIP_SENSE_EN_MASK | 1182 CS42L42_HSBIAS_SENSE_TRIP_MASK, 1183 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | 1184 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | 1185 (0 << CS42L42_TIP_SENSE_EN_SHIFT) | 1186 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); 1187 1188 /* Set hs detect to manual, disabled mode */ 1189 regmap_update_bits(cs42l42->regmap, 1190 CS42L42_HSDET_CTL2, 1191 CS42L42_HSDET_CTRL_MASK | 1192 CS42L42_HSDET_SET_MASK | 1193 CS42L42_HSBIAS_REF_MASK | 1194 CS42L42_HSDET_AUTO_TIME_MASK, 1195 (0 << CS42L42_HSDET_CTRL_SHIFT) | 1196 (2 << CS42L42_HSDET_SET_SHIFT) | 1197 (0 << CS42L42_HSBIAS_REF_SHIFT) | 1198 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 1199 } 1200 1201 static void cs42l42_handle_button_press(struct cs42l42_private *cs42l42) 1202 { 1203 int bias_level; 1204 unsigned int detect_status; 1205 1206 /* Mask button detect interrupts */ 1207 regmap_update_bits(cs42l42->regmap, 1208 CS42L42_DET_INT2_MASK, 1209 CS42L42_M_DETECT_TF_MASK | 1210 CS42L42_M_DETECT_FT_MASK | 1211 CS42L42_M_HSBIAS_HIZ_MASK | 1212 CS42L42_M_SHORT_RLS_MASK | 1213 CS42L42_M_SHORT_DET_MASK, 1214 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1215 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1216 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1217 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1218 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1219 1220 usleep_range(cs42l42->btn_det_event_dbnce * 1000, 1221 cs42l42->btn_det_event_dbnce * 2000); 1222 1223 /* Test all 4 level detect biases */ 1224 bias_level = 1; 1225 do { 1226 /* Adjust button detect level sensitivity */ 1227 regmap_update_bits(cs42l42->regmap, 1228 CS42L42_MIC_DET_CTL1, 1229 CS42L42_LATCH_TO_VP_MASK | 1230 CS42L42_EVENT_STAT_SEL_MASK | 1231 CS42L42_HS_DET_LEVEL_MASK, 1232 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1233 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1234 (cs42l42->bias_thresholds[bias_level] << 1235 CS42L42_HS_DET_LEVEL_SHIFT)); 1236 1237 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2, 1238 &detect_status); 1239 } while ((detect_status & CS42L42_HS_TRUE_MASK) && 1240 (++bias_level < CS42L42_NUM_BIASES)); 1241 1242 switch (bias_level) { 1243 case 1: /* Function C button press */ 1244 dev_dbg(cs42l42->component->dev, "Function C button press\n"); 1245 break; 1246 case 2: /* Function B button press */ 1247 dev_dbg(cs42l42->component->dev, "Function B button press\n"); 1248 break; 1249 case 3: /* Function D button press */ 1250 dev_dbg(cs42l42->component->dev, "Function D button press\n"); 1251 break; 1252 case 4: /* Function A button press */ 1253 dev_dbg(cs42l42->component->dev, "Function A button press\n"); 1254 break; 1255 } 1256 1257 /* Set button detect level sensitivity back to default */ 1258 regmap_update_bits(cs42l42->regmap, 1259 CS42L42_MIC_DET_CTL1, 1260 CS42L42_LATCH_TO_VP_MASK | 1261 CS42L42_EVENT_STAT_SEL_MASK | 1262 CS42L42_HS_DET_LEVEL_MASK, 1263 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1264 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1265 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); 1266 1267 /* Clear any button interrupts before unmasking them */ 1268 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2, 1269 &detect_status); 1270 1271 /* Unmask button detect interrupts */ 1272 regmap_update_bits(cs42l42->regmap, 1273 CS42L42_DET_INT2_MASK, 1274 CS42L42_M_DETECT_TF_MASK | 1275 CS42L42_M_DETECT_FT_MASK | 1276 CS42L42_M_HSBIAS_HIZ_MASK | 1277 CS42L42_M_SHORT_RLS_MASK | 1278 CS42L42_M_SHORT_DET_MASK, 1279 (0 << CS42L42_M_DETECT_TF_SHIFT) | 1280 (0 << CS42L42_M_DETECT_FT_SHIFT) | 1281 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1282 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1283 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1284 } 1285 1286 struct cs42l42_irq_params { 1287 u16 status_addr; 1288 u16 mask_addr; 1289 u8 mask; 1290 }; 1291 1292 static const struct cs42l42_irq_params irq_params_table[] = { 1293 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, 1294 CS42L42_ADC_OVFL_VAL_MASK}, 1295 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, 1296 CS42L42_MIXER_VAL_MASK}, 1297 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, 1298 CS42L42_SRC_VAL_MASK}, 1299 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, 1300 CS42L42_ASP_RX_VAL_MASK}, 1301 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, 1302 CS42L42_ASP_TX_VAL_MASK}, 1303 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, 1304 CS42L42_CODEC_VAL_MASK}, 1305 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, 1306 CS42L42_DET_INT_VAL1_MASK}, 1307 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, 1308 CS42L42_DET_INT_VAL2_MASK}, 1309 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, 1310 CS42L42_SRCPL_VAL_MASK}, 1311 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, 1312 CS42L42_VPMON_VAL_MASK}, 1313 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, 1314 CS42L42_PLL_LOCK_VAL_MASK}, 1315 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, 1316 CS42L42_TSRS_PLUG_VAL_MASK} 1317 }; 1318 1319 static irqreturn_t cs42l42_irq_thread(int irq, void *data) 1320 { 1321 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; 1322 struct snd_soc_component *component = cs42l42->component; 1323 unsigned int stickies[12]; 1324 unsigned int masks[12]; 1325 unsigned int current_plug_status; 1326 unsigned int current_button_status; 1327 unsigned int i; 1328 1329 /* Read sticky registers to clear interurpt */ 1330 for (i = 0; i < ARRAY_SIZE(stickies); i++) { 1331 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr, 1332 &(stickies[i])); 1333 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr, 1334 &(masks[i])); 1335 stickies[i] = stickies[i] & (~masks[i]) & 1336 irq_params_table[i].mask; 1337 } 1338 1339 /* Read tip sense status before handling type detect */ 1340 current_plug_status = (stickies[11] & 1341 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1342 CS42L42_TS_PLUG_SHIFT; 1343 1344 /* Read button sense status */ 1345 current_button_status = stickies[7] & 1346 (CS42L42_M_DETECT_TF_MASK | 1347 CS42L42_M_DETECT_FT_MASK | 1348 CS42L42_M_HSBIAS_HIZ_MASK); 1349 1350 /* Check auto-detect status */ 1351 if ((~masks[5]) & irq_params_table[5].mask) { 1352 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { 1353 cs42l42_process_hs_type_detect(cs42l42); 1354 dev_dbg(component->dev, 1355 "Auto detect done (%d)\n", 1356 cs42l42->hs_type); 1357 } 1358 } 1359 1360 /* Check tip sense status */ 1361 if ((~masks[11]) & irq_params_table[11].mask) { 1362 switch (current_plug_status) { 1363 case CS42L42_TS_PLUG: 1364 if (cs42l42->plug_state != CS42L42_TS_PLUG) { 1365 cs42l42->plug_state = CS42L42_TS_PLUG; 1366 cs42l42_init_hs_type_detect(cs42l42); 1367 } 1368 break; 1369 1370 case CS42L42_TS_UNPLUG: 1371 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { 1372 cs42l42->plug_state = CS42L42_TS_UNPLUG; 1373 cs42l42_cancel_hs_type_detect(cs42l42); 1374 dev_dbg(component->dev, 1375 "Unplug event\n"); 1376 } 1377 break; 1378 1379 default: 1380 if (cs42l42->plug_state != CS42L42_TS_TRANS) 1381 cs42l42->plug_state = CS42L42_TS_TRANS; 1382 } 1383 } 1384 1385 /* Check button detect status */ 1386 if ((~masks[7]) & irq_params_table[7].mask) { 1387 if (!(current_button_status & 1388 CS42L42_M_HSBIAS_HIZ_MASK)) { 1389 1390 if (current_button_status & 1391 CS42L42_M_DETECT_TF_MASK) { 1392 dev_dbg(component->dev, 1393 "Button released\n"); 1394 } else if (current_button_status & 1395 CS42L42_M_DETECT_FT_MASK) { 1396 cs42l42_handle_button_press(cs42l42); 1397 } 1398 } 1399 } 1400 1401 return IRQ_HANDLED; 1402 } 1403 1404 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) 1405 { 1406 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, 1407 CS42L42_ADC_OVFL_MASK, 1408 (1 << CS42L42_ADC_OVFL_SHIFT)); 1409 1410 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK, 1411 CS42L42_MIX_CHB_OVFL_MASK | 1412 CS42L42_MIX_CHA_OVFL_MASK | 1413 CS42L42_EQ_OVFL_MASK | 1414 CS42L42_EQ_BIQUAD_OVFL_MASK, 1415 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | 1416 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | 1417 (1 << CS42L42_EQ_OVFL_SHIFT) | 1418 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); 1419 1420 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK, 1421 CS42L42_SRC_ILK_MASK | 1422 CS42L42_SRC_OLK_MASK | 1423 CS42L42_SRC_IUNLK_MASK | 1424 CS42L42_SRC_OUNLK_MASK, 1425 (1 << CS42L42_SRC_ILK_SHIFT) | 1426 (1 << CS42L42_SRC_OLK_SHIFT) | 1427 (1 << CS42L42_SRC_IUNLK_SHIFT) | 1428 (1 << CS42L42_SRC_OUNLK_SHIFT)); 1429 1430 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, 1431 CS42L42_ASPRX_NOLRCK_MASK | 1432 CS42L42_ASPRX_EARLY_MASK | 1433 CS42L42_ASPRX_LATE_MASK | 1434 CS42L42_ASPRX_ERROR_MASK | 1435 CS42L42_ASPRX_OVLD_MASK, 1436 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | 1437 (1 << CS42L42_ASPRX_EARLY_SHIFT) | 1438 (1 << CS42L42_ASPRX_LATE_SHIFT) | 1439 (1 << CS42L42_ASPRX_ERROR_SHIFT) | 1440 (1 << CS42L42_ASPRX_OVLD_SHIFT)); 1441 1442 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, 1443 CS42L42_ASPTX_NOLRCK_MASK | 1444 CS42L42_ASPTX_EARLY_MASK | 1445 CS42L42_ASPTX_LATE_MASK | 1446 CS42L42_ASPTX_SMERROR_MASK, 1447 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | 1448 (1 << CS42L42_ASPTX_EARLY_SHIFT) | 1449 (1 << CS42L42_ASPTX_LATE_SHIFT) | 1450 (1 << CS42L42_ASPTX_SMERROR_SHIFT)); 1451 1452 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 1453 CS42L42_PDN_DONE_MASK | 1454 CS42L42_HSDET_AUTO_DONE_MASK, 1455 (1 << CS42L42_PDN_DONE_SHIFT) | 1456 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); 1457 1458 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK, 1459 CS42L42_SRCPL_ADC_LK_MASK | 1460 CS42L42_SRCPL_DAC_LK_MASK | 1461 CS42L42_SRCPL_ADC_UNLK_MASK | 1462 CS42L42_SRCPL_DAC_UNLK_MASK, 1463 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | 1464 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | 1465 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | 1466 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); 1467 1468 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK, 1469 CS42L42_TIP_SENSE_UNPLUG_MASK | 1470 CS42L42_TIP_SENSE_PLUG_MASK | 1471 CS42L42_HSBIAS_SENSE_MASK, 1472 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | 1473 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | 1474 (1 << CS42L42_HSBIAS_SENSE_SHIFT)); 1475 1476 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK, 1477 CS42L42_M_DETECT_TF_MASK | 1478 CS42L42_M_DETECT_FT_MASK | 1479 CS42L42_M_HSBIAS_HIZ_MASK | 1480 CS42L42_M_SHORT_RLS_MASK | 1481 CS42L42_M_SHORT_DET_MASK, 1482 (1 << CS42L42_M_DETECT_TF_SHIFT) | 1483 (1 << CS42L42_M_DETECT_FT_SHIFT) | 1484 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | 1485 (1 << CS42L42_M_SHORT_RLS_SHIFT) | 1486 (1 << CS42L42_M_SHORT_DET_SHIFT)); 1487 1488 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK, 1489 CS42L42_VPMON_MASK, 1490 (1 << CS42L42_VPMON_SHIFT)); 1491 1492 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, 1493 CS42L42_PLL_LOCK_MASK, 1494 (1 << CS42L42_PLL_LOCK_SHIFT)); 1495 1496 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 1497 CS42L42_RS_PLUG_MASK | 1498 CS42L42_RS_UNPLUG_MASK | 1499 CS42L42_TS_PLUG_MASK | 1500 CS42L42_TS_UNPLUG_MASK, 1501 (1 << CS42L42_RS_PLUG_SHIFT) | 1502 (1 << CS42L42_RS_UNPLUG_SHIFT) | 1503 (0 << CS42L42_TS_PLUG_SHIFT) | 1504 (0 << CS42L42_TS_UNPLUG_SHIFT)); 1505 } 1506 1507 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) 1508 { 1509 unsigned int reg; 1510 1511 cs42l42->hs_type = CS42L42_PLUG_INVALID; 1512 1513 /* Latch analog controls to VP power domain */ 1514 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1, 1515 CS42L42_LATCH_TO_VP_MASK | 1516 CS42L42_EVENT_STAT_SEL_MASK | 1517 CS42L42_HS_DET_LEVEL_MASK, 1518 (1 << CS42L42_LATCH_TO_VP_SHIFT) | 1519 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | 1520 (cs42l42->bias_thresholds[0] << 1521 CS42L42_HS_DET_LEVEL_SHIFT)); 1522 1523 /* Remove ground noise-suppression clamps */ 1524 regmap_update_bits(cs42l42->regmap, 1525 CS42L42_HS_CLAMP_DISABLE, 1526 CS42L42_HS_CLAMP_DISABLE_MASK, 1527 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); 1528 1529 /* Enable the tip sense circuit */ 1530 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL, 1531 CS42L42_TIP_SENSE_CTRL_MASK | 1532 CS42L42_TIP_SENSE_INV_MASK | 1533 CS42L42_TIP_SENSE_DEBOUNCE_MASK, 1534 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | 1535 (0 << CS42L42_TIP_SENSE_INV_SHIFT) | 1536 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); 1537 1538 /* Save the initial status of the tip sense */ 1539 regmap_read(cs42l42->regmap, 1540 CS42L42_TSRS_PLUG_STATUS, 1541 ®); 1542 cs42l42->plug_state = (((char) reg) & 1543 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> 1544 CS42L42_TS_PLUG_SHIFT; 1545 } 1546 1547 static const unsigned int threshold_defaults[] = { 1548 CS42L42_HS_DET_LEVEL_15, 1549 CS42L42_HS_DET_LEVEL_8, 1550 CS42L42_HS_DET_LEVEL_4, 1551 CS42L42_HS_DET_LEVEL_1 1552 }; 1553 1554 static int cs42l42_handle_device_data(struct i2c_client *i2c_client, 1555 struct cs42l42_private *cs42l42) 1556 { 1557 struct device_node *np = i2c_client->dev.of_node; 1558 unsigned int val; 1559 unsigned int thresholds[CS42L42_NUM_BIASES]; 1560 int ret; 1561 int i; 1562 1563 ret = of_property_read_u32(np, "cirrus,ts-inv", &val); 1564 1565 if (!ret) { 1566 switch (val) { 1567 case CS42L42_TS_INV_EN: 1568 case CS42L42_TS_INV_DIS: 1569 cs42l42->ts_inv = val; 1570 break; 1571 default: 1572 dev_err(&i2c_client->dev, 1573 "Wrong cirrus,ts-inv DT value %d\n", 1574 val); 1575 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1576 } 1577 } else { 1578 cs42l42->ts_inv = CS42L42_TS_INV_DIS; 1579 } 1580 1581 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1582 CS42L42_TS_INV_MASK, 1583 (cs42l42->ts_inv << CS42L42_TS_INV_SHIFT)); 1584 1585 ret = of_property_read_u32(np, "cirrus,ts-dbnc-rise", &val); 1586 1587 if (!ret) { 1588 switch (val) { 1589 case CS42L42_TS_DBNCE_0: 1590 case CS42L42_TS_DBNCE_125: 1591 case CS42L42_TS_DBNCE_250: 1592 case CS42L42_TS_DBNCE_500: 1593 case CS42L42_TS_DBNCE_750: 1594 case CS42L42_TS_DBNCE_1000: 1595 case CS42L42_TS_DBNCE_1250: 1596 case CS42L42_TS_DBNCE_1500: 1597 cs42l42->ts_dbnc_rise = val; 1598 break; 1599 default: 1600 dev_err(&i2c_client->dev, 1601 "Wrong cirrus,ts-dbnc-rise DT value %d\n", 1602 val); 1603 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1604 } 1605 } else { 1606 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; 1607 } 1608 1609 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1610 CS42L42_TS_RISE_DBNCE_TIME_MASK, 1611 (cs42l42->ts_dbnc_rise << 1612 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); 1613 1614 ret = of_property_read_u32(np, "cirrus,ts-dbnc-fall", &val); 1615 1616 if (!ret) { 1617 switch (val) { 1618 case CS42L42_TS_DBNCE_0: 1619 case CS42L42_TS_DBNCE_125: 1620 case CS42L42_TS_DBNCE_250: 1621 case CS42L42_TS_DBNCE_500: 1622 case CS42L42_TS_DBNCE_750: 1623 case CS42L42_TS_DBNCE_1000: 1624 case CS42L42_TS_DBNCE_1250: 1625 case CS42L42_TS_DBNCE_1500: 1626 cs42l42->ts_dbnc_fall = val; 1627 break; 1628 default: 1629 dev_err(&i2c_client->dev, 1630 "Wrong cirrus,ts-dbnc-fall DT value %d\n", 1631 val); 1632 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1633 } 1634 } else { 1635 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; 1636 } 1637 1638 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL, 1639 CS42L42_TS_FALL_DBNCE_TIME_MASK, 1640 (cs42l42->ts_dbnc_fall << 1641 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); 1642 1643 ret = of_property_read_u32(np, "cirrus,btn-det-init-dbnce", &val); 1644 1645 if (!ret) { 1646 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) 1647 cs42l42->btn_det_init_dbnce = val; 1648 else { 1649 dev_err(&i2c_client->dev, 1650 "Wrong cirrus,btn-det-init-dbnce DT value %d\n", 1651 val); 1652 cs42l42->btn_det_init_dbnce = 1653 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1654 } 1655 } else { 1656 cs42l42->btn_det_init_dbnce = 1657 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; 1658 } 1659 1660 ret = of_property_read_u32(np, "cirrus,btn-det-event-dbnce", &val); 1661 1662 if (!ret) { 1663 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) 1664 cs42l42->btn_det_event_dbnce = val; 1665 else { 1666 dev_err(&i2c_client->dev, 1667 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val); 1668 cs42l42->btn_det_event_dbnce = 1669 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1670 } 1671 } else { 1672 cs42l42->btn_det_event_dbnce = 1673 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; 1674 } 1675 1676 ret = of_property_read_u32_array(np, "cirrus,bias-lvls", 1677 (u32 *)thresholds, CS42L42_NUM_BIASES); 1678 1679 if (!ret) { 1680 for (i = 0; i < CS42L42_NUM_BIASES; i++) { 1681 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) 1682 cs42l42->bias_thresholds[i] = thresholds[i]; 1683 else { 1684 dev_err(&i2c_client->dev, 1685 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i, 1686 thresholds[i]); 1687 cs42l42->bias_thresholds[i] = 1688 threshold_defaults[i]; 1689 } 1690 } 1691 } else { 1692 for (i = 0; i < CS42L42_NUM_BIASES; i++) 1693 cs42l42->bias_thresholds[i] = threshold_defaults[i]; 1694 } 1695 1696 ret = of_property_read_u32(np, "cirrus,hs-bias-ramp-rate", &val); 1697 1698 if (!ret) { 1699 switch (val) { 1700 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: 1701 cs42l42->hs_bias_ramp_rate = val; 1702 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; 1703 break; 1704 case CS42L42_HSBIAS_RAMP_FAST: 1705 cs42l42->hs_bias_ramp_rate = val; 1706 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; 1707 break; 1708 case CS42L42_HSBIAS_RAMP_SLOW: 1709 cs42l42->hs_bias_ramp_rate = val; 1710 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1711 break; 1712 case CS42L42_HSBIAS_RAMP_SLOWEST: 1713 cs42l42->hs_bias_ramp_rate = val; 1714 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; 1715 break; 1716 default: 1717 dev_err(&i2c_client->dev, 1718 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n", 1719 val); 1720 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1721 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1722 } 1723 } else { 1724 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; 1725 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; 1726 } 1727 1728 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL, 1729 CS42L42_HSBIAS_RAMP_MASK, 1730 (cs42l42->hs_bias_ramp_rate << 1731 CS42L42_HSBIAS_RAMP_SHIFT)); 1732 1733 return 0; 1734 } 1735 1736 static int cs42l42_i2c_probe(struct i2c_client *i2c_client, 1737 const struct i2c_device_id *id) 1738 { 1739 struct cs42l42_private *cs42l42; 1740 int ret, i; 1741 unsigned int devid = 0; 1742 unsigned int reg; 1743 1744 cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private), 1745 GFP_KERNEL); 1746 if (!cs42l42) 1747 return -ENOMEM; 1748 1749 i2c_set_clientdata(i2c_client, cs42l42); 1750 1751 cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap); 1752 if (IS_ERR(cs42l42->regmap)) { 1753 ret = PTR_ERR(cs42l42->regmap); 1754 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret); 1755 return ret; 1756 } 1757 1758 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) 1759 cs42l42->supplies[i].supply = cs42l42_supply_names[i]; 1760 1761 ret = devm_regulator_bulk_get(&i2c_client->dev, 1762 ARRAY_SIZE(cs42l42->supplies), 1763 cs42l42->supplies); 1764 if (ret != 0) { 1765 dev_err(&i2c_client->dev, 1766 "Failed to request supplies: %d\n", ret); 1767 return ret; 1768 } 1769 1770 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1771 cs42l42->supplies); 1772 if (ret != 0) { 1773 dev_err(&i2c_client->dev, 1774 "Failed to enable supplies: %d\n", ret); 1775 return ret; 1776 } 1777 1778 /* Reset the Device */ 1779 cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev, 1780 "reset", GPIOD_OUT_LOW); 1781 if (IS_ERR(cs42l42->reset_gpio)) { 1782 ret = PTR_ERR(cs42l42->reset_gpio); 1783 goto err_disable; 1784 } 1785 1786 if (cs42l42->reset_gpio) { 1787 dev_dbg(&i2c_client->dev, "Found reset GPIO\n"); 1788 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1789 } 1790 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 1791 1792 /* Request IRQ */ 1793 ret = devm_request_threaded_irq(&i2c_client->dev, 1794 i2c_client->irq, 1795 NULL, cs42l42_irq_thread, 1796 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 1797 "cs42l42", cs42l42); 1798 1799 if (ret != 0) 1800 dev_err(&i2c_client->dev, 1801 "Failed to request IRQ: %d\n", ret); 1802 1803 /* initialize codec */ 1804 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_AB, ®); 1805 devid = (reg & 0xFF) << 12; 1806 1807 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_CD, ®); 1808 devid |= (reg & 0xFF) << 4; 1809 1810 ret = regmap_read(cs42l42->regmap, CS42L42_DEVID_E, ®); 1811 devid |= (reg & 0xF0) >> 4; 1812 1813 if (devid != CS42L42_CHIP_ID) { 1814 ret = -ENODEV; 1815 dev_err(&i2c_client->dev, 1816 "CS42L42 Device ID (%X). Expected %X\n", 1817 devid, CS42L42_CHIP_ID); 1818 goto err_disable; 1819 } 1820 1821 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®); 1822 if (ret < 0) { 1823 dev_err(&i2c_client->dev, "Get Revision ID failed\n"); 1824 goto err_disable; 1825 } 1826 1827 dev_info(&i2c_client->dev, 1828 "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF); 1829 1830 /* Power up the codec */ 1831 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1, 1832 CS42L42_ASP_DAO_PDN_MASK | 1833 CS42L42_ASP_DAI_PDN_MASK | 1834 CS42L42_MIXER_PDN_MASK | 1835 CS42L42_EQ_PDN_MASK | 1836 CS42L42_HP_PDN_MASK | 1837 CS42L42_ADC_PDN_MASK | 1838 CS42L42_PDN_ALL_MASK, 1839 (1 << CS42L42_ASP_DAO_PDN_SHIFT) | 1840 (1 << CS42L42_ASP_DAI_PDN_SHIFT) | 1841 (1 << CS42L42_MIXER_PDN_SHIFT) | 1842 (1 << CS42L42_EQ_PDN_SHIFT) | 1843 (1 << CS42L42_HP_PDN_SHIFT) | 1844 (1 << CS42L42_ADC_PDN_SHIFT) | 1845 (0 << CS42L42_PDN_ALL_SHIFT)); 1846 1847 if (i2c_client->dev.of_node) { 1848 ret = cs42l42_handle_device_data(i2c_client, cs42l42); 1849 if (ret != 0) 1850 goto err_disable; 1851 } 1852 1853 /* Setup headset detection */ 1854 cs42l42_setup_hs_type_detect(cs42l42); 1855 1856 /* Mask/Unmask Interrupts */ 1857 cs42l42_set_interrupt_masks(cs42l42); 1858 1859 /* Register codec for machine driver */ 1860 ret = devm_snd_soc_register_component(&i2c_client->dev, 1861 &soc_component_dev_cs42l42, &cs42l42_dai, 1); 1862 if (ret < 0) 1863 goto err_disable; 1864 return 0; 1865 1866 err_disable: 1867 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1868 cs42l42->supplies); 1869 return ret; 1870 } 1871 1872 static int cs42l42_i2c_remove(struct i2c_client *i2c_client) 1873 { 1874 struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client); 1875 1876 devm_free_irq(&i2c_client->dev, i2c_client->irq, cs42l42); 1877 pm_runtime_suspend(&i2c_client->dev); 1878 pm_runtime_disable(&i2c_client->dev); 1879 1880 return 0; 1881 } 1882 1883 #ifdef CONFIG_PM 1884 static int cs42l42_runtime_suspend(struct device *dev) 1885 { 1886 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 1887 1888 regcache_cache_only(cs42l42->regmap, true); 1889 regcache_mark_dirty(cs42l42->regmap); 1890 1891 /* Hold down reset */ 1892 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0); 1893 1894 /* remove power */ 1895 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), 1896 cs42l42->supplies); 1897 1898 return 0; 1899 } 1900 1901 static int cs42l42_runtime_resume(struct device *dev) 1902 { 1903 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); 1904 int ret; 1905 1906 /* Enable power */ 1907 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), 1908 cs42l42->supplies); 1909 if (ret != 0) { 1910 dev_err(dev, "Failed to enable supplies: %d\n", 1911 ret); 1912 return ret; 1913 } 1914 1915 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1); 1916 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); 1917 1918 regcache_cache_only(cs42l42->regmap, false); 1919 regcache_sync(cs42l42->regmap); 1920 1921 return 0; 1922 } 1923 #endif 1924 1925 static const struct dev_pm_ops cs42l42_runtime_pm = { 1926 SET_RUNTIME_PM_OPS(cs42l42_runtime_suspend, cs42l42_runtime_resume, 1927 NULL) 1928 }; 1929 1930 static const struct of_device_id cs42l42_of_match[] = { 1931 { .compatible = "cirrus,cs42l42", }, 1932 {}, 1933 }; 1934 MODULE_DEVICE_TABLE(of, cs42l42_of_match); 1935 1936 1937 static const struct i2c_device_id cs42l42_id[] = { 1938 {"cs42l42", 0}, 1939 {} 1940 }; 1941 1942 MODULE_DEVICE_TABLE(i2c, cs42l42_id); 1943 1944 static struct i2c_driver cs42l42_i2c_driver = { 1945 .driver = { 1946 .name = "cs42l42", 1947 .pm = &cs42l42_runtime_pm, 1948 .of_match_table = cs42l42_of_match, 1949 }, 1950 .id_table = cs42l42_id, 1951 .probe = cs42l42_i2c_probe, 1952 .remove = cs42l42_i2c_remove, 1953 }; 1954 1955 module_i2c_driver(cs42l42_i2c_driver); 1956 1957 MODULE_DESCRIPTION("ASoC CS42L42 driver"); 1958 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>"); 1959 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 1960 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>"); 1961 MODULE_LICENSE("GPL"); 1962