1 /* 2 * cs35l35.c -- CS35L35 ALSA SoC audio driver 3 * 4 * Copyright 2017 Cirrus Logic, Inc. 5 * 6 * Author: Brian Austin <brian.austin@cirrus.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/version.h> 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/delay.h> 20 #include <linux/i2c.h> 21 #include <linux/slab.h> 22 #include <linux/platform_device.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/gpio/consumer.h> 25 #include <linux/of_device.h> 26 #include <linux/of_gpio.h> 27 #include <linux/regmap.h> 28 #include <sound/core.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/soc.h> 32 #include <sound/soc-dapm.h> 33 #include <linux/gpio.h> 34 #include <sound/initval.h> 35 #include <sound/tlv.h> 36 #include <sound/cs35l35.h> 37 #include <linux/of_irq.h> 38 #include <linux/completion.h> 39 40 #include "cs35l35.h" 41 42 /* 43 * Some fields take zero as a valid value so use a high bit flag that won't 44 * get written to the device to mark those. 45 */ 46 #define CS35L35_VALID_PDATA 0x80000000 47 48 static const struct reg_default cs35l35_reg[] = { 49 {CS35L35_PWRCTL1, 0x01}, 50 {CS35L35_PWRCTL2, 0x11}, 51 {CS35L35_PWRCTL3, 0x00}, 52 {CS35L35_CLK_CTL1, 0x04}, 53 {CS35L35_CLK_CTL2, 0x10}, 54 {CS35L35_CLK_CTL3, 0xCF}, 55 {CS35L35_SP_FMT_CTL1, 0x20}, 56 {CS35L35_SP_FMT_CTL2, 0x00}, 57 {CS35L35_SP_FMT_CTL3, 0x02}, 58 {CS35L35_MAG_COMP_CTL, 0x00}, 59 {CS35L35_AMP_INP_DRV_CTL, 0x01}, 60 {CS35L35_AMP_DIG_VOL_CTL, 0x12}, 61 {CS35L35_AMP_DIG_VOL, 0x00}, 62 {CS35L35_ADV_DIG_VOL, 0x00}, 63 {CS35L35_PROTECT_CTL, 0x06}, 64 {CS35L35_AMP_GAIN_AUD_CTL, 0x13}, 65 {CS35L35_AMP_GAIN_PDM_CTL, 0x00}, 66 {CS35L35_AMP_GAIN_ADV_CTL, 0x00}, 67 {CS35L35_GPI_CTL, 0x00}, 68 {CS35L35_BST_CVTR_V_CTL, 0x00}, 69 {CS35L35_BST_PEAK_I, 0x07}, 70 {CS35L35_BST_RAMP_CTL, 0x85}, 71 {CS35L35_BST_CONV_COEF_1, 0x24}, 72 {CS35L35_BST_CONV_COEF_2, 0x24}, 73 {CS35L35_BST_CONV_SLOPE_COMP, 0x47}, 74 {CS35L35_BST_CONV_SW_FREQ, 0x04}, 75 {CS35L35_CLASS_H_CTL, 0x0B}, 76 {CS35L35_CLASS_H_HEADRM_CTL, 0x0B}, 77 {CS35L35_CLASS_H_RELEASE_RATE, 0x08}, 78 {CS35L35_CLASS_H_FET_DRIVE_CTL, 0x41}, 79 {CS35L35_CLASS_H_VP_CTL, 0xC5}, 80 {CS35L35_VPBR_CTL, 0x0A}, 81 {CS35L35_VPBR_VOL_CTL, 0x09}, 82 {CS35L35_VPBR_TIMING_CTL, 0x6A}, 83 {CS35L35_VPBR_MODE_VOL_CTL, 0x40}, 84 {CS35L35_SPKR_MON_CTL, 0xC0}, 85 {CS35L35_IMON_SCALE_CTL, 0x30}, 86 {CS35L35_AUDIN_RXLOC_CTL, 0x00}, 87 {CS35L35_ADVIN_RXLOC_CTL, 0x80}, 88 {CS35L35_VMON_TXLOC_CTL, 0x00}, 89 {CS35L35_IMON_TXLOC_CTL, 0x80}, 90 {CS35L35_VPMON_TXLOC_CTL, 0x04}, 91 {CS35L35_VBSTMON_TXLOC_CTL, 0x84}, 92 {CS35L35_VPBR_STATUS_TXLOC_CTL, 0x04}, 93 {CS35L35_ZERO_FILL_LOC_CTL, 0x00}, 94 {CS35L35_AUDIN_DEPTH_CTL, 0x0F}, 95 {CS35L35_SPKMON_DEPTH_CTL, 0x0F}, 96 {CS35L35_SUPMON_DEPTH_CTL, 0x0F}, 97 {CS35L35_ZEROFILL_DEPTH_CTL, 0x00}, 98 {CS35L35_MULT_DEV_SYNCH1, 0x02}, 99 {CS35L35_MULT_DEV_SYNCH2, 0x80}, 100 {CS35L35_PROT_RELEASE_CTL, 0x00}, 101 {CS35L35_DIAG_MODE_REG_LOCK, 0x00}, 102 {CS35L35_DIAG_MODE_CTL_1, 0x40}, 103 {CS35L35_DIAG_MODE_CTL_2, 0x00}, 104 {CS35L35_INT_MASK_1, 0xFF}, 105 {CS35L35_INT_MASK_2, 0xFF}, 106 {CS35L35_INT_MASK_3, 0xFF}, 107 {CS35L35_INT_MASK_4, 0xFF}, 108 109 }; 110 111 static bool cs35l35_volatile_register(struct device *dev, unsigned int reg) 112 { 113 switch (reg) { 114 case CS35L35_INT_STATUS_1: 115 case CS35L35_INT_STATUS_2: 116 case CS35L35_INT_STATUS_3: 117 case CS35L35_INT_STATUS_4: 118 case CS35L35_PLL_STATUS: 119 case CS35L35_OTP_TRIM_STATUS: 120 return true; 121 default: 122 return false; 123 } 124 } 125 126 static bool cs35l35_readable_register(struct device *dev, unsigned int reg) 127 { 128 switch (reg) { 129 case CS35L35_DEVID_AB ... CS35L35_PWRCTL3: 130 case CS35L35_CLK_CTL1 ... CS35L35_SP_FMT_CTL3: 131 case CS35L35_MAG_COMP_CTL ... CS35L35_AMP_GAIN_AUD_CTL: 132 case CS35L35_AMP_GAIN_PDM_CTL ... CS35L35_BST_PEAK_I: 133 case CS35L35_BST_RAMP_CTL ... CS35L35_BST_CONV_SW_FREQ: 134 case CS35L35_CLASS_H_CTL ... CS35L35_CLASS_H_VP_CTL: 135 case CS35L35_CLASS_H_STATUS: 136 case CS35L35_VPBR_CTL ... CS35L35_VPBR_MODE_VOL_CTL: 137 case CS35L35_VPBR_ATTEN_STATUS: 138 case CS35L35_SPKR_MON_CTL: 139 case CS35L35_IMON_SCALE_CTL ... CS35L35_ZEROFILL_DEPTH_CTL: 140 case CS35L35_MULT_DEV_SYNCH1 ... CS35L35_PROT_RELEASE_CTL: 141 case CS35L35_DIAG_MODE_REG_LOCK ... CS35L35_DIAG_MODE_CTL_2: 142 case CS35L35_INT_MASK_1 ... CS35L35_PLL_STATUS: 143 case CS35L35_OTP_TRIM_STATUS: 144 return true; 145 default: 146 return false; 147 } 148 } 149 150 static bool cs35l35_precious_register(struct device *dev, unsigned int reg) 151 { 152 switch (reg) { 153 case CS35L35_INT_STATUS_1: 154 case CS35L35_INT_STATUS_2: 155 case CS35L35_INT_STATUS_3: 156 case CS35L35_INT_STATUS_4: 157 case CS35L35_PLL_STATUS: 158 case CS35L35_OTP_TRIM_STATUS: 159 return true; 160 default: 161 return false; 162 } 163 } 164 165 static int cs35l35_sdin_event(struct snd_soc_dapm_widget *w, 166 struct snd_kcontrol *kcontrol, int event) 167 { 168 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 169 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec); 170 int ret = 0; 171 172 switch (event) { 173 case SND_SOC_DAPM_PRE_PMU: 174 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1, 175 CS35L35_MCLK_DIS_MASK, 176 0 << CS35L35_MCLK_DIS_SHIFT); 177 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1, 178 CS35L35_DISCHG_FILT_MASK, 179 0 << CS35L35_DISCHG_FILT_SHIFT); 180 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1, 181 CS35L35_PDN_ALL_MASK, 0); 182 break; 183 case SND_SOC_DAPM_POST_PMD: 184 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1, 185 CS35L35_DISCHG_FILT_MASK, 186 1 << CS35L35_DISCHG_FILT_SHIFT); 187 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1, 188 CS35L35_PDN_ALL_MASK, 1); 189 190 reinit_completion(&cs35l35->pdn_done); 191 192 ret = wait_for_completion_timeout(&cs35l35->pdn_done, 193 msecs_to_jiffies(100)); 194 if (ret == 0) { 195 dev_err(codec->dev, "TIMEOUT PDN_DONE did not complete in 100ms\n"); 196 ret = -ETIMEDOUT; 197 } 198 199 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1, 200 CS35L35_MCLK_DIS_MASK, 201 1 << CS35L35_MCLK_DIS_SHIFT); 202 break; 203 default: 204 dev_err(codec->dev, "Invalid event = 0x%x\n", event); 205 ret = -EINVAL; 206 } 207 return ret; 208 } 209 210 static int cs35l35_main_amp_event(struct snd_soc_dapm_widget *w, 211 struct snd_kcontrol *kcontrol, int event) 212 { 213 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 214 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec); 215 unsigned int reg[4]; 216 int i; 217 218 switch (event) { 219 case SND_SOC_DAPM_PRE_PMU: 220 if (cs35l35->pdata.bst_pdn_fet_on) 221 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2, 222 CS35L35_PDN_BST_MASK, 223 0 << CS35L35_PDN_BST_FETON_SHIFT); 224 else 225 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2, 226 CS35L35_PDN_BST_MASK, 227 0 << CS35L35_PDN_BST_FETOFF_SHIFT); 228 break; 229 case SND_SOC_DAPM_POST_PMU: 230 usleep_range(5000, 5100); 231 /* If in PDM mode we must use VP for Voltage control */ 232 if (cs35l35->pdm_mode) 233 regmap_update_bits(cs35l35->regmap, 234 CS35L35_BST_CVTR_V_CTL, 235 CS35L35_BST_CTL_MASK, 236 0 << CS35L35_BST_CTL_SHIFT); 237 238 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL, 239 CS35L35_AMP_MUTE_MASK, 0); 240 241 for (i = 0; i < 2; i++) 242 regmap_bulk_read(cs35l35->regmap, CS35L35_INT_STATUS_1, 243 ®, ARRAY_SIZE(reg)); 244 245 break; 246 case SND_SOC_DAPM_PRE_PMD: 247 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL, 248 CS35L35_AMP_MUTE_MASK, 249 1 << CS35L35_AMP_MUTE_SHIFT); 250 if (cs35l35->pdata.bst_pdn_fet_on) 251 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2, 252 CS35L35_PDN_BST_MASK, 253 1 << CS35L35_PDN_BST_FETON_SHIFT); 254 else 255 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2, 256 CS35L35_PDN_BST_MASK, 257 1 << CS35L35_PDN_BST_FETOFF_SHIFT); 258 break; 259 case SND_SOC_DAPM_POST_PMD: 260 usleep_range(5000, 5100); 261 /* 262 * If PDM mode we should switch back to pdata value 263 * for Voltage control when we go down 264 */ 265 if (cs35l35->pdm_mode) 266 regmap_update_bits(cs35l35->regmap, 267 CS35L35_BST_CVTR_V_CTL, 268 CS35L35_BST_CTL_MASK, 269 cs35l35->pdata.bst_vctl 270 << CS35L35_BST_CTL_SHIFT); 271 272 break; 273 default: 274 dev_err(codec->dev, "Invalid event = 0x%x\n", event); 275 } 276 return 0; 277 } 278 279 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1); 280 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10200, 50, 0); 281 282 static const struct snd_kcontrol_new cs35l35_aud_controls[] = { 283 SOC_SINGLE_SX_TLV("Digital Audio Volume", CS35L35_AMP_DIG_VOL, 284 0, 0x34, 0xE4, dig_vol_tlv), 285 SOC_SINGLE_TLV("Analog Audio Volume", CS35L35_AMP_GAIN_AUD_CTL, 0, 19, 0, 286 amp_gain_tlv), 287 SOC_SINGLE_TLV("PDM Volume", CS35L35_AMP_GAIN_PDM_CTL, 0, 19, 0, 288 amp_gain_tlv), 289 }; 290 291 static const struct snd_kcontrol_new cs35l35_adv_controls[] = { 292 SOC_SINGLE_SX_TLV("Digital Advisory Volume", CS35L35_ADV_DIG_VOL, 293 0, 0x34, 0xE4, dig_vol_tlv), 294 SOC_SINGLE_TLV("Analog Advisory Volume", CS35L35_AMP_GAIN_ADV_CTL, 0, 19, 0, 295 amp_gain_tlv), 296 }; 297 298 static const struct snd_soc_dapm_widget cs35l35_dapm_widgets[] = { 299 SND_SOC_DAPM_AIF_IN_E("SDIN", NULL, 0, CS35L35_PWRCTL3, 1, 1, 300 cs35l35_sdin_event, SND_SOC_DAPM_PRE_PMU | 301 SND_SOC_DAPM_POST_PMD), 302 SND_SOC_DAPM_AIF_OUT("SDOUT", NULL, 0, CS35L35_PWRCTL3, 2, 1), 303 304 SND_SOC_DAPM_OUTPUT("SPK"), 305 306 SND_SOC_DAPM_INPUT("VP"), 307 SND_SOC_DAPM_INPUT("VBST"), 308 SND_SOC_DAPM_INPUT("ISENSE"), 309 SND_SOC_DAPM_INPUT("VSENSE"), 310 311 SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L35_PWRCTL2, 7, 1), 312 SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L35_PWRCTL2, 6, 1), 313 SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L35_PWRCTL3, 3, 1), 314 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L35_PWRCTL3, 4, 1), 315 SND_SOC_DAPM_ADC("CLASS H", NULL, CS35L35_PWRCTL2, 5, 1), 316 317 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L35_PWRCTL2, 0, 1, NULL, 0, 318 cs35l35_main_amp_event, SND_SOC_DAPM_PRE_PMU | 319 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU | 320 SND_SOC_DAPM_PRE_PMD), 321 }; 322 323 static const struct snd_soc_dapm_route cs35l35_audio_map[] = { 324 {"VPMON ADC", NULL, "VP"}, 325 {"VBSTMON ADC", NULL, "VBST"}, 326 {"IMON ADC", NULL, "ISENSE"}, 327 {"VMON ADC", NULL, "VSENSE"}, 328 {"SDOUT", NULL, "IMON ADC"}, 329 {"SDOUT", NULL, "VMON ADC"}, 330 {"SDOUT", NULL, "VBSTMON ADC"}, 331 {"SDOUT", NULL, "VPMON ADC"}, 332 {"AMP Capture", NULL, "SDOUT"}, 333 334 {"SDIN", NULL, "AMP Playback"}, 335 {"CLASS H", NULL, "SDIN"}, 336 {"Main AMP", NULL, "CLASS H"}, 337 {"SPK", NULL, "Main AMP"}, 338 }; 339 340 static int cs35l35_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 341 { 342 struct snd_soc_codec *codec = codec_dai->codec; 343 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec); 344 345 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 346 case SND_SOC_DAIFMT_CBM_CFM: 347 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1, 348 CS35L35_MS_MASK, 1 << CS35L35_MS_SHIFT); 349 cs35l35->slave_mode = false; 350 break; 351 case SND_SOC_DAIFMT_CBS_CFS: 352 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1, 353 CS35L35_MS_MASK, 0 << CS35L35_MS_SHIFT); 354 cs35l35->slave_mode = true; 355 break; 356 default: 357 return -EINVAL; 358 } 359 360 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 361 case SND_SOC_DAIFMT_I2S: 362 cs35l35->i2s_mode = true; 363 cs35l35->pdm_mode = false; 364 break; 365 case SND_SOC_DAIFMT_PDM: 366 cs35l35->pdm_mode = true; 367 cs35l35->i2s_mode = false; 368 break; 369 default: 370 return -EINVAL; 371 } 372 373 return 0; 374 } 375 376 struct cs35l35_sysclk_config { 377 int sysclk; 378 int srate; 379 u8 clk_cfg; 380 }; 381 382 static struct cs35l35_sysclk_config cs35l35_clk_ctl[] = { 383 384 /* SYSCLK, Sample Rate, Serial Port Cfg */ 385 {5644800, 44100, 0x00}, 386 {5644800, 88200, 0x40}, 387 {6144000, 48000, 0x10}, 388 {6144000, 96000, 0x50}, 389 {11289600, 44100, 0x01}, 390 {11289600, 88200, 0x41}, 391 {11289600, 176400, 0x81}, 392 {12000000, 44100, 0x03}, 393 {12000000, 48000, 0x13}, 394 {12000000, 88200, 0x43}, 395 {12000000, 96000, 0x53}, 396 {12000000, 176400, 0x83}, 397 {12000000, 192000, 0x93}, 398 {12288000, 48000, 0x11}, 399 {12288000, 96000, 0x51}, 400 {12288000, 192000, 0x91}, 401 {13000000, 44100, 0x07}, 402 {13000000, 48000, 0x17}, 403 {13000000, 88200, 0x47}, 404 {13000000, 96000, 0x57}, 405 {13000000, 176400, 0x87}, 406 {13000000, 192000, 0x97}, 407 {22579200, 44100, 0x02}, 408 {22579200, 88200, 0x42}, 409 {22579200, 176400, 0x82}, 410 {24000000, 44100, 0x0B}, 411 {24000000, 48000, 0x1B}, 412 {24000000, 88200, 0x4B}, 413 {24000000, 96000, 0x5B}, 414 {24000000, 176400, 0x8B}, 415 {24000000, 192000, 0x9B}, 416 {24576000, 48000, 0x12}, 417 {24576000, 96000, 0x52}, 418 {24576000, 192000, 0x92}, 419 {26000000, 44100, 0x0F}, 420 {26000000, 48000, 0x1F}, 421 {26000000, 88200, 0x4F}, 422 {26000000, 96000, 0x5F}, 423 {26000000, 176400, 0x8F}, 424 {26000000, 192000, 0x9F}, 425 }; 426 427 static int cs35l35_get_clk_config(int sysclk, int srate) 428 { 429 int i; 430 431 for (i = 0; i < ARRAY_SIZE(cs35l35_clk_ctl); i++) { 432 if (cs35l35_clk_ctl[i].sysclk == sysclk && 433 cs35l35_clk_ctl[i].srate == srate) 434 return cs35l35_clk_ctl[i].clk_cfg; 435 } 436 return -EINVAL; 437 } 438 439 static int cs35l35_hw_params(struct snd_pcm_substream *substream, 440 struct snd_pcm_hw_params *params, 441 struct snd_soc_dai *dai) 442 { 443 struct snd_soc_codec *codec = dai->codec; 444 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec); 445 struct classh_cfg *classh = &cs35l35->pdata.classh_algo; 446 int srate = params_rate(params); 447 int ret = 0; 448 u8 sp_sclks; 449 int audin_format; 450 int errata_chk; 451 452 int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate); 453 454 if (clk_ctl < 0) { 455 dev_err(codec->dev, "Invalid CLK:Rate %d:%d\n", 456 cs35l35->sysclk, srate); 457 return -EINVAL; 458 } 459 460 ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL2, 461 CS35L35_CLK_CTL2_MASK, clk_ctl); 462 if (ret != 0) { 463 dev_err(codec->dev, "Failed to set port config %d\n", ret); 464 return ret; 465 } 466 467 /* 468 * Rev A0 Errata 469 * When configured for the weak-drive detection path (CH_WKFET_DIS = 0) 470 * the Class H algorithm does not enable weak-drive operation for 471 * nonzero values of CH_WKFET_DELAY if SP_RATE = 01 or 10 472 */ 473 errata_chk = clk_ctl & CS35L35_SP_RATE_MASK; 474 475 if (classh->classh_wk_fet_disable == 0x00 && 476 (errata_chk == 0x01 || errata_chk == 0x03)) { 477 ret = regmap_update_bits(cs35l35->regmap, 478 CS35L35_CLASS_H_FET_DRIVE_CTL, 479 CS35L35_CH_WKFET_DEL_MASK, 480 0 << CS35L35_CH_WKFET_DEL_SHIFT); 481 if (ret != 0) { 482 dev_err(codec->dev, "Failed to set fet config %d\n", 483 ret); 484 return ret; 485 } 486 } 487 488 /* 489 * You can pull more Monitor data from the SDOUT pin than going to SDIN 490 * Just make sure your SCLK is fast enough to fill the frame 491 */ 492 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 493 switch (params_width(params)) { 494 case 8: 495 audin_format = CS35L35_SDIN_DEPTH_8; 496 break; 497 case 16: 498 audin_format = CS35L35_SDIN_DEPTH_16; 499 break; 500 case 24: 501 audin_format = CS35L35_SDIN_DEPTH_24; 502 break; 503 default: 504 dev_err(codec->dev, "Unsupported Width %d\n", 505 params_width(params)); 506 return -EINVAL; 507 } 508 regmap_update_bits(cs35l35->regmap, 509 CS35L35_AUDIN_DEPTH_CTL, 510 CS35L35_AUDIN_DEPTH_MASK, 511 audin_format << 512 CS35L35_AUDIN_DEPTH_SHIFT); 513 if (cs35l35->pdata.stereo) { 514 regmap_update_bits(cs35l35->regmap, 515 CS35L35_AUDIN_DEPTH_CTL, 516 CS35L35_ADVIN_DEPTH_MASK, 517 audin_format << 518 CS35L35_ADVIN_DEPTH_SHIFT); 519 } 520 } 521 522 if (cs35l35->i2s_mode) { 523 /* We have to take the SCLK to derive num sclks 524 * to configure the CLOCK_CTL3 register correctly 525 */ 526 if ((cs35l35->sclk / srate) % 4) { 527 dev_err(codec->dev, "Unsupported sclk/fs ratio %d:%d\n", 528 cs35l35->sclk, srate); 529 return -EINVAL; 530 } 531 sp_sclks = ((cs35l35->sclk / srate) / 4) - 1; 532 533 /* Only certain ratios are supported in I2S Slave Mode */ 534 if (cs35l35->slave_mode) { 535 switch (sp_sclks) { 536 case CS35L35_SP_SCLKS_32FS: 537 case CS35L35_SP_SCLKS_48FS: 538 case CS35L35_SP_SCLKS_64FS: 539 break; 540 default: 541 dev_err(codec->dev, "ratio not supported\n"); 542 return -EINVAL; 543 } 544 } else { 545 /* Only certain ratios supported in I2S MASTER Mode */ 546 switch (sp_sclks) { 547 case CS35L35_SP_SCLKS_32FS: 548 case CS35L35_SP_SCLKS_64FS: 549 break; 550 default: 551 dev_err(codec->dev, "ratio not supported\n"); 552 return -EINVAL; 553 } 554 } 555 ret = regmap_update_bits(cs35l35->regmap, 556 CS35L35_CLK_CTL3, 557 CS35L35_SP_SCLKS_MASK, sp_sclks << 558 CS35L35_SP_SCLKS_SHIFT); 559 if (ret != 0) { 560 dev_err(codec->dev, "Failed to set fsclk %d\n", ret); 561 return ret; 562 } 563 } 564 565 return ret; 566 } 567 568 static const unsigned int cs35l35_src_rates[] = { 569 44100, 48000, 88200, 96000, 176400, 192000 570 }; 571 572 static const struct snd_pcm_hw_constraint_list cs35l35_constraints = { 573 .count = ARRAY_SIZE(cs35l35_src_rates), 574 .list = cs35l35_src_rates, 575 }; 576 577 static int cs35l35_pcm_startup(struct snd_pcm_substream *substream, 578 struct snd_soc_dai *dai) 579 { 580 struct snd_soc_codec *codec = dai->codec; 581 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec); 582 583 if (!substream->runtime) 584 return 0; 585 586 snd_pcm_hw_constraint_list(substream->runtime, 0, 587 SNDRV_PCM_HW_PARAM_RATE, &cs35l35_constraints); 588 589 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL, 590 CS35L35_PDM_MODE_MASK, 591 0 << CS35L35_PDM_MODE_SHIFT); 592 593 return 0; 594 } 595 596 static const unsigned int cs35l35_pdm_rates[] = { 597 44100, 48000, 88200, 96000 598 }; 599 600 static const struct snd_pcm_hw_constraint_list cs35l35_pdm_constraints = { 601 .count = ARRAY_SIZE(cs35l35_pdm_rates), 602 .list = cs35l35_pdm_rates, 603 }; 604 605 static int cs35l35_pdm_startup(struct snd_pcm_substream *substream, 606 struct snd_soc_dai *dai) 607 { 608 struct snd_soc_codec *codec = dai->codec; 609 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec); 610 611 if (!substream->runtime) 612 return 0; 613 614 snd_pcm_hw_constraint_list(substream->runtime, 0, 615 SNDRV_PCM_HW_PARAM_RATE, 616 &cs35l35_pdm_constraints); 617 618 regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL, 619 CS35L35_PDM_MODE_MASK, 620 1 << CS35L35_PDM_MODE_SHIFT); 621 622 return 0; 623 } 624 625 static int cs35l35_dai_set_sysclk(struct snd_soc_dai *dai, 626 int clk_id, unsigned int freq, int dir) 627 { 628 struct snd_soc_codec *codec = dai->codec; 629 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec); 630 631 /* Need the SCLK Frequency regardless of sysclk source for I2S */ 632 cs35l35->sclk = freq; 633 634 return 0; 635 } 636 637 static const struct snd_soc_dai_ops cs35l35_ops = { 638 .startup = cs35l35_pcm_startup, 639 .set_fmt = cs35l35_set_dai_fmt, 640 .hw_params = cs35l35_hw_params, 641 .set_sysclk = cs35l35_dai_set_sysclk, 642 }; 643 644 static const struct snd_soc_dai_ops cs35l35_pdm_ops = { 645 .startup = cs35l35_pdm_startup, 646 .set_fmt = cs35l35_set_dai_fmt, 647 .hw_params = cs35l35_hw_params, 648 }; 649 650 static struct snd_soc_dai_driver cs35l35_dai[] = { 651 { 652 .name = "cs35l35-pcm", 653 .id = 0, 654 .playback = { 655 .stream_name = "AMP Playback", 656 .channels_min = 1, 657 .channels_max = 8, 658 .rates = SNDRV_PCM_RATE_KNOT, 659 .formats = CS35L35_FORMATS, 660 }, 661 .capture = { 662 .stream_name = "AMP Capture", 663 .channels_min = 1, 664 .channels_max = 8, 665 .rates = SNDRV_PCM_RATE_KNOT, 666 .formats = CS35L35_FORMATS, 667 }, 668 .ops = &cs35l35_ops, 669 .symmetric_rates = 1, 670 }, 671 { 672 .name = "cs35l35-pdm", 673 .id = 1, 674 .playback = { 675 .stream_name = "PDM Playback", 676 .channels_min = 1, 677 .channels_max = 2, 678 .rates = SNDRV_PCM_RATE_KNOT, 679 .formats = CS35L35_FORMATS, 680 }, 681 .ops = &cs35l35_pdm_ops, 682 }, 683 }; 684 685 static int cs35l35_codec_set_sysclk(struct snd_soc_codec *codec, 686 int clk_id, int source, unsigned int freq, 687 int dir) 688 { 689 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec); 690 int clksrc; 691 int ret = 0; 692 693 switch (clk_id) { 694 case 0: 695 clksrc = CS35L35_CLK_SOURCE_MCLK; 696 break; 697 case 1: 698 clksrc = CS35L35_CLK_SOURCE_SCLK; 699 break; 700 case 2: 701 clksrc = CS35L35_CLK_SOURCE_PDM; 702 break; 703 default: 704 dev_err(codec->dev, "Invalid CLK Source\n"); 705 return -EINVAL; 706 } 707 708 switch (freq) { 709 case 5644800: 710 case 6144000: 711 case 11289600: 712 case 12000000: 713 case 12288000: 714 case 13000000: 715 case 22579200: 716 case 24000000: 717 case 24576000: 718 case 26000000: 719 cs35l35->sysclk = freq; 720 break; 721 default: 722 dev_err(codec->dev, "Invalid CLK Frequency Input : %d\n", freq); 723 return -EINVAL; 724 } 725 726 ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1, 727 CS35L35_CLK_SOURCE_MASK, 728 clksrc << CS35L35_CLK_SOURCE_SHIFT); 729 if (ret != 0) { 730 dev_err(codec->dev, "Failed to set sysclk %d\n", ret); 731 return ret; 732 } 733 734 return ret; 735 } 736 737 static int cs35l35_codec_probe(struct snd_soc_codec *codec) 738 { 739 struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec); 740 struct classh_cfg *classh = &cs35l35->pdata.classh_algo; 741 struct monitor_cfg *monitor_config = &cs35l35->pdata.mon_cfg; 742 int ret; 743 744 /* Set Platform Data */ 745 if (cs35l35->pdata.bst_vctl) 746 regmap_update_bits(cs35l35->regmap, CS35L35_BST_CVTR_V_CTL, 747 CS35L35_BST_CTL_MASK, 748 cs35l35->pdata.bst_vctl); 749 750 if (cs35l35->pdata.bst_ipk) 751 regmap_update_bits(cs35l35->regmap, CS35L35_BST_PEAK_I, 752 CS35L35_BST_IPK_MASK, 753 cs35l35->pdata.bst_ipk << 754 CS35L35_BST_IPK_SHIFT); 755 756 if (cs35l35->pdata.gain_zc) 757 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL, 758 CS35L35_AMP_GAIN_ZC_MASK, 759 cs35l35->pdata.gain_zc << 760 CS35L35_AMP_GAIN_ZC_SHIFT); 761 762 if (cs35l35->pdata.aud_channel) 763 regmap_update_bits(cs35l35->regmap, 764 CS35L35_AUDIN_RXLOC_CTL, 765 CS35L35_AUD_IN_LR_MASK, 766 cs35l35->pdata.aud_channel << 767 CS35L35_AUD_IN_LR_SHIFT); 768 769 if (cs35l35->pdata.stereo) { 770 regmap_update_bits(cs35l35->regmap, 771 CS35L35_ADVIN_RXLOC_CTL, 772 CS35L35_ADV_IN_LR_MASK, 773 cs35l35->pdata.adv_channel << 774 CS35L35_ADV_IN_LR_SHIFT); 775 if (cs35l35->pdata.shared_bst) 776 regmap_update_bits(cs35l35->regmap, CS35L35_CLASS_H_CTL, 777 CS35L35_CH_STEREO_MASK, 778 1 << CS35L35_CH_STEREO_SHIFT); 779 ret = snd_soc_add_codec_controls(codec, cs35l35_adv_controls, 780 ARRAY_SIZE(cs35l35_adv_controls)); 781 if (ret) 782 return ret; 783 } 784 785 if (cs35l35->pdata.sp_drv_str) 786 regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1, 787 CS35L35_SP_DRV_MASK, 788 cs35l35->pdata.sp_drv_str << 789 CS35L35_SP_DRV_SHIFT); 790 if (cs35l35->pdata.sp_drv_unused) 791 regmap_update_bits(cs35l35->regmap, CS35L35_SP_FMT_CTL3, 792 CS35L35_SP_I2S_DRV_MASK, 793 cs35l35->pdata.sp_drv_unused << 794 CS35L35_SP_I2S_DRV_SHIFT); 795 796 if (classh->classh_algo_enable) { 797 if (classh->classh_bst_override) 798 regmap_update_bits(cs35l35->regmap, 799 CS35L35_CLASS_H_CTL, 800 CS35L35_CH_BST_OVR_MASK, 801 classh->classh_bst_override << 802 CS35L35_CH_BST_OVR_SHIFT); 803 if (classh->classh_bst_max_limit) 804 regmap_update_bits(cs35l35->regmap, 805 CS35L35_CLASS_H_CTL, 806 CS35L35_CH_BST_LIM_MASK, 807 classh->classh_bst_max_limit << 808 CS35L35_CH_BST_LIM_SHIFT); 809 if (classh->classh_mem_depth) 810 regmap_update_bits(cs35l35->regmap, 811 CS35L35_CLASS_H_CTL, 812 CS35L35_CH_MEM_DEPTH_MASK, 813 classh->classh_mem_depth << 814 CS35L35_CH_MEM_DEPTH_SHIFT); 815 if (classh->classh_headroom) 816 regmap_update_bits(cs35l35->regmap, 817 CS35L35_CLASS_H_HEADRM_CTL, 818 CS35L35_CH_HDRM_CTL_MASK, 819 classh->classh_headroom << 820 CS35L35_CH_HDRM_CTL_SHIFT); 821 if (classh->classh_release_rate) 822 regmap_update_bits(cs35l35->regmap, 823 CS35L35_CLASS_H_RELEASE_RATE, 824 CS35L35_CH_REL_RATE_MASK, 825 classh->classh_release_rate << 826 CS35L35_CH_REL_RATE_SHIFT); 827 if (classh->classh_wk_fet_disable) 828 regmap_update_bits(cs35l35->regmap, 829 CS35L35_CLASS_H_FET_DRIVE_CTL, 830 CS35L35_CH_WKFET_DIS_MASK, 831 classh->classh_wk_fet_disable << 832 CS35L35_CH_WKFET_DIS_SHIFT); 833 if (classh->classh_wk_fet_delay) 834 regmap_update_bits(cs35l35->regmap, 835 CS35L35_CLASS_H_FET_DRIVE_CTL, 836 CS35L35_CH_WKFET_DEL_MASK, 837 classh->classh_wk_fet_delay << 838 CS35L35_CH_WKFET_DEL_SHIFT); 839 if (classh->classh_wk_fet_thld) 840 regmap_update_bits(cs35l35->regmap, 841 CS35L35_CLASS_H_FET_DRIVE_CTL, 842 CS35L35_CH_WKFET_THLD_MASK, 843 classh->classh_wk_fet_thld << 844 CS35L35_CH_WKFET_THLD_SHIFT); 845 if (classh->classh_vpch_auto) 846 regmap_update_bits(cs35l35->regmap, 847 CS35L35_CLASS_H_VP_CTL, 848 CS35L35_CH_VP_AUTO_MASK, 849 classh->classh_vpch_auto << 850 CS35L35_CH_VP_AUTO_SHIFT); 851 if (classh->classh_vpch_rate) 852 regmap_update_bits(cs35l35->regmap, 853 CS35L35_CLASS_H_VP_CTL, 854 CS35L35_CH_VP_RATE_MASK, 855 classh->classh_vpch_rate << 856 CS35L35_CH_VP_RATE_SHIFT); 857 if (classh->classh_vpch_man) 858 regmap_update_bits(cs35l35->regmap, 859 CS35L35_CLASS_H_VP_CTL, 860 CS35L35_CH_VP_MAN_MASK, 861 classh->classh_vpch_man << 862 CS35L35_CH_VP_MAN_SHIFT); 863 } 864 865 if (monitor_config->is_present) { 866 if (monitor_config->vmon_specs) { 867 regmap_update_bits(cs35l35->regmap, 868 CS35L35_SPKMON_DEPTH_CTL, 869 CS35L35_VMON_DEPTH_MASK, 870 monitor_config->vmon_dpth << 871 CS35L35_VMON_DEPTH_SHIFT); 872 regmap_update_bits(cs35l35->regmap, 873 CS35L35_VMON_TXLOC_CTL, 874 CS35L35_MON_TXLOC_MASK, 875 monitor_config->vmon_loc << 876 CS35L35_MON_TXLOC_SHIFT); 877 regmap_update_bits(cs35l35->regmap, 878 CS35L35_VMON_TXLOC_CTL, 879 CS35L35_MON_FRM_MASK, 880 monitor_config->vmon_frm << 881 CS35L35_MON_FRM_SHIFT); 882 } 883 if (monitor_config->imon_specs) { 884 regmap_update_bits(cs35l35->regmap, 885 CS35L35_SPKMON_DEPTH_CTL, 886 CS35L35_IMON_DEPTH_MASK, 887 monitor_config->imon_dpth << 888 CS35L35_IMON_DEPTH_SHIFT); 889 regmap_update_bits(cs35l35->regmap, 890 CS35L35_IMON_TXLOC_CTL, 891 CS35L35_MON_TXLOC_MASK, 892 monitor_config->imon_loc << 893 CS35L35_MON_TXLOC_SHIFT); 894 regmap_update_bits(cs35l35->regmap, 895 CS35L35_IMON_TXLOC_CTL, 896 CS35L35_MON_FRM_MASK, 897 monitor_config->imon_frm << 898 CS35L35_MON_FRM_SHIFT); 899 } 900 if (monitor_config->vpmon_specs) { 901 regmap_update_bits(cs35l35->regmap, 902 CS35L35_SUPMON_DEPTH_CTL, 903 CS35L35_VPMON_DEPTH_MASK, 904 monitor_config->vpmon_dpth << 905 CS35L35_VPMON_DEPTH_SHIFT); 906 regmap_update_bits(cs35l35->regmap, 907 CS35L35_VPMON_TXLOC_CTL, 908 CS35L35_MON_TXLOC_MASK, 909 monitor_config->vpmon_loc << 910 CS35L35_MON_TXLOC_SHIFT); 911 regmap_update_bits(cs35l35->regmap, 912 CS35L35_VPMON_TXLOC_CTL, 913 CS35L35_MON_FRM_MASK, 914 monitor_config->vpmon_frm << 915 CS35L35_MON_FRM_SHIFT); 916 } 917 if (monitor_config->vbstmon_specs) { 918 regmap_update_bits(cs35l35->regmap, 919 CS35L35_SUPMON_DEPTH_CTL, 920 CS35L35_VBSTMON_DEPTH_MASK, 921 monitor_config->vpmon_dpth << 922 CS35L35_VBSTMON_DEPTH_SHIFT); 923 regmap_update_bits(cs35l35->regmap, 924 CS35L35_VBSTMON_TXLOC_CTL, 925 CS35L35_MON_TXLOC_MASK, 926 monitor_config->vbstmon_loc << 927 CS35L35_MON_TXLOC_SHIFT); 928 regmap_update_bits(cs35l35->regmap, 929 CS35L35_VBSTMON_TXLOC_CTL, 930 CS35L35_MON_FRM_MASK, 931 monitor_config->vbstmon_frm << 932 CS35L35_MON_FRM_SHIFT); 933 } 934 if (monitor_config->vpbrstat_specs) { 935 regmap_update_bits(cs35l35->regmap, 936 CS35L35_SUPMON_DEPTH_CTL, 937 CS35L35_VPBRSTAT_DEPTH_MASK, 938 monitor_config->vpbrstat_dpth << 939 CS35L35_VPBRSTAT_DEPTH_SHIFT); 940 regmap_update_bits(cs35l35->regmap, 941 CS35L35_VPBR_STATUS_TXLOC_CTL, 942 CS35L35_MON_TXLOC_MASK, 943 monitor_config->vpbrstat_loc << 944 CS35L35_MON_TXLOC_SHIFT); 945 regmap_update_bits(cs35l35->regmap, 946 CS35L35_VPBR_STATUS_TXLOC_CTL, 947 CS35L35_MON_FRM_MASK, 948 monitor_config->vpbrstat_frm << 949 CS35L35_MON_FRM_SHIFT); 950 } 951 if (monitor_config->zerofill_specs) { 952 regmap_update_bits(cs35l35->regmap, 953 CS35L35_SUPMON_DEPTH_CTL, 954 CS35L35_ZEROFILL_DEPTH_MASK, 955 monitor_config->zerofill_dpth << 956 CS35L35_ZEROFILL_DEPTH_SHIFT); 957 regmap_update_bits(cs35l35->regmap, 958 CS35L35_ZERO_FILL_LOC_CTL, 959 CS35L35_MON_TXLOC_MASK, 960 monitor_config->zerofill_loc << 961 CS35L35_MON_TXLOC_SHIFT); 962 regmap_update_bits(cs35l35->regmap, 963 CS35L35_ZERO_FILL_LOC_CTL, 964 CS35L35_MON_FRM_MASK, 965 monitor_config->zerofill_frm << 966 CS35L35_MON_FRM_SHIFT); 967 } 968 } 969 970 return 0; 971 } 972 973 static struct snd_soc_codec_driver soc_codec_dev_cs35l35 = { 974 .probe = cs35l35_codec_probe, 975 .set_sysclk = cs35l35_codec_set_sysclk, 976 .component_driver = { 977 .dapm_widgets = cs35l35_dapm_widgets, 978 .num_dapm_widgets = ARRAY_SIZE(cs35l35_dapm_widgets), 979 980 .dapm_routes = cs35l35_audio_map, 981 .num_dapm_routes = ARRAY_SIZE(cs35l35_audio_map), 982 983 .controls = cs35l35_aud_controls, 984 .num_controls = ARRAY_SIZE(cs35l35_aud_controls), 985 }, 986 987 }; 988 989 static struct regmap_config cs35l35_regmap = { 990 .reg_bits = 8, 991 .val_bits = 8, 992 993 .max_register = CS35L35_MAX_REGISTER, 994 .reg_defaults = cs35l35_reg, 995 .num_reg_defaults = ARRAY_SIZE(cs35l35_reg), 996 .volatile_reg = cs35l35_volatile_register, 997 .readable_reg = cs35l35_readable_register, 998 .precious_reg = cs35l35_precious_register, 999 .cache_type = REGCACHE_RBTREE, 1000 }; 1001 1002 static irqreturn_t cs35l35_irq(int irq, void *data) 1003 { 1004 struct cs35l35_private *cs35l35 = data; 1005 unsigned int sticky1, sticky2, sticky3, sticky4; 1006 unsigned int mask1, mask2, mask3, mask4, current1; 1007 1008 /* ack the irq by reading all status registers */ 1009 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_4, &sticky4); 1010 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_3, &sticky3); 1011 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_2, &sticky2); 1012 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, &sticky1); 1013 1014 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_4, &mask4); 1015 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_3, &mask3); 1016 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_2, &mask2); 1017 regmap_read(cs35l35->regmap, CS35L35_INT_MASK_1, &mask1); 1018 1019 /* Check to see if unmasked bits are active */ 1020 if (!(sticky1 & ~mask1) && !(sticky2 & ~mask2) && !(sticky3 & ~mask3) 1021 && !(sticky4 & ~mask4)) 1022 return IRQ_NONE; 1023 1024 if (sticky2 & CS35L35_PDN_DONE) 1025 complete(&cs35l35->pdn_done); 1026 1027 /* read the current values */ 1028 regmap_read(cs35l35->regmap, CS35L35_INT_STATUS_1, ¤t1); 1029 1030 /* handle the interrupts */ 1031 if (sticky1 & CS35L35_CAL_ERR) { 1032 dev_crit(cs35l35->dev, "Calibration Error\n"); 1033 1034 /* error is no longer asserted; safe to reset */ 1035 if (!(current1 & CS35L35_CAL_ERR)) { 1036 pr_debug("%s : Cal error release\n", __func__); 1037 regmap_update_bits(cs35l35->regmap, 1038 CS35L35_PROT_RELEASE_CTL, 1039 CS35L35_CAL_ERR_RLS, 0); 1040 regmap_update_bits(cs35l35->regmap, 1041 CS35L35_PROT_RELEASE_CTL, 1042 CS35L35_CAL_ERR_RLS, 1043 CS35L35_CAL_ERR_RLS); 1044 regmap_update_bits(cs35l35->regmap, 1045 CS35L35_PROT_RELEASE_CTL, 1046 CS35L35_CAL_ERR_RLS, 0); 1047 } 1048 } 1049 1050 if (sticky1 & CS35L35_AMP_SHORT) { 1051 dev_crit(cs35l35->dev, "AMP Short Error\n"); 1052 /* error is no longer asserted; safe to reset */ 1053 if (!(current1 & CS35L35_AMP_SHORT)) { 1054 dev_dbg(cs35l35->dev, "Amp short error release\n"); 1055 regmap_update_bits(cs35l35->regmap, 1056 CS35L35_PROT_RELEASE_CTL, 1057 CS35L35_SHORT_RLS, 0); 1058 regmap_update_bits(cs35l35->regmap, 1059 CS35L35_PROT_RELEASE_CTL, 1060 CS35L35_SHORT_RLS, 1061 CS35L35_SHORT_RLS); 1062 regmap_update_bits(cs35l35->regmap, 1063 CS35L35_PROT_RELEASE_CTL, 1064 CS35L35_SHORT_RLS, 0); 1065 } 1066 } 1067 1068 if (sticky1 & CS35L35_OTW) { 1069 dev_warn(cs35l35->dev, "Over temperature warning\n"); 1070 1071 /* error is no longer asserted; safe to reset */ 1072 if (!(current1 & CS35L35_OTW)) { 1073 dev_dbg(cs35l35->dev, "Over temperature warn release\n"); 1074 regmap_update_bits(cs35l35->regmap, 1075 CS35L35_PROT_RELEASE_CTL, 1076 CS35L35_OTW_RLS, 0); 1077 regmap_update_bits(cs35l35->regmap, 1078 CS35L35_PROT_RELEASE_CTL, 1079 CS35L35_OTW_RLS, 1080 CS35L35_OTW_RLS); 1081 regmap_update_bits(cs35l35->regmap, 1082 CS35L35_PROT_RELEASE_CTL, 1083 CS35L35_OTW_RLS, 0); 1084 } 1085 } 1086 1087 if (sticky1 & CS35L35_OTE) { 1088 dev_crit(cs35l35->dev, "Over temperature error\n"); 1089 /* error is no longer asserted; safe to reset */ 1090 if (!(current1 & CS35L35_OTE)) { 1091 dev_dbg(cs35l35->dev, "Over temperature error release\n"); 1092 regmap_update_bits(cs35l35->regmap, 1093 CS35L35_PROT_RELEASE_CTL, 1094 CS35L35_OTE_RLS, 0); 1095 regmap_update_bits(cs35l35->regmap, 1096 CS35L35_PROT_RELEASE_CTL, 1097 CS35L35_OTE_RLS, 1098 CS35L35_OTE_RLS); 1099 regmap_update_bits(cs35l35->regmap, 1100 CS35L35_PROT_RELEASE_CTL, 1101 CS35L35_OTE_RLS, 0); 1102 } 1103 } 1104 1105 if (sticky3 & CS35L35_BST_HIGH) { 1106 dev_crit(cs35l35->dev, "VBST error: powering off!\n"); 1107 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2, 1108 CS35L35_PDN_AMP, CS35L35_PDN_AMP); 1109 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1, 1110 CS35L35_PDN_ALL, CS35L35_PDN_ALL); 1111 } 1112 1113 if (sticky3 & CS35L35_LBST_SHORT) { 1114 dev_crit(cs35l35->dev, "LBST error: powering off!\n"); 1115 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2, 1116 CS35L35_PDN_AMP, CS35L35_PDN_AMP); 1117 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1, 1118 CS35L35_PDN_ALL, CS35L35_PDN_ALL); 1119 } 1120 1121 if (sticky2 & CS35L35_VPBR_ERR) 1122 dev_dbg(cs35l35->dev, "Error: Reactive Brownout\n"); 1123 1124 if (sticky4 & CS35L35_VMON_OVFL) 1125 dev_dbg(cs35l35->dev, "Error: VMON overflow\n"); 1126 1127 if (sticky4 & CS35L35_IMON_OVFL) 1128 dev_dbg(cs35l35->dev, "Error: IMON overflow\n"); 1129 1130 return IRQ_HANDLED; 1131 } 1132 1133 1134 static int cs35l35_handle_of_data(struct i2c_client *i2c_client, 1135 struct cs35l35_platform_data *pdata) 1136 { 1137 struct device_node *np = i2c_client->dev.of_node; 1138 struct device_node *classh, *signal_format; 1139 struct classh_cfg *classh_config = &pdata->classh_algo; 1140 struct monitor_cfg *monitor_config = &pdata->mon_cfg; 1141 unsigned int val32 = 0; 1142 u8 monitor_array[3]; 1143 int ret = 0; 1144 1145 if (!np) 1146 return 0; 1147 1148 pdata->bst_pdn_fet_on = of_property_read_bool(np, 1149 "cirrus,boost-pdn-fet-on"); 1150 1151 ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val32); 1152 if (ret >= 0) { 1153 if (val32 < 2600 || val32 > 9000) { 1154 dev_err(&i2c_client->dev, 1155 "Invalid Boost Voltage %d mV\n", val32); 1156 return -EINVAL; 1157 } 1158 pdata->bst_vctl = ((val32 - 2600) / 100) + 1; 1159 } 1160 1161 ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val32); 1162 if (ret >= 0) { 1163 if (val32 < 1680 || val32 > 4480) { 1164 dev_err(&i2c_client->dev, 1165 "Invalid Boost Peak Current %u mA\n", val32); 1166 return -EINVAL; 1167 } 1168 1169 pdata->bst_ipk = (val32 - 1680) / 110; 1170 } 1171 1172 if (of_property_read_u32(np, "cirrus,sp-drv-strength", &val32) >= 0) 1173 pdata->sp_drv_str = val32; 1174 if (of_property_read_u32(np, "cirrus,sp-drv-unused", &val32) >= 0) 1175 pdata->sp_drv_unused = val32 | CS35L35_VALID_PDATA; 1176 1177 pdata->stereo = of_property_read_bool(np, "cirrus,stereo-config"); 1178 1179 if (pdata->stereo) { 1180 ret = of_property_read_u32(np, "cirrus,audio-channel", &val32); 1181 if (ret >= 0) 1182 pdata->aud_channel = val32; 1183 1184 ret = of_property_read_u32(np, "cirrus,advisory-channel", 1185 &val32); 1186 if (ret >= 0) 1187 pdata->adv_channel = val32; 1188 1189 pdata->shared_bst = of_property_read_bool(np, 1190 "cirrus,shared-boost"); 1191 } 1192 1193 pdata->gain_zc = of_property_read_bool(np, "cirrus,amp-gain-zc"); 1194 1195 classh = of_get_child_by_name(np, "cirrus,classh-internal-algo"); 1196 classh_config->classh_algo_enable = classh ? true : false; 1197 1198 if (classh_config->classh_algo_enable) { 1199 classh_config->classh_bst_override = 1200 of_property_read_bool(np, "cirrus,classh-bst-overide"); 1201 1202 ret = of_property_read_u32(classh, 1203 "cirrus,classh-bst-max-limit", 1204 &val32); 1205 if (ret >= 0) { 1206 val32 |= CS35L35_VALID_PDATA; 1207 classh_config->classh_bst_max_limit = val32; 1208 } 1209 1210 ret = of_property_read_u32(classh, 1211 "cirrus,classh-bst-max-limit", 1212 &val32); 1213 if (ret >= 0) { 1214 val32 |= CS35L35_VALID_PDATA; 1215 classh_config->classh_bst_max_limit = val32; 1216 } 1217 1218 ret = of_property_read_u32(classh, "cirrus,classh-mem-depth", 1219 &val32); 1220 if (ret >= 0) { 1221 val32 |= CS35L35_VALID_PDATA; 1222 classh_config->classh_mem_depth = val32; 1223 } 1224 1225 ret = of_property_read_u32(classh, "cirrus,classh-release-rate", 1226 &val32); 1227 if (ret >= 0) 1228 classh_config->classh_release_rate = val32; 1229 1230 ret = of_property_read_u32(classh, "cirrus,classh-headroom", 1231 &val32); 1232 if (ret >= 0) { 1233 val32 |= CS35L35_VALID_PDATA; 1234 classh_config->classh_headroom = val32; 1235 } 1236 1237 ret = of_property_read_u32(classh, 1238 "cirrus,classh-wk-fet-disable", 1239 &val32); 1240 if (ret >= 0) 1241 classh_config->classh_wk_fet_disable = val32; 1242 1243 ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-delay", 1244 &val32); 1245 if (ret >= 0) { 1246 val32 |= CS35L35_VALID_PDATA; 1247 classh_config->classh_wk_fet_delay = val32; 1248 } 1249 1250 ret = of_property_read_u32(classh, "cirrus,classh-wk-fet-thld", 1251 &val32); 1252 if (ret >= 0) 1253 classh_config->classh_wk_fet_thld = val32; 1254 1255 ret = of_property_read_u32(classh, "cirrus,classh-vpch-auto", 1256 &val32); 1257 if (ret >= 0) { 1258 val32 |= CS35L35_VALID_PDATA; 1259 classh_config->classh_vpch_auto = val32; 1260 } 1261 1262 ret = of_property_read_u32(classh, "cirrus,classh-vpch-rate", 1263 &val32); 1264 if (ret >= 0) { 1265 val32 |= CS35L35_VALID_PDATA; 1266 classh_config->classh_vpch_rate = val32; 1267 } 1268 1269 ret = of_property_read_u32(classh, "cirrus,classh-vpch-man", 1270 &val32); 1271 if (ret >= 0) 1272 classh_config->classh_vpch_man = val32; 1273 } 1274 of_node_put(classh); 1275 1276 /* frame depth location */ 1277 signal_format = of_get_child_by_name(np, "cirrus,monitor-signal-format"); 1278 monitor_config->is_present = signal_format ? true : false; 1279 if (monitor_config->is_present) { 1280 ret = of_property_read_u8_array(signal_format, "cirrus,imon", 1281 monitor_array, ARRAY_SIZE(monitor_array)); 1282 if (!ret) { 1283 monitor_config->imon_specs = true; 1284 monitor_config->imon_dpth = monitor_array[0]; 1285 monitor_config->imon_loc = monitor_array[1]; 1286 monitor_config->imon_frm = monitor_array[2]; 1287 } 1288 ret = of_property_read_u8_array(signal_format, "cirrus,vmon", 1289 monitor_array, ARRAY_SIZE(monitor_array)); 1290 if (!ret) { 1291 monitor_config->vmon_specs = true; 1292 monitor_config->vmon_dpth = monitor_array[0]; 1293 monitor_config->vmon_loc = monitor_array[1]; 1294 monitor_config->vmon_frm = monitor_array[2]; 1295 } 1296 ret = of_property_read_u8_array(signal_format, "cirrus,vpmon", 1297 monitor_array, ARRAY_SIZE(monitor_array)); 1298 if (!ret) { 1299 monitor_config->vpmon_specs = true; 1300 monitor_config->vpmon_dpth = monitor_array[0]; 1301 monitor_config->vpmon_loc = monitor_array[1]; 1302 monitor_config->vpmon_frm = monitor_array[2]; 1303 } 1304 ret = of_property_read_u8_array(signal_format, "cirrus,vbstmon", 1305 monitor_array, ARRAY_SIZE(monitor_array)); 1306 if (!ret) { 1307 monitor_config->vbstmon_specs = true; 1308 monitor_config->vbstmon_dpth = monitor_array[0]; 1309 monitor_config->vbstmon_loc = monitor_array[1]; 1310 monitor_config->vbstmon_frm = monitor_array[2]; 1311 } 1312 ret = of_property_read_u8_array(signal_format, "cirrus,vpbrstat", 1313 monitor_array, ARRAY_SIZE(monitor_array)); 1314 if (!ret) { 1315 monitor_config->vpbrstat_specs = true; 1316 monitor_config->vpbrstat_dpth = monitor_array[0]; 1317 monitor_config->vpbrstat_loc = monitor_array[1]; 1318 monitor_config->vpbrstat_frm = monitor_array[2]; 1319 } 1320 ret = of_property_read_u8_array(signal_format, "cirrus,zerofill", 1321 monitor_array, ARRAY_SIZE(monitor_array)); 1322 if (!ret) { 1323 monitor_config->zerofill_specs = true; 1324 monitor_config->zerofill_dpth = monitor_array[0]; 1325 monitor_config->zerofill_loc = monitor_array[1]; 1326 monitor_config->zerofill_frm = monitor_array[2]; 1327 } 1328 } 1329 of_node_put(signal_format); 1330 1331 return 0; 1332 } 1333 1334 /* Errata Rev A0 */ 1335 static const struct reg_sequence cs35l35_errata_patch[] = { 1336 1337 { 0x7F, 0x99 }, 1338 { 0x00, 0x99 }, 1339 { 0x52, 0x22 }, 1340 { 0x04, 0x14 }, 1341 { 0x6D, 0x44 }, 1342 { 0x24, 0x10 }, 1343 { 0x58, 0xC4 }, 1344 { 0x00, 0x98 }, 1345 { 0x18, 0x08 }, 1346 { 0x00, 0x00 }, 1347 { 0x7F, 0x00 }, 1348 }; 1349 1350 static int cs35l35_i2c_probe(struct i2c_client *i2c_client, 1351 const struct i2c_device_id *id) 1352 { 1353 struct cs35l35_private *cs35l35; 1354 struct device *dev = &i2c_client->dev; 1355 struct cs35l35_platform_data *pdata = dev_get_platdata(dev); 1356 int i; 1357 int ret; 1358 unsigned int devid = 0; 1359 unsigned int reg; 1360 1361 cs35l35 = devm_kzalloc(dev, sizeof(struct cs35l35_private), GFP_KERNEL); 1362 if (!cs35l35) 1363 return -ENOMEM; 1364 1365 cs35l35->dev = dev; 1366 1367 i2c_set_clientdata(i2c_client, cs35l35); 1368 cs35l35->regmap = devm_regmap_init_i2c(i2c_client, &cs35l35_regmap); 1369 if (IS_ERR(cs35l35->regmap)) { 1370 ret = PTR_ERR(cs35l35->regmap); 1371 dev_err(dev, "regmap_init() failed: %d\n", ret); 1372 goto err; 1373 } 1374 1375 for (i = 0; i < ARRAY_SIZE(cs35l35_supplies); i++) 1376 cs35l35->supplies[i].supply = cs35l35_supplies[i]; 1377 1378 cs35l35->num_supplies = ARRAY_SIZE(cs35l35_supplies); 1379 1380 ret = devm_regulator_bulk_get(dev, cs35l35->num_supplies, 1381 cs35l35->supplies); 1382 if (ret != 0) { 1383 dev_err(dev, "Failed to request core supplies: %d\n", ret); 1384 return ret; 1385 } 1386 1387 if (pdata) { 1388 cs35l35->pdata = *pdata; 1389 } else { 1390 pdata = devm_kzalloc(dev, sizeof(struct cs35l35_platform_data), 1391 GFP_KERNEL); 1392 if (!pdata) 1393 return -ENOMEM; 1394 if (i2c_client->dev.of_node) { 1395 ret = cs35l35_handle_of_data(i2c_client, pdata); 1396 if (ret != 0) 1397 return ret; 1398 1399 } 1400 cs35l35->pdata = *pdata; 1401 } 1402 1403 ret = regulator_bulk_enable(cs35l35->num_supplies, 1404 cs35l35->supplies); 1405 if (ret != 0) { 1406 dev_err(dev, "Failed to enable core supplies: %d\n", ret); 1407 return ret; 1408 } 1409 1410 /* returning NULL can be valid if in stereo mode */ 1411 cs35l35->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1412 GPIOD_OUT_LOW); 1413 if (IS_ERR(cs35l35->reset_gpio)) { 1414 ret = PTR_ERR(cs35l35->reset_gpio); 1415 cs35l35->reset_gpio = NULL; 1416 if (ret == -EBUSY) { 1417 dev_info(dev, 1418 "Reset line busy, assuming shared reset\n"); 1419 } else { 1420 dev_err(dev, "Failed to get reset GPIO: %d\n", ret); 1421 goto err; 1422 } 1423 } 1424 1425 gpiod_set_value_cansleep(cs35l35->reset_gpio, 1); 1426 1427 init_completion(&cs35l35->pdn_done); 1428 1429 ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l35_irq, 1430 IRQF_ONESHOT | IRQF_TRIGGER_LOW | 1431 IRQF_SHARED, "cs35l35", cs35l35); 1432 if (ret != 0) { 1433 dev_err(dev, "Failed to request IRQ: %d\n", ret); 1434 goto err; 1435 } 1436 /* initialize codec */ 1437 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_AB, ®); 1438 1439 devid = (reg & 0xFF) << 12; 1440 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_CD, ®); 1441 devid |= (reg & 0xFF) << 4; 1442 ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_E, ®); 1443 devid |= (reg & 0xF0) >> 4; 1444 1445 if (devid != CS35L35_CHIP_ID) { 1446 dev_err(dev, "CS35L35 Device ID (%X). Expected ID %X\n", 1447 devid, CS35L35_CHIP_ID); 1448 ret = -ENODEV; 1449 goto err; 1450 } 1451 1452 ret = regmap_read(cs35l35->regmap, CS35L35_REV_ID, ®); 1453 if (ret < 0) { 1454 dev_err(dev, "Get Revision ID failed: %d\n", ret); 1455 goto err; 1456 } 1457 1458 ret = regmap_register_patch(cs35l35->regmap, cs35l35_errata_patch, 1459 ARRAY_SIZE(cs35l35_errata_patch)); 1460 if (ret < 0) { 1461 dev_err(dev, "Failed to apply errata patch: %d\n", ret); 1462 goto err; 1463 } 1464 1465 dev_info(dev, "Cirrus Logic CS35L35 (%x), Revision: %02X\n", 1466 devid, reg & 0xFF); 1467 1468 /* Set the INT Masks for critical errors */ 1469 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_1, 1470 CS35L35_INT1_CRIT_MASK); 1471 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_2, 1472 CS35L35_INT2_CRIT_MASK); 1473 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_3, 1474 CS35L35_INT3_CRIT_MASK); 1475 regmap_write(cs35l35->regmap, CS35L35_INT_MASK_4, 1476 CS35L35_INT4_CRIT_MASK); 1477 1478 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2, 1479 CS35L35_PWR2_PDN_MASK, 1480 CS35L35_PWR2_PDN_MASK); 1481 1482 if (cs35l35->pdata.bst_pdn_fet_on) 1483 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2, 1484 CS35L35_PDN_BST_MASK, 1485 1 << CS35L35_PDN_BST_FETON_SHIFT); 1486 else 1487 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2, 1488 CS35L35_PDN_BST_MASK, 1489 1 << CS35L35_PDN_BST_FETOFF_SHIFT); 1490 1491 regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL3, 1492 CS35L35_PWR3_PDN_MASK, 1493 CS35L35_PWR3_PDN_MASK); 1494 1495 regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL, 1496 CS35L35_AMP_MUTE_MASK, 1 << CS35L35_AMP_MUTE_SHIFT); 1497 1498 ret = snd_soc_register_codec(dev, &soc_codec_dev_cs35l35, cs35l35_dai, 1499 ARRAY_SIZE(cs35l35_dai)); 1500 if (ret < 0) { 1501 dev_err(dev, "Failed to register codec: %d\n", ret); 1502 goto err; 1503 } 1504 1505 return 0; 1506 1507 err: 1508 regulator_bulk_disable(cs35l35->num_supplies, 1509 cs35l35->supplies); 1510 gpiod_set_value_cansleep(cs35l35->reset_gpio, 0); 1511 1512 return ret; 1513 } 1514 1515 static int cs35l35_i2c_remove(struct i2c_client *client) 1516 { 1517 snd_soc_unregister_codec(&client->dev); 1518 return 0; 1519 } 1520 1521 static const struct of_device_id cs35l35_of_match[] = { 1522 {.compatible = "cirrus,cs35l35"}, 1523 {}, 1524 }; 1525 MODULE_DEVICE_TABLE(of, cs35l35_of_match); 1526 1527 static const struct i2c_device_id cs35l35_id[] = { 1528 {"cs35l35", 0}, 1529 {} 1530 }; 1531 1532 MODULE_DEVICE_TABLE(i2c, cs35l35_id); 1533 1534 static struct i2c_driver cs35l35_i2c_driver = { 1535 .driver = { 1536 .name = "cs35l35", 1537 .of_match_table = cs35l35_of_match, 1538 }, 1539 .id_table = cs35l35_id, 1540 .probe = cs35l35_i2c_probe, 1541 .remove = cs35l35_i2c_remove, 1542 }; 1543 1544 module_i2c_driver(cs35l35_i2c_driver); 1545 1546 MODULE_DESCRIPTION("ASoC CS35L35 driver"); 1547 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>"); 1548 MODULE_LICENSE("GPL"); 1549