1*2aec85b2SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2*2aec85b2SThomas Gleixner /* Copyright (C) 2014-2015 Broadcom Corporation */ 3a6ee05d9SSimran Rai #ifndef __CYGNUS_SSP_H__ 4a6ee05d9SSimran Rai #define __CYGNUS_SSP_H__ 5a6ee05d9SSimran Rai 6a6ee05d9SSimran Rai #define CYGNUS_TDM_DAI_MAX_SLOTS 16 7a6ee05d9SSimran Rai 8a6ee05d9SSimran Rai #define CYGNUS_MAX_PLAYBACK_PORTS 4 9a6ee05d9SSimran Rai #define CYGNUS_MAX_CAPTURE_PORTS 3 10a6ee05d9SSimran Rai #define CYGNUS_MAX_I2S_PORTS 3 11a6ee05d9SSimran Rai #define CYGNUS_MAX_PORTS CYGNUS_MAX_PLAYBACK_PORTS 12a6ee05d9SSimran Rai #define CYGNUS_AUIDO_MAX_NUM_CLKS 3 13a6ee05d9SSimran Rai 14a6ee05d9SSimran Rai #define CYGNUS_SSP_FRAMEBITS_DIV 1 15a6ee05d9SSimran Rai 16a6ee05d9SSimran Rai #define CYGNUS_SSPMODE_I2S 0 17a6ee05d9SSimran Rai #define CYGNUS_SSPMODE_TDM 1 18a6ee05d9SSimran Rai #define CYGNUS_SSPMODE_UNKNOWN -1 19a6ee05d9SSimran Rai 20a6ee05d9SSimran Rai #define CYGNUS_SSP_CLKSRC_PLL 0 21a6ee05d9SSimran Rai 22a6ee05d9SSimran Rai /* Max string length of our dt property names */ 23a6ee05d9SSimran Rai #define PROP_LEN_MAX 40 24a6ee05d9SSimran Rai 25a6ee05d9SSimran Rai struct ringbuf_regs { 26a6ee05d9SSimran Rai unsigned rdaddr; 27a6ee05d9SSimran Rai unsigned wraddr; 28a6ee05d9SSimran Rai unsigned baseaddr; 29a6ee05d9SSimran Rai unsigned endaddr; 30a6ee05d9SSimran Rai unsigned fmark; /* freemark for play, fullmark for caputure */ 31a6ee05d9SSimran Rai unsigned period_bytes; 32a6ee05d9SSimran Rai unsigned buf_size; 33a6ee05d9SSimran Rai }; 34a6ee05d9SSimran Rai 35a6ee05d9SSimran Rai #define RINGBUF_REG_PLAYBACK(num) ((struct ringbuf_regs) { \ 36a6ee05d9SSimran Rai .rdaddr = SRC_RBUF_ ##num## _RDADDR_OFFSET, \ 37a6ee05d9SSimran Rai .wraddr = SRC_RBUF_ ##num## _WRADDR_OFFSET, \ 38a6ee05d9SSimran Rai .baseaddr = SRC_RBUF_ ##num## _BASEADDR_OFFSET, \ 39a6ee05d9SSimran Rai .endaddr = SRC_RBUF_ ##num## _ENDADDR_OFFSET, \ 40a6ee05d9SSimran Rai .fmark = SRC_RBUF_ ##num## _FREE_MARK_OFFSET, \ 41a6ee05d9SSimran Rai .period_bytes = 0, \ 42a6ee05d9SSimran Rai .buf_size = 0, \ 43a6ee05d9SSimran Rai }) 44a6ee05d9SSimran Rai 45a6ee05d9SSimran Rai #define RINGBUF_REG_CAPTURE(num) ((struct ringbuf_regs) { \ 46a6ee05d9SSimran Rai .rdaddr = DST_RBUF_ ##num## _RDADDR_OFFSET, \ 47a6ee05d9SSimran Rai .wraddr = DST_RBUF_ ##num## _WRADDR_OFFSET, \ 48a6ee05d9SSimran Rai .baseaddr = DST_RBUF_ ##num## _BASEADDR_OFFSET, \ 49a6ee05d9SSimran Rai .endaddr = DST_RBUF_ ##num## _ENDADDR_OFFSET, \ 50a6ee05d9SSimran Rai .fmark = DST_RBUF_ ##num## _FULL_MARK_OFFSET, \ 51a6ee05d9SSimran Rai .period_bytes = 0, \ 52a6ee05d9SSimran Rai .buf_size = 0, \ 53a6ee05d9SSimran Rai }) 54a6ee05d9SSimran Rai 55a6ee05d9SSimran Rai enum cygnus_audio_port_type { 56a6ee05d9SSimran Rai PORT_TDM, 57a6ee05d9SSimran Rai PORT_SPDIF, 58a6ee05d9SSimran Rai }; 59a6ee05d9SSimran Rai 60a6ee05d9SSimran Rai struct cygnus_ssp_regs { 61a6ee05d9SSimran Rai u32 i2s_stream_cfg; 62a6ee05d9SSimran Rai u32 i2s_cfg; 63a6ee05d9SSimran Rai u32 i2s_cap_stream_cfg; 64a6ee05d9SSimran Rai u32 i2s_cap_cfg; 65a6ee05d9SSimran Rai u32 i2s_mclk_cfg; 66a6ee05d9SSimran Rai 67a6ee05d9SSimran Rai u32 bf_destch_ctrl; 68a6ee05d9SSimran Rai u32 bf_destch_cfg; 69a6ee05d9SSimran Rai u32 bf_sourcech_ctrl; 70a6ee05d9SSimran Rai u32 bf_sourcech_cfg; 71a6ee05d9SSimran Rai u32 bf_sourcech_grp; 72a6ee05d9SSimran Rai }; 73a6ee05d9SSimran Rai 74a6ee05d9SSimran Rai struct cygnus_track_clk { 75a6ee05d9SSimran Rai bool cap_en; 76a6ee05d9SSimran Rai bool play_en; 77a6ee05d9SSimran Rai bool cap_clk_en; 78a6ee05d9SSimran Rai bool play_clk_en; 79a6ee05d9SSimran Rai }; 80a6ee05d9SSimran Rai 81a6ee05d9SSimran Rai struct cygnus_aio_port { 82a6ee05d9SSimran Rai int portnum; 83a6ee05d9SSimran Rai int mode; 84a6ee05d9SSimran Rai bool is_slave; 85a6ee05d9SSimran Rai int streams_on; /* will be 0 if both capture and play are off */ 86a6ee05d9SSimran Rai int fsync_width; 87a6ee05d9SSimran Rai int port_type; 88a6ee05d9SSimran Rai 89a6ee05d9SSimran Rai u32 mclk; 90a6ee05d9SSimran Rai u32 lrclk; 91a6ee05d9SSimran Rai u32 bit_per_frame; 92a6ee05d9SSimran Rai u32 pll_clk_num; 93a6ee05d9SSimran Rai 94a6ee05d9SSimran Rai struct cygnus_audio *cygaud; 95a6ee05d9SSimran Rai struct cygnus_ssp_regs regs; 96a6ee05d9SSimran Rai 97a6ee05d9SSimran Rai struct ringbuf_regs play_rb_regs; 98a6ee05d9SSimran Rai struct ringbuf_regs capture_rb_regs; 99a6ee05d9SSimran Rai 100a6ee05d9SSimran Rai struct snd_pcm_substream *play_stream; 101a6ee05d9SSimran Rai struct snd_pcm_substream *capture_stream; 102a6ee05d9SSimran Rai 103a6ee05d9SSimran Rai struct cygnus_track_clk clk_trace; 104a6ee05d9SSimran Rai }; 105a6ee05d9SSimran Rai 106a6ee05d9SSimran Rai 107a6ee05d9SSimran Rai struct cygnus_audio { 108a6ee05d9SSimran Rai struct cygnus_aio_port portinfo[CYGNUS_MAX_PORTS]; 109a6ee05d9SSimran Rai 110a6ee05d9SSimran Rai int irq_num; 111a6ee05d9SSimran Rai void __iomem *audio; 112a6ee05d9SSimran Rai struct device *dev; 113a6ee05d9SSimran Rai void __iomem *i2s_in; 114a6ee05d9SSimran Rai 115a6ee05d9SSimran Rai struct clk *audio_clk[CYGNUS_AUIDO_MAX_NUM_CLKS]; 116a6ee05d9SSimran Rai int active_ports; 117a6ee05d9SSimran Rai unsigned long vco_rate; 118a6ee05d9SSimran Rai }; 119a6ee05d9SSimran Rai 120a6ee05d9SSimran Rai extern int cygnus_ssp_set_custom_fsync_width(struct snd_soc_dai *cpu_dai, 121a6ee05d9SSimran Rai int len); 122a6ee05d9SSimran Rai extern int cygnus_soc_platform_register(struct device *dev, 123a6ee05d9SSimran Rai struct cygnus_audio *cygaud); 124a6ee05d9SSimran Rai extern int cygnus_soc_platform_unregister(struct device *dev); 125a6ee05d9SSimran Rai extern int cygnus_ssp_set_custom_fsync_width(struct snd_soc_dai *cpu_dai, 126a6ee05d9SSimran Rai int len); 127a6ee05d9SSimran Rai #endif 128