1c62442bdSVijendar Mukunda /* SPDX-License-Identifier: GPL-2.0+ */
2c62442bdSVijendar Mukunda /*
3c62442bdSVijendar Mukunda * AMD ALSA SoC PDM Driver
4c62442bdSVijendar Mukunda *
5c62442bdSVijendar Mukunda * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
6c62442bdSVijendar Mukunda */
7c62442bdSVijendar Mukunda
8c62442bdSVijendar Mukunda #include "acp6x_chip_offset_byte.h"
9c62442bdSVijendar Mukunda
10c62442bdSVijendar Mukunda #define ACP_DEVICE_ID 0x15E2
11c62442bdSVijendar Mukunda #define ACP6x_PHY_BASE_ADDRESS 0x1240000
12fc329c1dSVijendar Mukunda #define ACP6x_REG_START 0x1240000
13fc329c1dSVijendar Mukunda #define ACP6x_REG_END 0x1250200
14058dfdf3SVijendar Mukunda #define ACP6x_DEVS 3
15fc329c1dSVijendar Mukunda #define ACP6x_PDM_MODE 1
16c62442bdSVijendar Mukunda
178c7161f2SVijendar Mukunda #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
188c7161f2SVijendar Mukunda #define ACP_PGFSM_CNTL_POWER_ON_MASK 1
198c7161f2SVijendar Mukunda #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
208c7161f2SVijendar Mukunda #define ACP_PGFSM_STATUS_MASK 3
218c7161f2SVijendar Mukunda #define ACP_POWERED_ON 0
228c7161f2SVijendar Mukunda #define ACP_POWER_ON_IN_PROGRESS 1
238c7161f2SVijendar Mukunda #define ACP_POWERED_OFF 2
248c7161f2SVijendar Mukunda #define ACP_POWER_OFF_IN_PROGRESS 3
258c7161f2SVijendar Mukunda
268c7161f2SVijendar Mukunda #define ACP_ERROR_MASK 0x20000000
278c7161f2SVijendar Mukunda #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
28cc0deaa2SVijendar Mukunda #define PDM_DMA_STAT 0x10
298c7161f2SVijendar Mukunda
30ceb4fcc1SVijendar Mukunda #define PDM_DMA_INTR_MASK 0x10000
31ceb4fcc1SVijendar Mukunda #define ACP_ERROR_STAT 29
32ceb4fcc1SVijendar Mukunda #define PDM_DECIMATION_FACTOR 2
33ceb4fcc1SVijendar Mukunda #define ACP_PDM_CLK_FREQ_MASK 7
3402ea45d1SMario Limonciello #define ACP_WOV_GAIN_CONTROL GENMASK(4, 3)
35ceb4fcc1SVijendar Mukunda #define ACP_PDM_ENABLE 1
36ceb4fcc1SVijendar Mukunda #define ACP_PDM_DISABLE 0
37ceb4fcc1SVijendar Mukunda #define ACP_PDM_DMA_EN_STATUS 2
38ceb4fcc1SVijendar Mukunda #define TWO_CH 2
39ceb4fcc1SVijendar Mukunda #define DELAY_US 5
40ceb4fcc1SVijendar Mukunda #define ACP_COUNTER 20000
41ceb4fcc1SVijendar Mukunda
42ceb4fcc1SVijendar Mukunda #define ACP_SRAM_PTE_OFFSET 0x03800000
43ceb4fcc1SVijendar Mukunda #define PAGE_SIZE_4K_ENABLE 2
44ceb4fcc1SVijendar Mukunda #define PDM_PTE_OFFSET 0
45ceb4fcc1SVijendar Mukunda #define PDM_MEM_WINDOW_START 0x4000000
46ceb4fcc1SVijendar Mukunda
47ceb4fcc1SVijendar Mukunda #define CAPTURE_MIN_NUM_PERIODS 4
48ceb4fcc1SVijendar Mukunda #define CAPTURE_MAX_NUM_PERIODS 4
49ceb4fcc1SVijendar Mukunda #define CAPTURE_MAX_PERIOD_SIZE 8192
50ceb4fcc1SVijendar Mukunda #define CAPTURE_MIN_PERIOD_SIZE 4096
51ceb4fcc1SVijendar Mukunda
52ceb4fcc1SVijendar Mukunda #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
53ceb4fcc1SVijendar Mukunda #define MIN_BUFFER MAX_BUFFER
54ceb4fcc1SVijendar Mukunda
55c8212df7SVijendar Mukunda /* time in ms for runtime suspend delay */
56c8212df7SVijendar Mukunda #define ACP_SUSPEND_DELAY_MS 2000
57c8212df7SVijendar Mukunda
58fc329c1dSVijendar Mukunda enum acp_config {
59fc329c1dSVijendar Mukunda ACP_CONFIG_0 = 0,
60fc329c1dSVijendar Mukunda ACP_CONFIG_1,
61fc329c1dSVijendar Mukunda ACP_CONFIG_2,
62fc329c1dSVijendar Mukunda ACP_CONFIG_3,
63fc329c1dSVijendar Mukunda ACP_CONFIG_4,
64fc329c1dSVijendar Mukunda ACP_CONFIG_5,
65fc329c1dSVijendar Mukunda ACP_CONFIG_6,
66fc329c1dSVijendar Mukunda ACP_CONFIG_7,
67fc329c1dSVijendar Mukunda ACP_CONFIG_8,
68fc329c1dSVijendar Mukunda ACP_CONFIG_9,
69fc329c1dSVijendar Mukunda ACP_CONFIG_10,
70fc329c1dSVijendar Mukunda ACP_CONFIG_11,
71fc329c1dSVijendar Mukunda ACP_CONFIG_12,
72fc329c1dSVijendar Mukunda ACP_CONFIG_13,
73fc329c1dSVijendar Mukunda ACP_CONFIG_14,
74fc329c1dSVijendar Mukunda ACP_CONFIG_15,
75fc329c1dSVijendar Mukunda };
76fc329c1dSVijendar Mukunda
777610174aSVijendar Mukunda struct pdm_dev_data {
78cc0deaa2SVijendar Mukunda u32 pdm_irq;
797610174aSVijendar Mukunda void __iomem *acp6x_base;
807610174aSVijendar Mukunda struct snd_pcm_substream *capture_stream;
817610174aSVijendar Mukunda };
827610174aSVijendar Mukunda
83ceb4fcc1SVijendar Mukunda struct pdm_stream_instance {
84ceb4fcc1SVijendar Mukunda u16 num_pages;
85ceb4fcc1SVijendar Mukunda u16 channels;
86ceb4fcc1SVijendar Mukunda dma_addr_t dma_addr;
87ceb4fcc1SVijendar Mukunda u64 bytescount;
88ceb4fcc1SVijendar Mukunda void __iomem *acp6x_base;
89ceb4fcc1SVijendar Mukunda };
90ceb4fcc1SVijendar Mukunda
91ceb4fcc1SVijendar Mukunda union acp_pdm_dma_count {
92ceb4fcc1SVijendar Mukunda struct {
93ceb4fcc1SVijendar Mukunda u32 low;
94ceb4fcc1SVijendar Mukunda u32 high;
95ceb4fcc1SVijendar Mukunda } bcount;
96ceb4fcc1SVijendar Mukunda u64 bytescount;
97ceb4fcc1SVijendar Mukunda };
98ceb4fcc1SVijendar Mukunda
acp6x_readl(void __iomem * base_addr)99c62442bdSVijendar Mukunda static inline u32 acp6x_readl(void __iomem *base_addr)
100c62442bdSVijendar Mukunda {
101c62442bdSVijendar Mukunda return readl(base_addr - ACP6x_PHY_BASE_ADDRESS);
102c62442bdSVijendar Mukunda }
103c62442bdSVijendar Mukunda
acp6x_writel(u32 val,void __iomem * base_addr)104c62442bdSVijendar Mukunda static inline void acp6x_writel(u32 val, void __iomem *base_addr)
105c62442bdSVijendar Mukunda {
106c62442bdSVijendar Mukunda writel(val, base_addr - ACP6x_PHY_BASE_ADDRESS);
107c62442bdSVijendar Mukunda }
108*bddcfb08SSyed Saba Kareem
109*bddcfb08SSyed Saba Kareem int snd_amd_acp_find_config(struct pci_dev *pci);
110*bddcfb08SSyed Saba Kareem
111