xref: /openbmc/linux/sound/pci/trident/trident.h (revision 762f99f4f3cb41a775b5157dd761217beba65873)
11a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
281fcb170STakashi Iwai #ifndef __SOUND_TRIDENT_H
381fcb170STakashi Iwai #define __SOUND_TRIDENT_H
481fcb170STakashi Iwai 
581fcb170STakashi Iwai /*
681fcb170STakashi Iwai  *  audio@tridentmicro.com
781fcb170STakashi Iwai  *  Fri Feb 19 15:55:28 MST 1999
881fcb170STakashi Iwai  *  Definitions for Trident 4DWave DX/NX chips
981fcb170STakashi Iwai  */
1081fcb170STakashi Iwai 
1181fcb170STakashi Iwai #include <sound/pcm.h>
1281fcb170STakashi Iwai #include <sound/mpu401.h>
1381fcb170STakashi Iwai #include <sound/ac97_codec.h>
1481fcb170STakashi Iwai #include <sound/util_mem.h>
1581fcb170STakashi Iwai 
1681fcb170STakashi Iwai #define TRIDENT_DEVICE_ID_DX		((PCI_VENDOR_ID_TRIDENT<<16)|PCI_DEVICE_ID_TRIDENT_4DWAVE_DX)
1781fcb170STakashi Iwai #define TRIDENT_DEVICE_ID_NX		((PCI_VENDOR_ID_TRIDENT<<16)|PCI_DEVICE_ID_TRIDENT_4DWAVE_NX)
1881fcb170STakashi Iwai #define TRIDENT_DEVICE_ID_SI7018	((PCI_VENDOR_ID_SI<<16)|PCI_DEVICE_ID_SI_7018)
1981fcb170STakashi Iwai 
2081fcb170STakashi Iwai #define SNDRV_TRIDENT_VOICE_TYPE_PCM		0
2181fcb170STakashi Iwai #define SNDRV_TRIDENT_VOICE_TYPE_SYNTH		1
2281fcb170STakashi Iwai #define SNDRV_TRIDENT_VOICE_TYPE_MIDI		2
2381fcb170STakashi Iwai 
2481fcb170STakashi Iwai #define SNDRV_TRIDENT_VFLG_RUNNING		(1<<0)
2581fcb170STakashi Iwai 
2681fcb170STakashi Iwai /* TLB code constants */
2781fcb170STakashi Iwai #define SNDRV_TRIDENT_PAGE_SIZE			4096
2881fcb170STakashi Iwai #define SNDRV_TRIDENT_PAGE_SHIFT			12
2981fcb170STakashi Iwai #define SNDRV_TRIDENT_PAGE_MASK			((1<<SNDRV_TRIDENT_PAGE_SHIFT)-1)
3081fcb170STakashi Iwai #define SNDRV_TRIDENT_MAX_PAGES			4096
3181fcb170STakashi Iwai 
3281fcb170STakashi Iwai /*
3381fcb170STakashi Iwai  * Direct registers
3481fcb170STakashi Iwai  */
3581fcb170STakashi Iwai 
3681fcb170STakashi Iwai #define TRID_REG(trident, x) ((trident)->port + (x))
3781fcb170STakashi Iwai 
3881fcb170STakashi Iwai #define ID_4DWAVE_DX        0x2000
3981fcb170STakashi Iwai #define ID_4DWAVE_NX        0x2001
4081fcb170STakashi Iwai 
4181fcb170STakashi Iwai /* Bank definitions */
4281fcb170STakashi Iwai 
4381fcb170STakashi Iwai #define T4D_BANK_A	0
4481fcb170STakashi Iwai #define T4D_BANK_B	1
4581fcb170STakashi Iwai #define T4D_NUM_BANKS	2
4681fcb170STakashi Iwai 
4781fcb170STakashi Iwai /* Register definitions */
4881fcb170STakashi Iwai 
4981fcb170STakashi Iwai /* Global registers */
5081fcb170STakashi Iwai 
5181fcb170STakashi Iwai enum global_control_bits {
5281fcb170STakashi Iwai 	CHANNEL_IDX	= 0x0000003f,
5381fcb170STakashi Iwai 	OVERRUN_IE	= 0x00000400,	/* interrupt enable: capture overrun */
5481fcb170STakashi Iwai 	UNDERRUN_IE	= 0x00000800,	/* interrupt enable: playback underrun */
5581fcb170STakashi Iwai 	ENDLP_IE	= 0x00001000,	/* interrupt enable: end of buffer */
5681fcb170STakashi Iwai 	MIDLP_IE	= 0x00002000,	/* interrupt enable: middle buffer */
5781fcb170STakashi Iwai 	ETOG_IE		= 0x00004000,	/* interrupt enable: envelope toggling */
5881fcb170STakashi Iwai 	EDROP_IE	= 0x00008000,	/* interrupt enable: envelope drop */
5981fcb170STakashi Iwai 	BANK_B_EN	= 0x00010000,	/* SiS: enable bank B (64 channels) */
6081fcb170STakashi Iwai 	PCMIN_B_MIX	= 0x00020000,	/* SiS: PCM IN B mixing enable */
6181fcb170STakashi Iwai 	I2S_OUT_ASSIGN	= 0x00040000,	/* SiS: I2S Out contains surround PCM */
6281fcb170STakashi Iwai 	SPDIF_OUT_ASSIGN= 0x00080000,	/* SiS: 0=S/PDIF L/R | 1=PCM Out FIFO */
6381fcb170STakashi Iwai 	MAIN_OUT_ASSIGN = 0x00100000,	/* SiS: 0=PCM Out FIFO | 1=MMC Out buffer */
6481fcb170STakashi Iwai };
6581fcb170STakashi Iwai 
6681fcb170STakashi Iwai enum miscint_bits {
6781fcb170STakashi Iwai 	PB_UNDERRUN_IRQ = 0x00000001, REC_OVERRUN_IRQ = 0x00000002,
6881fcb170STakashi Iwai 	SB_IRQ		= 0x00000004, MPU401_IRQ      = 0x00000008,
6981fcb170STakashi Iwai 	OPL3_IRQ        = 0x00000010, ADDRESS_IRQ     = 0x00000020,
7081fcb170STakashi Iwai 	ENVELOPE_IRQ    = 0x00000040, PB_UNDERRUN     = 0x00000100,
7181fcb170STakashi Iwai 	REC_OVERRUN	= 0x00000200, MIXER_UNDERFLOW = 0x00000400,
7281fcb170STakashi Iwai 	MIXER_OVERFLOW  = 0x00000800, NX_SB_IRQ_DISABLE = 0x00001000,
7381fcb170STakashi Iwai         ST_TARGET_REACHED = 0x00008000,
7481fcb170STakashi Iwai 	PB_24K_MODE     = 0x00010000, ST_IRQ_EN       = 0x00800000,
7581fcb170STakashi Iwai 	ACGPIO_IRQ	= 0x01000000
7681fcb170STakashi Iwai };
7781fcb170STakashi Iwai 
7881fcb170STakashi Iwai /* T2 legacy dma control registers. */
7981fcb170STakashi Iwai #define LEGACY_DMAR0                0x00  // ADR0
8081fcb170STakashi Iwai #define LEGACY_DMAR4                0x04  // CNT0
8181fcb170STakashi Iwai #define LEGACY_DMAR6		    0x06  // CNT0 - High bits
8281fcb170STakashi Iwai #define LEGACY_DMAR11               0x0b  // MOD
8381fcb170STakashi Iwai #define LEGACY_DMAR15               0x0f  // MMR
8481fcb170STakashi Iwai 
8581fcb170STakashi Iwai #define T4D_START_A		     0x80
8681fcb170STakashi Iwai #define T4D_STOP_A		     0x84
8781fcb170STakashi Iwai #define T4D_DLY_A		     0x88
8881fcb170STakashi Iwai #define T4D_SIGN_CSO_A		     0x8c
8981fcb170STakashi Iwai #define T4D_CSPF_A		     0x90
9081fcb170STakashi Iwai #define T4D_CSPF_B		     0xbc
9181fcb170STakashi Iwai #define T4D_CEBC_A		     0x94
9281fcb170STakashi Iwai #define T4D_AINT_A		     0x98
9381fcb170STakashi Iwai #define T4D_AINTEN_A		     0x9c
9481fcb170STakashi Iwai #define T4D_LFO_GC_CIR               0xa0
9581fcb170STakashi Iwai #define T4D_MUSICVOL_WAVEVOL         0xa8
9681fcb170STakashi Iwai #define T4D_SBDELTA_DELTA_R          0xac
9781fcb170STakashi Iwai #define T4D_MISCINT                  0xb0
9881fcb170STakashi Iwai #define T4D_START_B                  0xb4
9981fcb170STakashi Iwai #define T4D_STOP_B                   0xb8
10081fcb170STakashi Iwai #define T4D_SBBL_SBCL                0xc0
10181fcb170STakashi Iwai #define T4D_SBCTRL_SBE2R_SBDD        0xc4
10281fcb170STakashi Iwai #define T4D_STIMER		     0xc8
10381fcb170STakashi Iwai #define T4D_AINT_B                   0xd8
10481fcb170STakashi Iwai #define T4D_AINTEN_B                 0xdc
10581fcb170STakashi Iwai #define T4D_RCI                      0x70
10681fcb170STakashi Iwai 
10781fcb170STakashi Iwai /* MPU-401 UART */
10881fcb170STakashi Iwai #define T4D_MPU401_BASE             0x20
10981fcb170STakashi Iwai #define T4D_MPUR0                   0x20
11081fcb170STakashi Iwai #define T4D_MPUR1                   0x21
11181fcb170STakashi Iwai #define T4D_MPUR2                   0x22
11281fcb170STakashi Iwai #define T4D_MPUR3                   0x23
11381fcb170STakashi Iwai 
11481fcb170STakashi Iwai /* S/PDIF Registers */
11581fcb170STakashi Iwai #define NX_SPCTRL_SPCSO             0x24
11681fcb170STakashi Iwai #define NX_SPLBA                    0x28
11781fcb170STakashi Iwai #define NX_SPESO                    0x2c
11881fcb170STakashi Iwai #define NX_SPCSTATUS                0x64
11981fcb170STakashi Iwai 
12081fcb170STakashi Iwai /* Joystick */
12181fcb170STakashi Iwai #define GAMEPORT_GCR                0x30
12281fcb170STakashi Iwai #define GAMEPORT_MODE_ADC           0x80
12381fcb170STakashi Iwai #define GAMEPORT_LEGACY             0x31
12481fcb170STakashi Iwai #define GAMEPORT_AXES               0x34
12581fcb170STakashi Iwai 
12681fcb170STakashi Iwai /* NX Specific Registers */
12781fcb170STakashi Iwai #define NX_TLBC                     0x6c
12881fcb170STakashi Iwai 
12981fcb170STakashi Iwai /* Channel Registers */
13081fcb170STakashi Iwai 
13181fcb170STakashi Iwai #define CH_START		    0xe0
13281fcb170STakashi Iwai 
13381fcb170STakashi Iwai #define CH_DX_CSO_ALPHA_FMS         0xe0
13481fcb170STakashi Iwai #define CH_DX_ESO_DELTA             0xe8
13581fcb170STakashi Iwai #define CH_DX_FMC_RVOL_CVOL         0xec
13681fcb170STakashi Iwai 
13781fcb170STakashi Iwai #define CH_NX_DELTA_CSO             0xe0
13881fcb170STakashi Iwai #define CH_NX_DELTA_ESO             0xe8
13981fcb170STakashi Iwai #define CH_NX_ALPHA_FMS_FMC_RVOL_CVOL 0xec
14081fcb170STakashi Iwai 
14181fcb170STakashi Iwai #define CH_LBA                      0xe4
14281fcb170STakashi Iwai #define CH_GVSEL_PAN_VOL_CTRL_EC    0xf0
14381fcb170STakashi Iwai #define CH_EBUF1                    0xf4
14481fcb170STakashi Iwai #define CH_EBUF2                    0xf8
14581fcb170STakashi Iwai 
14681fcb170STakashi Iwai /* AC-97 Registers */
14781fcb170STakashi Iwai 
14881fcb170STakashi Iwai #define DX_ACR0_AC97_W              0x40
14981fcb170STakashi Iwai #define DX_ACR1_AC97_R              0x44
15081fcb170STakashi Iwai #define DX_ACR2_AC97_COM_STAT       0x48
15181fcb170STakashi Iwai 
15281fcb170STakashi Iwai #define NX_ACR0_AC97_COM_STAT       0x40
15381fcb170STakashi Iwai #define NX_ACR1_AC97_W              0x44
15481fcb170STakashi Iwai #define NX_ACR2_AC97_R_PRIMARY      0x48
15581fcb170STakashi Iwai #define NX_ACR3_AC97_R_SECONDARY    0x4c
15681fcb170STakashi Iwai 
15781fcb170STakashi Iwai #define SI_AC97_WRITE		    0x40
15881fcb170STakashi Iwai #define SI_AC97_READ		    0x44
15981fcb170STakashi Iwai #define SI_SERIAL_INTF_CTRL	    0x48
16081fcb170STakashi Iwai #define SI_AC97_GPIO		    0x4c
16181fcb170STakashi Iwai #define SI_ASR0			    0x50
16281fcb170STakashi Iwai #define SI_SPDIF_CS		    0x70
16381fcb170STakashi Iwai #define SI_GPIO			    0x7c
16481fcb170STakashi Iwai 
16581fcb170STakashi Iwai enum trident_nx_ac97_bits {
16681fcb170STakashi Iwai 	/* ACR1-3 */
16781fcb170STakashi Iwai 	NX_AC97_BUSY_WRITE 	= 0x0800,
16881fcb170STakashi Iwai 	NX_AC97_BUSY_READ	= 0x0800,
16981fcb170STakashi Iwai 	NX_AC97_BUSY_DATA 	= 0x0400,
17081fcb170STakashi Iwai 	NX_AC97_WRITE_SECONDARY = 0x0100,
17181fcb170STakashi Iwai 	/* ACR0 */
17281fcb170STakashi Iwai 	NX_AC97_SECONDARY_READY = 0x0040,
17381fcb170STakashi Iwai 	NX_AC97_SECONDARY_RECORD = 0x0020,
17481fcb170STakashi Iwai 	NX_AC97_SURROUND_OUTPUT = 0x0010,
17581fcb170STakashi Iwai 	NX_AC97_PRIMARY_READY	= 0x0008,
17681fcb170STakashi Iwai 	NX_AC97_PRIMARY_RECORD	= 0x0004,
17781fcb170STakashi Iwai 	NX_AC97_PCM_OUTPUT	= 0x0002,
17881fcb170STakashi Iwai 	NX_AC97_WARM_RESET	= 0x0001
17981fcb170STakashi Iwai };
18081fcb170STakashi Iwai 
18181fcb170STakashi Iwai enum trident_dx_ac97_bits {
18281fcb170STakashi Iwai 	DX_AC97_BUSY_WRITE	= 0x8000,
18381fcb170STakashi Iwai 	DX_AC97_BUSY_READ	= 0x8000,
18481fcb170STakashi Iwai 	DX_AC97_READY		= 0x0010,
18581fcb170STakashi Iwai 	DX_AC97_RECORD		= 0x0008,
18681fcb170STakashi Iwai 	DX_AC97_PLAYBACK	= 0x0002
18781fcb170STakashi Iwai };
18881fcb170STakashi Iwai 
18981fcb170STakashi Iwai enum sis7018_ac97_bits {
19081fcb170STakashi Iwai 	SI_AC97_BUSY_WRITE =	0x00008000,
19181fcb170STakashi Iwai 	SI_AC97_AUDIO_BUSY =	0x00004000,
19281fcb170STakashi Iwai 	SI_AC97_MODEM_BUSY =	0x00002000,
19381fcb170STakashi Iwai 	SI_AC97_BUSY_READ =	0x00008000,
19481fcb170STakashi Iwai 	SI_AC97_SECONDARY =	0x00000080,
19581fcb170STakashi Iwai };
19681fcb170STakashi Iwai 
19781fcb170STakashi Iwai enum serial_intf_ctrl_bits {
19881fcb170STakashi Iwai 	WARM_RESET	= 0x00000001,
19981fcb170STakashi Iwai 	COLD_RESET	= 0x00000002,
20081fcb170STakashi Iwai 	I2S_CLOCK	= 0x00000004,
20181fcb170STakashi Iwai 	PCM_SEC_AC97	= 0x00000008,
20281fcb170STakashi Iwai 	AC97_DBL_RATE	= 0x00000010,
20381fcb170STakashi Iwai 	SPDIF_EN	= 0x00000020,
20481fcb170STakashi Iwai 	I2S_OUTPUT_EN	= 0x00000040,
20581fcb170STakashi Iwai 	I2S_INPUT_EN	= 0x00000080,
20681fcb170STakashi Iwai 	PCMIN		= 0x00000100,
20781fcb170STakashi Iwai 	LINE1IN		= 0x00000200,
20881fcb170STakashi Iwai 	MICIN		= 0x00000400,
20981fcb170STakashi Iwai 	LINE2IN		= 0x00000800,
21081fcb170STakashi Iwai 	HEAD_SET_IN	= 0x00001000,
21181fcb170STakashi Iwai 	GPIOIN		= 0x00002000,
21281fcb170STakashi Iwai 	/* 7018 spec says id = 01 but the demo board routed to 10
21381fcb170STakashi Iwai 	   SECONDARY_ID= 0x00004000, */
21481fcb170STakashi Iwai 	SECONDARY_ID	= 0x00004000,
21581fcb170STakashi Iwai 	PCMOUT		= 0x00010000,
21681fcb170STakashi Iwai 	SURROUT		= 0x00020000,
21781fcb170STakashi Iwai 	CENTEROUT	= 0x00040000,
21881fcb170STakashi Iwai 	LFEOUT		= 0x00080000,
21981fcb170STakashi Iwai 	LINE1OUT	= 0x00100000,
22081fcb170STakashi Iwai 	LINE2OUT	= 0x00200000,
22181fcb170STakashi Iwai 	GPIOOUT		= 0x00400000,
22281fcb170STakashi Iwai 	SI_AC97_PRIMARY_READY = 0x01000000,
22381fcb170STakashi Iwai 	SI_AC97_SECONDARY_READY = 0x02000000,
22481fcb170STakashi Iwai 	SI_AC97_POWERDOWN = 0x04000000,
22581fcb170STakashi Iwai };
22681fcb170STakashi Iwai 
22781fcb170STakashi Iwai /* PCM defaults */
22881fcb170STakashi Iwai 
22981fcb170STakashi Iwai #define T4D_DEFAULT_PCM_VOL	10	/* 0 - 255 */
23081fcb170STakashi Iwai #define T4D_DEFAULT_PCM_PAN	0	/* 0 - 127 */
23181fcb170STakashi Iwai #define T4D_DEFAULT_PCM_RVOL	127	/* 0 - 127 */
23281fcb170STakashi Iwai #define T4D_DEFAULT_PCM_CVOL	127	/* 0 - 127 */
23381fcb170STakashi Iwai 
23481fcb170STakashi Iwai struct snd_trident;
23581fcb170STakashi Iwai struct snd_trident_voice;
23681fcb170STakashi Iwai struct snd_trident_pcm_mixer;
23781fcb170STakashi Iwai 
23881fcb170STakashi Iwai struct snd_trident_port {
23981fcb170STakashi Iwai 	struct snd_midi_channel_set * chset;
24081fcb170STakashi Iwai 	struct snd_trident * trident;
24181fcb170STakashi Iwai 	int mode;		/* operation mode */
24281fcb170STakashi Iwai 	int client;		/* sequencer client number */
24381fcb170STakashi Iwai 	int port;		/* sequencer port number */
24481fcb170STakashi Iwai 	unsigned int midi_has_voices: 1;
24581fcb170STakashi Iwai };
24681fcb170STakashi Iwai 
24781fcb170STakashi Iwai struct snd_trident_memblk_arg {
24881fcb170STakashi Iwai 	short first_page, last_page;
24981fcb170STakashi Iwai };
25081fcb170STakashi Iwai 
25181fcb170STakashi Iwai struct snd_trident_tlb {
252752089feSTakashi Iwai 	__le32 *entries;		/* 16k-aligned TLB table */
25381fcb170STakashi Iwai 	dma_addr_t entries_dmaaddr;	/* 16k-aligned PCI address to TLB table */
254*5adfd8c2STakashi Iwai 	struct snd_dma_buffer *buffer;
25581fcb170STakashi Iwai 	struct snd_util_memhdr * memhdr;	/* page allocation list */
256*5adfd8c2STakashi Iwai 	struct snd_dma_buffer *silent_page;
25781fcb170STakashi Iwai };
25881fcb170STakashi Iwai 
25981fcb170STakashi Iwai struct snd_trident_voice {
26081fcb170STakashi Iwai 	unsigned int number;
26181fcb170STakashi Iwai 	unsigned int use: 1,
26281fcb170STakashi Iwai 	    pcm: 1,
26381fcb170STakashi Iwai 	    synth:1,
26481fcb170STakashi Iwai 	    midi: 1;
26581fcb170STakashi Iwai 	unsigned int flags;
26681fcb170STakashi Iwai 	unsigned char client;
26781fcb170STakashi Iwai 	unsigned char port;
26881fcb170STakashi Iwai 	unsigned char index;
26981fcb170STakashi Iwai 
27081fcb170STakashi Iwai 	struct snd_trident_sample_ops *sample_ops;
27181fcb170STakashi Iwai 
27281fcb170STakashi Iwai 	/* channel parameters */
27381fcb170STakashi Iwai 	unsigned int CSO;		/* 24 bits (16 on DX) */
27481fcb170STakashi Iwai 	unsigned int ESO;		/* 24 bits (16 on DX) */
27581fcb170STakashi Iwai 	unsigned int LBA;		/* 30 bits */
27681fcb170STakashi Iwai 	unsigned short EC;		/* 12 bits */
27781fcb170STakashi Iwai 	unsigned short Alpha;		/* 12 bits */
27881fcb170STakashi Iwai 	unsigned short Delta;		/* 16 bits */
27981fcb170STakashi Iwai 	unsigned short Attribute;	/* 16 bits - SiS 7018 */
28081fcb170STakashi Iwai 	unsigned short Vol;		/* 12 bits (6.6) */
28181fcb170STakashi Iwai 	unsigned char Pan;		/* 7 bits (1.4.2) */
28281fcb170STakashi Iwai 	unsigned char GVSel;		/* 1 bit */
28381fcb170STakashi Iwai 	unsigned char RVol;		/* 7 bits (5.2) */
28481fcb170STakashi Iwai 	unsigned char CVol;		/* 7 bits (5.2) */
28581fcb170STakashi Iwai 	unsigned char FMC;		/* 2 bits */
28681fcb170STakashi Iwai 	unsigned char CTRL;		/* 4 bits */
28781fcb170STakashi Iwai 	unsigned char FMS;		/* 4 bits */
28881fcb170STakashi Iwai 	unsigned char LFO;		/* 8 bits */
28981fcb170STakashi Iwai 
29081fcb170STakashi Iwai 	unsigned int negCSO;	/* nonzero - use negative CSO */
29181fcb170STakashi Iwai 
29281fcb170STakashi Iwai 	struct snd_util_memblk *memblk;	/* memory block if TLB enabled */
29381fcb170STakashi Iwai 
29481fcb170STakashi Iwai 	/* PCM data */
29581fcb170STakashi Iwai 
29681fcb170STakashi Iwai 	struct snd_trident *trident;
29781fcb170STakashi Iwai 	struct snd_pcm_substream *substream;
29881fcb170STakashi Iwai 	struct snd_trident_voice *extra;	/* extra PCM voice (acts as interrupt generator) */
29981fcb170STakashi Iwai 	unsigned int running: 1,
30081fcb170STakashi Iwai             capture: 1,
30181fcb170STakashi Iwai             spdif: 1,
30281fcb170STakashi Iwai             foldback: 1,
30381fcb170STakashi Iwai             isync: 1,
30481fcb170STakashi Iwai             isync2: 1,
30581fcb170STakashi Iwai             isync3: 1;
30681fcb170STakashi Iwai 	int foldback_chan;		/* foldback subdevice number */
30781fcb170STakashi Iwai 	unsigned int stimer;		/* global sample timer (to detect spurious interrupts) */
30881fcb170STakashi Iwai 	unsigned int spurious_threshold; /* spurious threshold */
30981fcb170STakashi Iwai 	unsigned int isync_mark;
31081fcb170STakashi Iwai 	unsigned int isync_max;
31181fcb170STakashi Iwai 	unsigned int isync_ESO;
31281fcb170STakashi Iwai 
31381fcb170STakashi Iwai 	/* --- */
31481fcb170STakashi Iwai 
31581fcb170STakashi Iwai 	void *private_data;
31681fcb170STakashi Iwai 	void (*private_free)(struct snd_trident_voice *voice);
31781fcb170STakashi Iwai };
31881fcb170STakashi Iwai 
31981fcb170STakashi Iwai struct snd_4dwave {
32081fcb170STakashi Iwai 	int seq_client;
32181fcb170STakashi Iwai 
32281fcb170STakashi Iwai 	struct snd_trident_port seq_ports[4];
32381fcb170STakashi Iwai 	struct snd_trident_voice voices[64];
32481fcb170STakashi Iwai 
32581fcb170STakashi Iwai 	int ChanSynthCount;		/* number of allocated synth channels */
32681fcb170STakashi Iwai 	int max_size;			/* maximum synth memory size in bytes */
32781fcb170STakashi Iwai 	int current_size;		/* current allocated synth mem in bytes */
32881fcb170STakashi Iwai };
32981fcb170STakashi Iwai 
33081fcb170STakashi Iwai struct snd_trident_pcm_mixer {
33181fcb170STakashi Iwai 	struct snd_trident_voice *voice;	/* active voice */
33281fcb170STakashi Iwai 	unsigned short vol;		/* front volume */
33381fcb170STakashi Iwai 	unsigned char pan;		/* pan control */
33481fcb170STakashi Iwai 	unsigned char rvol;		/* rear volume */
33581fcb170STakashi Iwai 	unsigned char cvol;		/* center volume */
33681fcb170STakashi Iwai 	unsigned char pad;
33781fcb170STakashi Iwai };
33881fcb170STakashi Iwai 
33981fcb170STakashi Iwai struct snd_trident {
34081fcb170STakashi Iwai 	int irq;
34181fcb170STakashi Iwai 
34281fcb170STakashi Iwai 	unsigned int device;	/* device ID */
34381fcb170STakashi Iwai 
34481fcb170STakashi Iwai         unsigned char  bDMAStart;
34581fcb170STakashi Iwai 
34681fcb170STakashi Iwai 	unsigned long port;
34781fcb170STakashi Iwai 	unsigned long midi_port;
34881fcb170STakashi Iwai 
34981fcb170STakashi Iwai 	unsigned int spurious_irq_count;
35081fcb170STakashi Iwai 	unsigned int spurious_irq_max_delta;
35181fcb170STakashi Iwai 
35281fcb170STakashi Iwai         struct snd_trident_tlb tlb;	/* TLB entries for NX cards */
35381fcb170STakashi Iwai 
35481fcb170STakashi Iwai 	unsigned char spdif_ctrl;
35581fcb170STakashi Iwai 	unsigned char spdif_pcm_ctrl;
35681fcb170STakashi Iwai 	unsigned int spdif_bits;
35781fcb170STakashi Iwai 	unsigned int spdif_pcm_bits;
35881fcb170STakashi Iwai 	struct snd_kcontrol *spdif_pcm_ctl;	/* S/PDIF settings */
35981fcb170STakashi Iwai 	unsigned int ac97_ctrl;
36081fcb170STakashi Iwai 
36181fcb170STakashi Iwai         unsigned int ChanMap[2];	/* allocation map for hardware channels */
36281fcb170STakashi Iwai 
36381fcb170STakashi Iwai         int ChanPCM;			/* max number of PCM channels */
36481fcb170STakashi Iwai 	int ChanPCMcnt;			/* actual number of PCM channels */
36581fcb170STakashi Iwai 
36681fcb170STakashi Iwai 	unsigned int ac97_detect: 1;	/* 1 = AC97 in detection phase */
36781fcb170STakashi Iwai 	unsigned int in_suspend: 1;	/* 1 during suspend/resume */
36881fcb170STakashi Iwai 
36981fcb170STakashi Iwai 	struct snd_4dwave synth;	/* synth specific variables */
37081fcb170STakashi Iwai 
37181fcb170STakashi Iwai 	spinlock_t event_lock;
37281fcb170STakashi Iwai 	spinlock_t voice_alloc;
37381fcb170STakashi Iwai 
37481fcb170STakashi Iwai 	struct snd_dma_device dma_dev;
37581fcb170STakashi Iwai 
37681fcb170STakashi Iwai 	struct pci_dev *pci;
37781fcb170STakashi Iwai 	struct snd_card *card;
37881fcb170STakashi Iwai 	struct snd_pcm *pcm;		/* ADC/DAC PCM */
37981fcb170STakashi Iwai 	struct snd_pcm *foldback;	/* Foldback PCM */
38081fcb170STakashi Iwai 	struct snd_pcm *spdif;	/* SPDIF PCM */
38181fcb170STakashi Iwai 	struct snd_rawmidi *rmidi;
38281fcb170STakashi Iwai 
38381fcb170STakashi Iwai 	struct snd_ac97_bus *ac97_bus;
38481fcb170STakashi Iwai 	struct snd_ac97 *ac97;
38581fcb170STakashi Iwai 	struct snd_ac97 *ac97_sec;
38681fcb170STakashi Iwai 
38781fcb170STakashi Iwai 	unsigned int musicvol_wavevol;
38881fcb170STakashi Iwai 	struct snd_trident_pcm_mixer pcm_mixer[32];
38981fcb170STakashi Iwai 	struct snd_kcontrol *ctl_vol;	/* front volume */
39081fcb170STakashi Iwai 	struct snd_kcontrol *ctl_pan;	/* pan */
39181fcb170STakashi Iwai 	struct snd_kcontrol *ctl_rvol;	/* rear volume */
39281fcb170STakashi Iwai 	struct snd_kcontrol *ctl_cvol;	/* center volume */
39381fcb170STakashi Iwai 
39481fcb170STakashi Iwai 	spinlock_t reg_lock;
39581fcb170STakashi Iwai 
39681fcb170STakashi Iwai 	struct gameport *gameport;
39781fcb170STakashi Iwai };
39881fcb170STakashi Iwai 
39981fcb170STakashi Iwai int snd_trident_create(struct snd_card *card,
40081fcb170STakashi Iwai 		       struct pci_dev *pci,
40181fcb170STakashi Iwai 		       int pcm_streams,
40281fcb170STakashi Iwai 		       int pcm_spdif_device,
403*5adfd8c2STakashi Iwai 		       int max_wavetable_size);
40481fcb170STakashi Iwai int snd_trident_create_gameport(struct snd_trident *trident);
40581fcb170STakashi Iwai 
4061b16416fSLars-Peter Clausen int snd_trident_pcm(struct snd_trident *trident, int device);
4071b16416fSLars-Peter Clausen int snd_trident_foldback_pcm(struct snd_trident *trident, int device);
4081b16416fSLars-Peter Clausen int snd_trident_spdif_pcm(struct snd_trident *trident, int device);
40981fcb170STakashi Iwai int snd_trident_attach_synthesizer(struct snd_trident * trident);
41081fcb170STakashi Iwai struct snd_trident_voice *snd_trident_alloc_voice(struct snd_trident * trident, int type,
41181fcb170STakashi Iwai 					     int client, int port);
41281fcb170STakashi Iwai void snd_trident_free_voice(struct snd_trident * trident, struct snd_trident_voice *voice);
41381fcb170STakashi Iwai void snd_trident_start_voice(struct snd_trident * trident, unsigned int voice);
41481fcb170STakashi Iwai void snd_trident_stop_voice(struct snd_trident * trident, unsigned int voice);
41581fcb170STakashi Iwai void snd_trident_write_voice_regs(struct snd_trident * trident, struct snd_trident_voice *voice);
41681fcb170STakashi Iwai extern const struct dev_pm_ops snd_trident_pm;
41781fcb170STakashi Iwai 
41881fcb170STakashi Iwai /* TLB memory allocation */
41981fcb170STakashi Iwai struct snd_util_memblk *snd_trident_alloc_pages(struct snd_trident *trident,
42081fcb170STakashi Iwai 						struct snd_pcm_substream *substream);
42181fcb170STakashi Iwai int snd_trident_free_pages(struct snd_trident *trident, struct snd_util_memblk *blk);
42281fcb170STakashi Iwai struct snd_util_memblk *snd_trident_synth_alloc(struct snd_trident *trident, unsigned int size);
42381fcb170STakashi Iwai int snd_trident_synth_free(struct snd_trident *trident, struct snd_util_memblk *blk);
42481fcb170STakashi Iwai int snd_trident_synth_copy_from_user(struct snd_trident *trident, struct snd_util_memblk *blk,
42581fcb170STakashi Iwai 				     int offset, const char __user *data, int size);
42681fcb170STakashi Iwai 
42781fcb170STakashi Iwai #endif /* __SOUND_TRIDENT_H */
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