xref: /openbmc/linux/sound/pci/rme96.c (revision e868d61272caa648214046a096e5a6bfc068dc8c)
1 /*
2  *   ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
3  *   interfaces
4  *
5  *	Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
6  *
7  *      Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
8  *      code.
9  *
10  *   This program is free software; you can redistribute it and/or modify
11  *   it under the terms of the GNU General Public License as published by
12  *   the Free Software Foundation; either version 2 of the License, or
13  *   (at your option) any later version.
14  *
15  *   This program is distributed in the hope that it will be useful,
16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  *   GNU General Public License for more details.
19  *
20  *   You should have received a copy of the GNU General Public License
21  *   along with this program; if not, write to the Free Software
22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  */
25 
26 #include <sound/driver.h>
27 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32 #include <linux/moduleparam.h>
33 
34 #include <sound/core.h>
35 #include <sound/info.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/pcm_params.h>
39 #include <sound/asoundef.h>
40 #include <sound/initval.h>
41 
42 #include <asm/io.h>
43 
44 /* note, two last pcis should be equal, it is not a bug */
45 
46 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
47 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
48 		   "Digi96/8 PAD");
49 MODULE_LICENSE("GPL");
50 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
51 		"{RME,Digi96/8},"
52 		"{RME,Digi96/8 PRO},"
53 		"{RME,Digi96/8 PST},"
54 		"{RME,Digi96/8 PAD}}");
55 
56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable this card */
59 
60 module_param_array(index, int, NULL, 0444);
61 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
62 module_param_array(id, charp, NULL, 0444);
63 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
64 module_param_array(enable, bool, NULL, 0444);
65 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
66 
67 /*
68  * Defines for RME Digi96 series, from internal RME reference documents
69  * dated 12.01.00
70  */
71 
72 #define RME96_SPDIF_NCHANNELS 2
73 
74 /* Playback and capture buffer size */
75 #define RME96_BUFFER_SIZE 0x10000
76 
77 /* IO area size */
78 #define RME96_IO_SIZE 0x60000
79 
80 /* IO area offsets */
81 #define RME96_IO_PLAY_BUFFER      0x0
82 #define RME96_IO_REC_BUFFER       0x10000
83 #define RME96_IO_CONTROL_REGISTER 0x20000
84 #define RME96_IO_ADDITIONAL_REG   0x20004
85 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
86 #define RME96_IO_CONFIRM_REC_IRQ  0x2000C
87 #define RME96_IO_SET_PLAY_POS     0x40000
88 #define RME96_IO_RESET_PLAY_POS   0x4FFFC
89 #define RME96_IO_SET_REC_POS      0x50000
90 #define RME96_IO_RESET_REC_POS    0x5FFFC
91 #define RME96_IO_GET_PLAY_POS     0x20000
92 #define RME96_IO_GET_REC_POS      0x30000
93 
94 /* Write control register bits */
95 #define RME96_WCR_START     (1 << 0)
96 #define RME96_WCR_START_2   (1 << 1)
97 #define RME96_WCR_GAIN_0    (1 << 2)
98 #define RME96_WCR_GAIN_1    (1 << 3)
99 #define RME96_WCR_MODE24    (1 << 4)
100 #define RME96_WCR_MODE24_2  (1 << 5)
101 #define RME96_WCR_BM        (1 << 6)
102 #define RME96_WCR_BM_2      (1 << 7)
103 #define RME96_WCR_ADAT      (1 << 8)
104 #define RME96_WCR_FREQ_0    (1 << 9)
105 #define RME96_WCR_FREQ_1    (1 << 10)
106 #define RME96_WCR_DS        (1 << 11)
107 #define RME96_WCR_PRO       (1 << 12)
108 #define RME96_WCR_EMP       (1 << 13)
109 #define RME96_WCR_SEL       (1 << 14)
110 #define RME96_WCR_MASTER    (1 << 15)
111 #define RME96_WCR_PD        (1 << 16)
112 #define RME96_WCR_INP_0     (1 << 17)
113 #define RME96_WCR_INP_1     (1 << 18)
114 #define RME96_WCR_THRU_0    (1 << 19)
115 #define RME96_WCR_THRU_1    (1 << 20)
116 #define RME96_WCR_THRU_2    (1 << 21)
117 #define RME96_WCR_THRU_3    (1 << 22)
118 #define RME96_WCR_THRU_4    (1 << 23)
119 #define RME96_WCR_THRU_5    (1 << 24)
120 #define RME96_WCR_THRU_6    (1 << 25)
121 #define RME96_WCR_THRU_7    (1 << 26)
122 #define RME96_WCR_DOLBY     (1 << 27)
123 #define RME96_WCR_MONITOR_0 (1 << 28)
124 #define RME96_WCR_MONITOR_1 (1 << 29)
125 #define RME96_WCR_ISEL      (1 << 30)
126 #define RME96_WCR_IDIS      (1 << 31)
127 
128 #define RME96_WCR_BITPOS_GAIN_0 2
129 #define RME96_WCR_BITPOS_GAIN_1 3
130 #define RME96_WCR_BITPOS_FREQ_0 9
131 #define RME96_WCR_BITPOS_FREQ_1 10
132 #define RME96_WCR_BITPOS_INP_0 17
133 #define RME96_WCR_BITPOS_INP_1 18
134 #define RME96_WCR_BITPOS_MONITOR_0 28
135 #define RME96_WCR_BITPOS_MONITOR_1 29
136 
137 /* Read control register bits */
138 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
139 #define RME96_RCR_IRQ_2     (1 << 16)
140 #define RME96_RCR_T_OUT     (1 << 17)
141 #define RME96_RCR_DEV_ID_0  (1 << 21)
142 #define RME96_RCR_DEV_ID_1  (1 << 22)
143 #define RME96_RCR_LOCK      (1 << 23)
144 #define RME96_RCR_VERF      (1 << 26)
145 #define RME96_RCR_F0        (1 << 27)
146 #define RME96_RCR_F1        (1 << 28)
147 #define RME96_RCR_F2        (1 << 29)
148 #define RME96_RCR_AUTOSYNC  (1 << 30)
149 #define RME96_RCR_IRQ       (1 << 31)
150 
151 #define RME96_RCR_BITPOS_F0 27
152 #define RME96_RCR_BITPOS_F1 28
153 #define RME96_RCR_BITPOS_F2 29
154 
155 /* Additonal register bits */
156 #define RME96_AR_WSEL       (1 << 0)
157 #define RME96_AR_ANALOG     (1 << 1)
158 #define RME96_AR_FREQPAD_0  (1 << 2)
159 #define RME96_AR_FREQPAD_1  (1 << 3)
160 #define RME96_AR_FREQPAD_2  (1 << 4)
161 #define RME96_AR_PD2        (1 << 5)
162 #define RME96_AR_DAC_EN     (1 << 6)
163 #define RME96_AR_CLATCH     (1 << 7)
164 #define RME96_AR_CCLK       (1 << 8)
165 #define RME96_AR_CDATA      (1 << 9)
166 
167 #define RME96_AR_BITPOS_F0 2
168 #define RME96_AR_BITPOS_F1 3
169 #define RME96_AR_BITPOS_F2 4
170 
171 /* Monitor tracks */
172 #define RME96_MONITOR_TRACKS_1_2 0
173 #define RME96_MONITOR_TRACKS_3_4 1
174 #define RME96_MONITOR_TRACKS_5_6 2
175 #define RME96_MONITOR_TRACKS_7_8 3
176 
177 /* Attenuation */
178 #define RME96_ATTENUATION_0 0
179 #define RME96_ATTENUATION_6 1
180 #define RME96_ATTENUATION_12 2
181 #define RME96_ATTENUATION_18 3
182 
183 /* Input types */
184 #define RME96_INPUT_OPTICAL 0
185 #define RME96_INPUT_COAXIAL 1
186 #define RME96_INPUT_INTERNAL 2
187 #define RME96_INPUT_XLR 3
188 #define RME96_INPUT_ANALOG 4
189 
190 /* Clock modes */
191 #define RME96_CLOCKMODE_SLAVE 0
192 #define RME96_CLOCKMODE_MASTER 1
193 #define RME96_CLOCKMODE_WORDCLOCK 2
194 
195 /* Block sizes in bytes */
196 #define RME96_SMALL_BLOCK_SIZE 2048
197 #define RME96_LARGE_BLOCK_SIZE 8192
198 
199 /* Volume control */
200 #define RME96_AD1852_VOL_BITS 14
201 #define RME96_AD1855_VOL_BITS 10
202 
203 
204 struct rme96 {
205 	spinlock_t    lock;
206 	int irq;
207 	unsigned long port;
208 	void __iomem *iobase;
209 
210 	u32 wcreg;    /* cached write control register value */
211 	u32 wcreg_spdif;		/* S/PDIF setup */
212 	u32 wcreg_spdif_stream;		/* S/PDIF setup (temporary) */
213 	u32 rcreg;    /* cached read control register value */
214 	u32 areg;     /* cached additional register value */
215 	u16 vol[2]; /* cached volume of analog output */
216 
217 	u8 rev; /* card revision number */
218 
219 	struct snd_pcm_substream *playback_substream;
220 	struct snd_pcm_substream *capture_substream;
221 
222 	int playback_frlog; /* log2 of framesize */
223 	int capture_frlog;
224 
225         size_t playback_periodsize; /* in bytes, zero if not used */
226 	size_t capture_periodsize; /* in bytes, zero if not used */
227 
228 	struct snd_card *card;
229 	struct snd_pcm *spdif_pcm;
230 	struct snd_pcm *adat_pcm;
231 	struct pci_dev     *pci;
232 	struct snd_kcontrol   *spdif_ctl;
233 };
234 
235 static struct pci_device_id snd_rme96_ids[] = {
236 	{ PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96,
237 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
238 	{ PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8,
239 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
240 	{ PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO,
241 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
242 	{ PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST,
243 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
244 	{ 0, }
245 };
246 
247 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
248 
249 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
250 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
251 #define	RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
252 #define	RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
253 				     (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
254 #define	RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
255 #define	RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
256 			          ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
257 #define	RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
258 
259 static int
260 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
261 
262 static int
263 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
264 
265 static int
266 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
267 			   int cmd);
268 
269 static int
270 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
271 			  int cmd);
272 
273 static snd_pcm_uframes_t
274 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
275 
276 static snd_pcm_uframes_t
277 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
278 
279 static void __devinit
280 snd_rme96_proc_init(struct rme96 *rme96);
281 
282 static int
283 snd_rme96_create_switches(struct snd_card *card,
284 			  struct rme96 *rme96);
285 
286 static int
287 snd_rme96_getinputtype(struct rme96 *rme96);
288 
289 static inline unsigned int
290 snd_rme96_playback_ptr(struct rme96 *rme96)
291 {
292 	return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
293 		& RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
294 }
295 
296 static inline unsigned int
297 snd_rme96_capture_ptr(struct rme96 *rme96)
298 {
299 	return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
300 		& RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
301 }
302 
303 static int
304 snd_rme96_ratecode(int rate)
305 {
306     switch (rate) {
307     case 32000: return SNDRV_PCM_RATE_32000;
308     case 44100: return SNDRV_PCM_RATE_44100;
309     case 48000: return SNDRV_PCM_RATE_48000;
310     case 64000: return SNDRV_PCM_RATE_64000;
311     case 88200: return SNDRV_PCM_RATE_88200;
312     case 96000: return SNDRV_PCM_RATE_96000;
313     }
314     return 0;
315 }
316 
317 static int
318 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
319 			   int channel, /* not used (interleaved data) */
320 			   snd_pcm_uframes_t pos,
321 			   snd_pcm_uframes_t count)
322 {
323 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
324 	count <<= rme96->playback_frlog;
325 	pos <<= rme96->playback_frlog;
326 	memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
327 		  0, count);
328 	return 0;
329 }
330 
331 static int
332 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
333 			int channel, /* not used (interleaved data) */
334 			snd_pcm_uframes_t pos,
335 			void __user *src,
336 			snd_pcm_uframes_t count)
337 {
338 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
339 	count <<= rme96->playback_frlog;
340 	pos <<= rme96->playback_frlog;
341 	copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
342 			    count);
343 	return 0;
344 }
345 
346 static int
347 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
348 		       int channel, /* not used (interleaved data) */
349 		       snd_pcm_uframes_t pos,
350 		       void __user *dst,
351 		       snd_pcm_uframes_t count)
352 {
353 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
354 	count <<= rme96->capture_frlog;
355 	pos <<= rme96->capture_frlog;
356 	copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
357 			    count);
358         return 0;
359 }
360 
361 /*
362  * Digital output capabilities (S/PDIF)
363  */
364 static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
365 {
366 	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
367 			      SNDRV_PCM_INFO_MMAP_VALID |
368 			      SNDRV_PCM_INFO_INTERLEAVED |
369 			      SNDRV_PCM_INFO_PAUSE),
370 	.formats =	     (SNDRV_PCM_FMTBIT_S16_LE |
371 			      SNDRV_PCM_FMTBIT_S32_LE),
372 	.rates =	     (SNDRV_PCM_RATE_32000 |
373 			      SNDRV_PCM_RATE_44100 |
374 			      SNDRV_PCM_RATE_48000 |
375 			      SNDRV_PCM_RATE_64000 |
376 			      SNDRV_PCM_RATE_88200 |
377 			      SNDRV_PCM_RATE_96000),
378 	.rate_min =	     32000,
379 	.rate_max =	     96000,
380 	.channels_min =	     2,
381 	.channels_max =	     2,
382 	.buffer_bytes_max =  RME96_BUFFER_SIZE,
383 	.period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
384 	.period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
385 	.periods_min =	     RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
386 	.periods_max =	     RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
387 	.fifo_size =	     0,
388 };
389 
390 /*
391  * Digital input capabilities (S/PDIF)
392  */
393 static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
394 {
395 	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
396 			      SNDRV_PCM_INFO_MMAP_VALID |
397 			      SNDRV_PCM_INFO_INTERLEAVED |
398 			      SNDRV_PCM_INFO_PAUSE),
399 	.formats =	     (SNDRV_PCM_FMTBIT_S16_LE |
400 			      SNDRV_PCM_FMTBIT_S32_LE),
401 	.rates =	     (SNDRV_PCM_RATE_32000 |
402 			      SNDRV_PCM_RATE_44100 |
403 			      SNDRV_PCM_RATE_48000 |
404 			      SNDRV_PCM_RATE_64000 |
405 			      SNDRV_PCM_RATE_88200 |
406 			      SNDRV_PCM_RATE_96000),
407 	.rate_min =	     32000,
408 	.rate_max =	     96000,
409 	.channels_min =	     2,
410 	.channels_max =	     2,
411 	.buffer_bytes_max =  RME96_BUFFER_SIZE,
412 	.period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
413 	.period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
414 	.periods_min =	     RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
415 	.periods_max =	     RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
416 	.fifo_size =	     0,
417 };
418 
419 /*
420  * Digital output capabilities (ADAT)
421  */
422 static struct snd_pcm_hardware snd_rme96_playback_adat_info =
423 {
424 	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
425 			      SNDRV_PCM_INFO_MMAP_VALID |
426 			      SNDRV_PCM_INFO_INTERLEAVED |
427 			      SNDRV_PCM_INFO_PAUSE),
428 	.formats =	     (SNDRV_PCM_FMTBIT_S16_LE |
429 			      SNDRV_PCM_FMTBIT_S32_LE),
430 	.rates =             (SNDRV_PCM_RATE_44100 |
431 			      SNDRV_PCM_RATE_48000),
432 	.rate_min =          44100,
433 	.rate_max =          48000,
434 	.channels_min =      8,
435 	.channels_max =	     8,
436 	.buffer_bytes_max =  RME96_BUFFER_SIZE,
437 	.period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
438 	.period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
439 	.periods_min =	     RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
440 	.periods_max =	     RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
441 	.fifo_size =	     0,
442 };
443 
444 /*
445  * Digital input capabilities (ADAT)
446  */
447 static struct snd_pcm_hardware snd_rme96_capture_adat_info =
448 {
449 	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
450 			      SNDRV_PCM_INFO_MMAP_VALID |
451 			      SNDRV_PCM_INFO_INTERLEAVED |
452 			      SNDRV_PCM_INFO_PAUSE),
453 	.formats =	     (SNDRV_PCM_FMTBIT_S16_LE |
454 			      SNDRV_PCM_FMTBIT_S32_LE),
455 	.rates =	     (SNDRV_PCM_RATE_44100 |
456 			      SNDRV_PCM_RATE_48000),
457 	.rate_min =          44100,
458 	.rate_max =          48000,
459 	.channels_min =      8,
460 	.channels_max =	     8,
461 	.buffer_bytes_max =  RME96_BUFFER_SIZE,
462 	.period_bytes_min =  RME96_SMALL_BLOCK_SIZE,
463 	.period_bytes_max =  RME96_LARGE_BLOCK_SIZE,
464 	.periods_min =	     RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
465 	.periods_max =	     RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
466 	.fifo_size =         0,
467 };
468 
469 /*
470  * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
471  * of the AD1852 or AD1852 D/A converter on the board.  CDATA must be set up
472  * on the falling edge of CCLK and be stable on the rising edge.  The rising
473  * edge of CLATCH after the last data bit clocks in the whole data word.
474  * A fast processor could probably drive the SPI interface faster than the
475  * DAC can handle (3MHz for the 1855, unknown for the 1852).  The udelay(1)
476  * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
477  *
478  * NOTE: increased delay from 1 to 10, since there where problems setting
479  * the volume.
480  */
481 static void
482 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
483 {
484 	int i;
485 
486 	for (i = 0; i < 16; i++) {
487 		if (val & 0x8000) {
488 			rme96->areg |= RME96_AR_CDATA;
489 		} else {
490 			rme96->areg &= ~RME96_AR_CDATA;
491 		}
492 		rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
493 		writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
494 		udelay(10);
495 		rme96->areg |= RME96_AR_CCLK;
496 		writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
497 		udelay(10);
498 		val <<= 1;
499 	}
500 	rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
501 	rme96->areg |= RME96_AR_CLATCH;
502 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
503 	udelay(10);
504 	rme96->areg &= ~RME96_AR_CLATCH;
505 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
506 }
507 
508 static void
509 snd_rme96_apply_dac_volume(struct rme96 *rme96)
510 {
511 	if (RME96_DAC_IS_1852(rme96)) {
512 		snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
513 		snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
514 	} else if (RME96_DAC_IS_1855(rme96)) {
515 		snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
516 		snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
517 	}
518 }
519 
520 static void
521 snd_rme96_reset_dac(struct rme96 *rme96)
522 {
523 	writel(rme96->wcreg | RME96_WCR_PD,
524 	       rme96->iobase + RME96_IO_CONTROL_REGISTER);
525 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
526 }
527 
528 static int
529 snd_rme96_getmontracks(struct rme96 *rme96)
530 {
531 	return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
532 		(((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
533 }
534 
535 static int
536 snd_rme96_setmontracks(struct rme96 *rme96,
537 		       int montracks)
538 {
539 	if (montracks & 1) {
540 		rme96->wcreg |= RME96_WCR_MONITOR_0;
541 	} else {
542 		rme96->wcreg &= ~RME96_WCR_MONITOR_0;
543 	}
544 	if (montracks & 2) {
545 		rme96->wcreg |= RME96_WCR_MONITOR_1;
546 	} else {
547 		rme96->wcreg &= ~RME96_WCR_MONITOR_1;
548 	}
549 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
550 	return 0;
551 }
552 
553 static int
554 snd_rme96_getattenuation(struct rme96 *rme96)
555 {
556 	return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
557 		(((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
558 }
559 
560 static int
561 snd_rme96_setattenuation(struct rme96 *rme96,
562 			 int attenuation)
563 {
564 	switch (attenuation) {
565 	case 0:
566 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
567 			~RME96_WCR_GAIN_1;
568 		break;
569 	case 1:
570 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
571 			~RME96_WCR_GAIN_1;
572 		break;
573 	case 2:
574 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
575 			RME96_WCR_GAIN_1;
576 		break;
577 	case 3:
578 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
579 			RME96_WCR_GAIN_1;
580 		break;
581 	default:
582 		return -EINVAL;
583 	}
584 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
585 	return 0;
586 }
587 
588 static int
589 snd_rme96_capture_getrate(struct rme96 *rme96,
590 			  int *is_adat)
591 {
592 	int n, rate;
593 
594 	*is_adat = 0;
595 	if (rme96->areg & RME96_AR_ANALOG) {
596 		/* Analog input, overrides S/PDIF setting */
597 		n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
598 			(((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
599 		switch (n) {
600 		case 1:
601 			rate = 32000;
602 			break;
603 		case 2:
604 			rate = 44100;
605 			break;
606 		case 3:
607 			rate = 48000;
608 			break;
609 		default:
610 			return -1;
611 		}
612 		return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
613 	}
614 
615 	rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
616 	if (rme96->rcreg & RME96_RCR_LOCK) {
617 		/* ADAT rate */
618 		*is_adat = 1;
619 		if (rme96->rcreg & RME96_RCR_T_OUT) {
620 			return 48000;
621 		}
622 		return 44100;
623 	}
624 
625 	if (rme96->rcreg & RME96_RCR_VERF) {
626 		return -1;
627 	}
628 
629 	/* S/PDIF rate */
630 	n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
631 		(((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
632 		(((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
633 
634 	switch (n) {
635 	case 0:
636 		if (rme96->rcreg & RME96_RCR_T_OUT) {
637 			return 64000;
638 		}
639 		return -1;
640 	case 3: return 96000;
641 	case 4: return 88200;
642 	case 5: return 48000;
643 	case 6: return 44100;
644 	case 7: return 32000;
645 	default:
646 		break;
647 	}
648 	return -1;
649 }
650 
651 static int
652 snd_rme96_playback_getrate(struct rme96 *rme96)
653 {
654 	int rate, dummy;
655 
656 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&
657             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
658 	    (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
659 	{
660 	        /* slave clock */
661 	        return rate;
662 	}
663 	rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
664 		(((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
665 	switch (rate) {
666 	case 1:
667 		rate = 32000;
668 		break;
669 	case 2:
670 		rate = 44100;
671 		break;
672 	case 3:
673 		rate = 48000;
674 		break;
675 	default:
676 		return -1;
677 	}
678 	return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
679 }
680 
681 static int
682 snd_rme96_playback_setrate(struct rme96 *rme96,
683 			   int rate)
684 {
685 	int ds;
686 
687 	ds = rme96->wcreg & RME96_WCR_DS;
688 	switch (rate) {
689 	case 32000:
690 		rme96->wcreg &= ~RME96_WCR_DS;
691 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
692 			~RME96_WCR_FREQ_1;
693 		break;
694 	case 44100:
695 		rme96->wcreg &= ~RME96_WCR_DS;
696 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
697 			~RME96_WCR_FREQ_0;
698 		break;
699 	case 48000:
700 		rme96->wcreg &= ~RME96_WCR_DS;
701 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
702 			RME96_WCR_FREQ_1;
703 		break;
704 	case 64000:
705 		rme96->wcreg |= RME96_WCR_DS;
706 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
707 			~RME96_WCR_FREQ_1;
708 		break;
709 	case 88200:
710 		rme96->wcreg |= RME96_WCR_DS;
711 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
712 			~RME96_WCR_FREQ_0;
713 		break;
714 	case 96000:
715 		rme96->wcreg |= RME96_WCR_DS;
716 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
717 			RME96_WCR_FREQ_1;
718 		break;
719 	default:
720 		return -EINVAL;
721 	}
722 	if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
723 	    (ds && !(rme96->wcreg & RME96_WCR_DS)))
724 	{
725 		/* change to/from double-speed: reset the DAC (if available) */
726 		snd_rme96_reset_dac(rme96);
727 	} else {
728 		writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
729 	}
730 	return 0;
731 }
732 
733 static int
734 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
735 				 int rate)
736 {
737 	switch (rate) {
738 	case 32000:
739 		rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
740 			       ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
741 		break;
742 	case 44100:
743 		rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
744 			       RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
745 		break;
746 	case 48000:
747 		rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
748 			       RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
749 		break;
750 	case 64000:
751 		if (rme96->rev < 4) {
752 			return -EINVAL;
753 		}
754 		rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
755 			       ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
756 		break;
757 	case 88200:
758 		if (rme96->rev < 4) {
759 			return -EINVAL;
760 		}
761 		rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
762 			       RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
763 		break;
764 	case 96000:
765 		rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
766 			       RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
767 		break;
768 	default:
769 		return -EINVAL;
770 	}
771 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
772 	return 0;
773 }
774 
775 static int
776 snd_rme96_setclockmode(struct rme96 *rme96,
777 		       int mode)
778 {
779 	switch (mode) {
780 	case RME96_CLOCKMODE_SLAVE:
781 	        /* AutoSync */
782 		rme96->wcreg &= ~RME96_WCR_MASTER;
783 		rme96->areg &= ~RME96_AR_WSEL;
784 		break;
785 	case RME96_CLOCKMODE_MASTER:
786 	        /* Internal */
787 		rme96->wcreg |= RME96_WCR_MASTER;
788 		rme96->areg &= ~RME96_AR_WSEL;
789 		break;
790 	case RME96_CLOCKMODE_WORDCLOCK:
791 		/* Word clock is a master mode */
792 		rme96->wcreg |= RME96_WCR_MASTER;
793 		rme96->areg |= RME96_AR_WSEL;
794 		break;
795 	default:
796 		return -EINVAL;
797 	}
798 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
799 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
800 	return 0;
801 }
802 
803 static int
804 snd_rme96_getclockmode(struct rme96 *rme96)
805 {
806 	if (rme96->areg & RME96_AR_WSEL) {
807 		return RME96_CLOCKMODE_WORDCLOCK;
808 	}
809 	return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
810 		RME96_CLOCKMODE_SLAVE;
811 }
812 
813 static int
814 snd_rme96_setinputtype(struct rme96 *rme96,
815 		       int type)
816 {
817 	int n;
818 
819 	switch (type) {
820 	case RME96_INPUT_OPTICAL:
821 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
822 			~RME96_WCR_INP_1;
823 		break;
824 	case RME96_INPUT_COAXIAL:
825 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
826 			~RME96_WCR_INP_1;
827 		break;
828 	case RME96_INPUT_INTERNAL:
829 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
830 			RME96_WCR_INP_1;
831 		break;
832 	case RME96_INPUT_XLR:
833 		if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
834 		     rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
835 		    (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
836 		     rme96->rev > 4))
837 		{
838 			/* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
839 			return -EINVAL;
840 		}
841 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
842 			RME96_WCR_INP_1;
843 		break;
844 	case RME96_INPUT_ANALOG:
845 		if (!RME96_HAS_ANALOG_IN(rme96)) {
846 			return -EINVAL;
847 		}
848 		rme96->areg |= RME96_AR_ANALOG;
849 		writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
850 		if (rme96->rev < 4) {
851 			/*
852 			 * Revision less than 004 does not support 64 and
853 			 * 88.2 kHz
854 			 */
855 			if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
856 				snd_rme96_capture_analog_setrate(rme96, 44100);
857 			}
858 			if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
859 				snd_rme96_capture_analog_setrate(rme96, 32000);
860 			}
861 		}
862 		return 0;
863 	default:
864 		return -EINVAL;
865 	}
866 	if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
867 		rme96->areg &= ~RME96_AR_ANALOG;
868 		writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
869 	}
870 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
871 	return 0;
872 }
873 
874 static int
875 snd_rme96_getinputtype(struct rme96 *rme96)
876 {
877 	if (rme96->areg & RME96_AR_ANALOG) {
878 		return RME96_INPUT_ANALOG;
879 	}
880 	return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
881 		(((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
882 }
883 
884 static void
885 snd_rme96_setframelog(struct rme96 *rme96,
886 		      int n_channels,
887 		      int is_playback)
888 {
889 	int frlog;
890 
891 	if (n_channels == 2) {
892 		frlog = 1;
893 	} else {
894 		/* assume 8 channels */
895 		frlog = 3;
896 	}
897 	if (is_playback) {
898 		frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
899 		rme96->playback_frlog = frlog;
900 	} else {
901 		frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
902 		rme96->capture_frlog = frlog;
903 	}
904 }
905 
906 static int
907 snd_rme96_playback_setformat(struct rme96 *rme96,
908 			     int format)
909 {
910 	switch (format) {
911 	case SNDRV_PCM_FORMAT_S16_LE:
912 		rme96->wcreg &= ~RME96_WCR_MODE24;
913 		break;
914 	case SNDRV_PCM_FORMAT_S32_LE:
915 		rme96->wcreg |= RME96_WCR_MODE24;
916 		break;
917 	default:
918 		return -EINVAL;
919 	}
920 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
921 	return 0;
922 }
923 
924 static int
925 snd_rme96_capture_setformat(struct rme96 *rme96,
926 			    int format)
927 {
928 	switch (format) {
929 	case SNDRV_PCM_FORMAT_S16_LE:
930 		rme96->wcreg &= ~RME96_WCR_MODE24_2;
931 		break;
932 	case SNDRV_PCM_FORMAT_S32_LE:
933 		rme96->wcreg |= RME96_WCR_MODE24_2;
934 		break;
935 	default:
936 		return -EINVAL;
937 	}
938 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
939 	return 0;
940 }
941 
942 static void
943 snd_rme96_set_period_properties(struct rme96 *rme96,
944 				size_t period_bytes)
945 {
946 	switch (period_bytes) {
947 	case RME96_LARGE_BLOCK_SIZE:
948 		rme96->wcreg &= ~RME96_WCR_ISEL;
949 		break;
950 	case RME96_SMALL_BLOCK_SIZE:
951 		rme96->wcreg |= RME96_WCR_ISEL;
952 		break;
953 	default:
954 		snd_BUG();
955 		break;
956 	}
957 	rme96->wcreg &= ~RME96_WCR_IDIS;
958 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
959 }
960 
961 static int
962 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
963 			     struct snd_pcm_hw_params *params)
964 {
965 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
966 	struct snd_pcm_runtime *runtime = substream->runtime;
967 	int err, rate, dummy;
968 
969 	runtime->dma_area = (void __force *)(rme96->iobase +
970 					     RME96_IO_PLAY_BUFFER);
971 	runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
972 	runtime->dma_bytes = RME96_BUFFER_SIZE;
973 
974 	spin_lock_irq(&rme96->lock);
975 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&
976             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
977 	    (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
978 	{
979                 /* slave clock */
980                 if ((int)params_rate(params) != rate) {
981 			spin_unlock_irq(&rme96->lock);
982 			return -EIO;
983                 }
984 	} else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
985 		spin_unlock_irq(&rme96->lock);
986 		return err;
987 	}
988 	if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
989 		spin_unlock_irq(&rme96->lock);
990 		return err;
991 	}
992 	snd_rme96_setframelog(rme96, params_channels(params), 1);
993 	if (rme96->capture_periodsize != 0) {
994 		if (params_period_size(params) << rme96->playback_frlog !=
995 		    rme96->capture_periodsize)
996 		{
997 			spin_unlock_irq(&rme96->lock);
998 			return -EBUSY;
999 		}
1000 	}
1001 	rme96->playback_periodsize =
1002 		params_period_size(params) << rme96->playback_frlog;
1003 	snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1004 	/* S/PDIF setup */
1005 	if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1006 		rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1007 		writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1008 	}
1009 	spin_unlock_irq(&rme96->lock);
1010 
1011 	return 0;
1012 }
1013 
1014 static int
1015 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1016 			    struct snd_pcm_hw_params *params)
1017 {
1018 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1019 	struct snd_pcm_runtime *runtime = substream->runtime;
1020 	int err, isadat, rate;
1021 
1022 	runtime->dma_area = (void __force *)(rme96->iobase +
1023 					     RME96_IO_REC_BUFFER);
1024 	runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1025 	runtime->dma_bytes = RME96_BUFFER_SIZE;
1026 
1027 	spin_lock_irq(&rme96->lock);
1028 	if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1029 		spin_unlock_irq(&rme96->lock);
1030 		return err;
1031 	}
1032 	if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1033 		if ((err = snd_rme96_capture_analog_setrate(rme96,
1034 							    params_rate(params))) < 0)
1035 		{
1036 			spin_unlock_irq(&rme96->lock);
1037 			return err;
1038 		}
1039 	} else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1040                 if ((int)params_rate(params) != rate) {
1041 			spin_unlock_irq(&rme96->lock);
1042 			return -EIO;
1043                 }
1044                 if ((isadat && runtime->hw.channels_min == 2) ||
1045                     (!isadat && runtime->hw.channels_min == 8))
1046                 {
1047 			spin_unlock_irq(&rme96->lock);
1048 			return -EIO;
1049                 }
1050         }
1051 	snd_rme96_setframelog(rme96, params_channels(params), 0);
1052 	if (rme96->playback_periodsize != 0) {
1053 		if (params_period_size(params) << rme96->capture_frlog !=
1054 		    rme96->playback_periodsize)
1055 		{
1056 			spin_unlock_irq(&rme96->lock);
1057 			return -EBUSY;
1058 		}
1059 	}
1060 	rme96->capture_periodsize =
1061 		params_period_size(params) << rme96->capture_frlog;
1062 	snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1063 	spin_unlock_irq(&rme96->lock);
1064 
1065 	return 0;
1066 }
1067 
1068 static void
1069 snd_rme96_playback_start(struct rme96 *rme96,
1070 			 int from_pause)
1071 {
1072 	if (!from_pause) {
1073 		writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1074 	}
1075 
1076 	rme96->wcreg |= RME96_WCR_START;
1077 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1078 }
1079 
1080 static void
1081 snd_rme96_capture_start(struct rme96 *rme96,
1082 			int from_pause)
1083 {
1084 	if (!from_pause) {
1085 		writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1086 	}
1087 
1088 	rme96->wcreg |= RME96_WCR_START_2;
1089 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1090 }
1091 
1092 static void
1093 snd_rme96_playback_stop(struct rme96 *rme96)
1094 {
1095 	/*
1096 	 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1097 	 * the hardware will not stop generating interrupts
1098 	 */
1099 	rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1100 	if (rme96->rcreg & RME96_RCR_IRQ) {
1101 		writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1102 	}
1103 	rme96->wcreg &= ~RME96_WCR_START;
1104 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1105 }
1106 
1107 static void
1108 snd_rme96_capture_stop(struct rme96 *rme96)
1109 {
1110 	rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1111 	if (rme96->rcreg & RME96_RCR_IRQ_2) {
1112 		writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1113 	}
1114 	rme96->wcreg &= ~RME96_WCR_START_2;
1115 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1116 }
1117 
1118 static irqreturn_t
1119 snd_rme96_interrupt(int irq,
1120 		    void *dev_id)
1121 {
1122 	struct rme96 *rme96 = (struct rme96 *)dev_id;
1123 
1124 	rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1125 	/* fastpath out, to ease interrupt sharing */
1126 	if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1127 	      (rme96->rcreg & RME96_RCR_IRQ_2)))
1128 	{
1129 		return IRQ_NONE;
1130 	}
1131 
1132 	if (rme96->rcreg & RME96_RCR_IRQ) {
1133 		/* playback */
1134                 snd_pcm_period_elapsed(rme96->playback_substream);
1135 		writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1136 	}
1137 	if (rme96->rcreg & RME96_RCR_IRQ_2) {
1138 		/* capture */
1139 		snd_pcm_period_elapsed(rme96->capture_substream);
1140 		writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1141 	}
1142 	return IRQ_HANDLED;
1143 }
1144 
1145 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1146 
1147 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1148 	.count = ARRAY_SIZE(period_bytes),
1149 	.list = period_bytes,
1150 	.mask = 0
1151 };
1152 
1153 static void
1154 rme96_set_buffer_size_constraint(struct rme96 *rme96,
1155 				 struct snd_pcm_runtime *runtime)
1156 {
1157 	unsigned int size;
1158 
1159 	snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1160 				     RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1161 	if ((size = rme96->playback_periodsize) != 0 ||
1162 	    (size = rme96->capture_periodsize) != 0)
1163 		snd_pcm_hw_constraint_minmax(runtime,
1164 					     SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1165 					     size, size);
1166 	else
1167 		snd_pcm_hw_constraint_list(runtime, 0,
1168 					   SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1169 					   &hw_constraints_period_bytes);
1170 }
1171 
1172 static int
1173 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1174 {
1175         int rate, dummy;
1176 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1177 	struct snd_pcm_runtime *runtime = substream->runtime;
1178 
1179 	snd_pcm_set_sync(substream);
1180 
1181 	spin_lock_irq(&rme96->lock);
1182         if (rme96->playback_substream != NULL) {
1183 		spin_unlock_irq(&rme96->lock);
1184                 return -EBUSY;
1185         }
1186 	rme96->wcreg &= ~RME96_WCR_ADAT;
1187 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1188 	rme96->playback_substream = substream;
1189 	spin_unlock_irq(&rme96->lock);
1190 
1191 	runtime->hw = snd_rme96_playback_spdif_info;
1192 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1193             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1194 	    (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1195 	{
1196                 /* slave clock */
1197                 runtime->hw.rates = snd_rme96_ratecode(rate);
1198                 runtime->hw.rate_min = rate;
1199                 runtime->hw.rate_max = rate;
1200 	}
1201 	rme96_set_buffer_size_constraint(rme96, runtime);
1202 
1203 	rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1204 	rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1205 	snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1206 		       SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1207 	return 0;
1208 }
1209 
1210 static int
1211 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1212 {
1213         int isadat, rate;
1214 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1215 	struct snd_pcm_runtime *runtime = substream->runtime;
1216 
1217 	snd_pcm_set_sync(substream);
1218 
1219 	runtime->hw = snd_rme96_capture_spdif_info;
1220         if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1221             (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1222         {
1223                 if (isadat) {
1224                         return -EIO;
1225                 }
1226                 runtime->hw.rates = snd_rme96_ratecode(rate);
1227                 runtime->hw.rate_min = rate;
1228                 runtime->hw.rate_max = rate;
1229         }
1230 
1231 	spin_lock_irq(&rme96->lock);
1232         if (rme96->capture_substream != NULL) {
1233 		spin_unlock_irq(&rme96->lock);
1234                 return -EBUSY;
1235         }
1236 	rme96->capture_substream = substream;
1237 	spin_unlock_irq(&rme96->lock);
1238 
1239 	rme96_set_buffer_size_constraint(rme96, runtime);
1240 	return 0;
1241 }
1242 
1243 static int
1244 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1245 {
1246         int rate, dummy;
1247 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1248 	struct snd_pcm_runtime *runtime = substream->runtime;
1249 
1250 	snd_pcm_set_sync(substream);
1251 
1252 	spin_lock_irq(&rme96->lock);
1253         if (rme96->playback_substream != NULL) {
1254 		spin_unlock_irq(&rme96->lock);
1255                 return -EBUSY;
1256         }
1257 	rme96->wcreg |= RME96_WCR_ADAT;
1258 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1259 	rme96->playback_substream = substream;
1260 	spin_unlock_irq(&rme96->lock);
1261 
1262 	runtime->hw = snd_rme96_playback_adat_info;
1263 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1264             snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1265 	    (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1266 	{
1267                 /* slave clock */
1268                 runtime->hw.rates = snd_rme96_ratecode(rate);
1269                 runtime->hw.rate_min = rate;
1270                 runtime->hw.rate_max = rate;
1271 	}
1272 	rme96_set_buffer_size_constraint(rme96, runtime);
1273 	return 0;
1274 }
1275 
1276 static int
1277 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1278 {
1279         int isadat, rate;
1280 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1281 	struct snd_pcm_runtime *runtime = substream->runtime;
1282 
1283 	snd_pcm_set_sync(substream);
1284 
1285 	runtime->hw = snd_rme96_capture_adat_info;
1286         if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1287                 /* makes no sense to use analog input. Note that analog
1288                    expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1289                 return -EIO;
1290         }
1291         if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1292                 if (!isadat) {
1293                         return -EIO;
1294                 }
1295                 runtime->hw.rates = snd_rme96_ratecode(rate);
1296                 runtime->hw.rate_min = rate;
1297                 runtime->hw.rate_max = rate;
1298         }
1299 
1300 	spin_lock_irq(&rme96->lock);
1301         if (rme96->capture_substream != NULL) {
1302 		spin_unlock_irq(&rme96->lock);
1303                 return -EBUSY;
1304         }
1305 	rme96->capture_substream = substream;
1306 	spin_unlock_irq(&rme96->lock);
1307 
1308 	rme96_set_buffer_size_constraint(rme96, runtime);
1309 	return 0;
1310 }
1311 
1312 static int
1313 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1314 {
1315 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1316 	int spdif = 0;
1317 
1318 	spin_lock_irq(&rme96->lock);
1319 	if (RME96_ISPLAYING(rme96)) {
1320 		snd_rme96_playback_stop(rme96);
1321 	}
1322 	rme96->playback_substream = NULL;
1323 	rme96->playback_periodsize = 0;
1324 	spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1325 	spin_unlock_irq(&rme96->lock);
1326 	if (spdif) {
1327 		rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1328 		snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1329 			       SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1330 	}
1331 	return 0;
1332 }
1333 
1334 static int
1335 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1336 {
1337 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1338 
1339 	spin_lock_irq(&rme96->lock);
1340 	if (RME96_ISRECORDING(rme96)) {
1341 		snd_rme96_capture_stop(rme96);
1342 	}
1343 	rme96->capture_substream = NULL;
1344 	rme96->capture_periodsize = 0;
1345 	spin_unlock_irq(&rme96->lock);
1346 	return 0;
1347 }
1348 
1349 static int
1350 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1351 {
1352 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1353 
1354 	spin_lock_irq(&rme96->lock);
1355 	if (RME96_ISPLAYING(rme96)) {
1356 		snd_rme96_playback_stop(rme96);
1357 	}
1358 	writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1359 	spin_unlock_irq(&rme96->lock);
1360 	return 0;
1361 }
1362 
1363 static int
1364 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1365 {
1366 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1367 
1368 	spin_lock_irq(&rme96->lock);
1369 	if (RME96_ISRECORDING(rme96)) {
1370 		snd_rme96_capture_stop(rme96);
1371 	}
1372 	writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1373 	spin_unlock_irq(&rme96->lock);
1374 	return 0;
1375 }
1376 
1377 static int
1378 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1379 			   int cmd)
1380 {
1381 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1382 
1383 	switch (cmd) {
1384 	case SNDRV_PCM_TRIGGER_START:
1385 		if (!RME96_ISPLAYING(rme96)) {
1386 			if (substream != rme96->playback_substream) {
1387 				return -EBUSY;
1388 			}
1389 			snd_rme96_playback_start(rme96, 0);
1390 		}
1391 		break;
1392 
1393 	case SNDRV_PCM_TRIGGER_STOP:
1394 		if (RME96_ISPLAYING(rme96)) {
1395 			if (substream != rme96->playback_substream) {
1396 				return -EBUSY;
1397 			}
1398 			snd_rme96_playback_stop(rme96);
1399 		}
1400 		break;
1401 
1402 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1403 		if (RME96_ISPLAYING(rme96)) {
1404 			snd_rme96_playback_stop(rme96);
1405 		}
1406 		break;
1407 
1408 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1409 		if (!RME96_ISPLAYING(rme96)) {
1410 			snd_rme96_playback_start(rme96, 1);
1411 		}
1412 		break;
1413 
1414 	default:
1415 		return -EINVAL;
1416 	}
1417 	return 0;
1418 }
1419 
1420 static int
1421 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1422 			  int cmd)
1423 {
1424 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1425 
1426 	switch (cmd) {
1427 	case SNDRV_PCM_TRIGGER_START:
1428 		if (!RME96_ISRECORDING(rme96)) {
1429 			if (substream != rme96->capture_substream) {
1430 				return -EBUSY;
1431 			}
1432 			snd_rme96_capture_start(rme96, 0);
1433 		}
1434 		break;
1435 
1436 	case SNDRV_PCM_TRIGGER_STOP:
1437 		if (RME96_ISRECORDING(rme96)) {
1438 			if (substream != rme96->capture_substream) {
1439 				return -EBUSY;
1440 			}
1441 			snd_rme96_capture_stop(rme96);
1442 		}
1443 		break;
1444 
1445 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1446 		if (RME96_ISRECORDING(rme96)) {
1447 			snd_rme96_capture_stop(rme96);
1448 		}
1449 		break;
1450 
1451 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1452 		if (!RME96_ISRECORDING(rme96)) {
1453 			snd_rme96_capture_start(rme96, 1);
1454 		}
1455 		break;
1456 
1457 	default:
1458 		return -EINVAL;
1459 	}
1460 
1461 	return 0;
1462 }
1463 
1464 static snd_pcm_uframes_t
1465 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1466 {
1467 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1468 	return snd_rme96_playback_ptr(rme96);
1469 }
1470 
1471 static snd_pcm_uframes_t
1472 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1473 {
1474 	struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1475 	return snd_rme96_capture_ptr(rme96);
1476 }
1477 
1478 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1479 	.open =		snd_rme96_playback_spdif_open,
1480 	.close =	snd_rme96_playback_close,
1481 	.ioctl =	snd_pcm_lib_ioctl,
1482 	.hw_params =	snd_rme96_playback_hw_params,
1483 	.prepare =	snd_rme96_playback_prepare,
1484 	.trigger =	snd_rme96_playback_trigger,
1485 	.pointer =	snd_rme96_playback_pointer,
1486 	.copy =		snd_rme96_playback_copy,
1487 	.silence =	snd_rme96_playback_silence,
1488 	.mmap =		snd_pcm_lib_mmap_iomem,
1489 };
1490 
1491 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1492 	.open =		snd_rme96_capture_spdif_open,
1493 	.close =	snd_rme96_capture_close,
1494 	.ioctl =	snd_pcm_lib_ioctl,
1495 	.hw_params =	snd_rme96_capture_hw_params,
1496 	.prepare =	snd_rme96_capture_prepare,
1497 	.trigger =	snd_rme96_capture_trigger,
1498 	.pointer =	snd_rme96_capture_pointer,
1499 	.copy =		snd_rme96_capture_copy,
1500 	.mmap =		snd_pcm_lib_mmap_iomem,
1501 };
1502 
1503 static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1504 	.open =		snd_rme96_playback_adat_open,
1505 	.close =	snd_rme96_playback_close,
1506 	.ioctl =	snd_pcm_lib_ioctl,
1507 	.hw_params =	snd_rme96_playback_hw_params,
1508 	.prepare =	snd_rme96_playback_prepare,
1509 	.trigger =	snd_rme96_playback_trigger,
1510 	.pointer =	snd_rme96_playback_pointer,
1511 	.copy =		snd_rme96_playback_copy,
1512 	.silence =	snd_rme96_playback_silence,
1513 	.mmap =		snd_pcm_lib_mmap_iomem,
1514 };
1515 
1516 static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1517 	.open =		snd_rme96_capture_adat_open,
1518 	.close =	snd_rme96_capture_close,
1519 	.ioctl =	snd_pcm_lib_ioctl,
1520 	.hw_params =	snd_rme96_capture_hw_params,
1521 	.prepare =	snd_rme96_capture_prepare,
1522 	.trigger =	snd_rme96_capture_trigger,
1523 	.pointer =	snd_rme96_capture_pointer,
1524 	.copy =		snd_rme96_capture_copy,
1525 	.mmap =		snd_pcm_lib_mmap_iomem,
1526 };
1527 
1528 static void
1529 snd_rme96_free(void *private_data)
1530 {
1531 	struct rme96 *rme96 = (struct rme96 *)private_data;
1532 
1533 	if (rme96 == NULL) {
1534 	        return;
1535 	}
1536 	if (rme96->irq >= 0) {
1537 		snd_rme96_playback_stop(rme96);
1538 		snd_rme96_capture_stop(rme96);
1539 		rme96->areg &= ~RME96_AR_DAC_EN;
1540 		writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1541 		free_irq(rme96->irq, (void *)rme96);
1542 		rme96->irq = -1;
1543 	}
1544 	if (rme96->iobase) {
1545 		iounmap(rme96->iobase);
1546 		rme96->iobase = NULL;
1547 	}
1548 	if (rme96->port) {
1549 		pci_release_regions(rme96->pci);
1550 		rme96->port = 0;
1551 	}
1552 	pci_disable_device(rme96->pci);
1553 }
1554 
1555 static void
1556 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1557 {
1558 	struct rme96 *rme96 = (struct rme96 *) pcm->private_data;
1559 	rme96->spdif_pcm = NULL;
1560 }
1561 
1562 static void
1563 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1564 {
1565 	struct rme96 *rme96 = (struct rme96 *) pcm->private_data;
1566 	rme96->adat_pcm = NULL;
1567 }
1568 
1569 static int __devinit
1570 snd_rme96_create(struct rme96 *rme96)
1571 {
1572 	struct pci_dev *pci = rme96->pci;
1573 	int err;
1574 
1575 	rme96->irq = -1;
1576 	spin_lock_init(&rme96->lock);
1577 
1578 	if ((err = pci_enable_device(pci)) < 0)
1579 		return err;
1580 
1581 	if ((err = pci_request_regions(pci, "RME96")) < 0)
1582 		return err;
1583 	rme96->port = pci_resource_start(rme96->pci, 0);
1584 
1585 	if ((rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) {
1586 		snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1587 		return -ENOMEM;
1588 	}
1589 
1590 	if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
1591 			"RME96", rme96)) {
1592 		snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1593 		return -EBUSY;
1594 	}
1595 	rme96->irq = pci->irq;
1596 
1597 	/* read the card's revision number */
1598 	pci_read_config_byte(pci, 8, &rme96->rev);
1599 
1600 	/* set up ALSA pcm device for S/PDIF */
1601 	if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1602 			       1, 1, &rme96->spdif_pcm)) < 0)
1603 	{
1604 		return err;
1605 	}
1606 	rme96->spdif_pcm->private_data = rme96;
1607 	rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1608 	strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1609 	snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1610 	snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1611 
1612 	rme96->spdif_pcm->info_flags = 0;
1613 
1614 	/* set up ALSA pcm device for ADAT */
1615 	if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1616 		/* ADAT is not available on the base model */
1617 		rme96->adat_pcm = NULL;
1618 	} else {
1619 		if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1620 				       1, 1, &rme96->adat_pcm)) < 0)
1621 		{
1622 			return err;
1623 		}
1624 		rme96->adat_pcm->private_data = rme96;
1625 		rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1626 		strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1627 		snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1628 		snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1629 
1630 		rme96->adat_pcm->info_flags = 0;
1631 	}
1632 
1633 	rme96->playback_periodsize = 0;
1634 	rme96->capture_periodsize = 0;
1635 
1636 	/* make sure playback/capture is stopped, if by some reason active */
1637 	snd_rme96_playback_stop(rme96);
1638 	snd_rme96_capture_stop(rme96);
1639 
1640 	/* set default values in registers */
1641 	rme96->wcreg =
1642 		RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1643 		RME96_WCR_SEL |    /* normal playback */
1644 		RME96_WCR_MASTER | /* set to master clock mode */
1645 		RME96_WCR_INP_0;   /* set coaxial input */
1646 
1647 	rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1648 
1649 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1650 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1651 
1652 	/* reset the ADC */
1653 	writel(rme96->areg | RME96_AR_PD2,
1654 	       rme96->iobase + RME96_IO_ADDITIONAL_REG);
1655 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1656 
1657 	/* reset and enable the DAC (order is important). */
1658 	snd_rme96_reset_dac(rme96);
1659 	rme96->areg |= RME96_AR_DAC_EN;
1660 	writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1661 
1662 	/* reset playback and record buffer pointers */
1663 	writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1664 	writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1665 
1666 	/* reset volume */
1667 	rme96->vol[0] = rme96->vol[1] = 0;
1668 	if (RME96_HAS_ANALOG_OUT(rme96)) {
1669 		snd_rme96_apply_dac_volume(rme96);
1670 	}
1671 
1672 	/* init switch interface */
1673 	if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1674 		return err;
1675 	}
1676 
1677         /* init proc interface */
1678 	snd_rme96_proc_init(rme96);
1679 
1680 	return 0;
1681 }
1682 
1683 /*
1684  * proc interface
1685  */
1686 
1687 static void
1688 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1689 {
1690 	int n;
1691 	struct rme96 *rme96 = (struct rme96 *)entry->private_data;
1692 
1693 	rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1694 
1695 	snd_iprintf(buffer, rme96->card->longname);
1696 	snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1697 
1698 	snd_iprintf(buffer, "\nGeneral settings\n");
1699 	if (rme96->wcreg & RME96_WCR_IDIS) {
1700 		snd_iprintf(buffer, "  period size: N/A (interrupts "
1701 			    "disabled)\n");
1702 	} else if (rme96->wcreg & RME96_WCR_ISEL) {
1703 		snd_iprintf(buffer, "  period size: 2048 bytes\n");
1704 	} else {
1705 		snd_iprintf(buffer, "  period size: 8192 bytes\n");
1706 	}
1707 	snd_iprintf(buffer, "\nInput settings\n");
1708 	switch (snd_rme96_getinputtype(rme96)) {
1709 	case RME96_INPUT_OPTICAL:
1710 		snd_iprintf(buffer, "  input: optical");
1711 		break;
1712 	case RME96_INPUT_COAXIAL:
1713 		snd_iprintf(buffer, "  input: coaxial");
1714 		break;
1715 	case RME96_INPUT_INTERNAL:
1716 		snd_iprintf(buffer, "  input: internal");
1717 		break;
1718 	case RME96_INPUT_XLR:
1719 		snd_iprintf(buffer, "  input: XLR");
1720 		break;
1721 	case RME96_INPUT_ANALOG:
1722 		snd_iprintf(buffer, "  input: analog");
1723 		break;
1724 	}
1725 	if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1726 		snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1727 	} else {
1728 		if (n) {
1729 			snd_iprintf(buffer, " (8 channels)\n");
1730 		} else {
1731 			snd_iprintf(buffer, " (2 channels)\n");
1732 		}
1733 		snd_iprintf(buffer, "  sample rate: %d Hz\n",
1734 			    snd_rme96_capture_getrate(rme96, &n));
1735 	}
1736 	if (rme96->wcreg & RME96_WCR_MODE24_2) {
1737 		snd_iprintf(buffer, "  sample format: 24 bit\n");
1738 	} else {
1739 		snd_iprintf(buffer, "  sample format: 16 bit\n");
1740 	}
1741 
1742 	snd_iprintf(buffer, "\nOutput settings\n");
1743 	if (rme96->wcreg & RME96_WCR_SEL) {
1744 		snd_iprintf(buffer, "  output signal: normal playback\n");
1745 	} else {
1746 		snd_iprintf(buffer, "  output signal: same as input\n");
1747 	}
1748 	snd_iprintf(buffer, "  sample rate: %d Hz\n",
1749 		    snd_rme96_playback_getrate(rme96));
1750 	if (rme96->wcreg & RME96_WCR_MODE24) {
1751 		snd_iprintf(buffer, "  sample format: 24 bit\n");
1752 	} else {
1753 		snd_iprintf(buffer, "  sample format: 16 bit\n");
1754 	}
1755 	if (rme96->areg & RME96_AR_WSEL) {
1756 		snd_iprintf(buffer, "  sample clock source: word clock\n");
1757 	} else if (rme96->wcreg & RME96_WCR_MASTER) {
1758 		snd_iprintf(buffer, "  sample clock source: internal\n");
1759 	} else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1760 		snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to analog input setting)\n");
1761 	} else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1762 		snd_iprintf(buffer, "  sample clock source: autosync (internal anyway due to no valid signal)\n");
1763 	} else {
1764 		snd_iprintf(buffer, "  sample clock source: autosync\n");
1765 	}
1766 	if (rme96->wcreg & RME96_WCR_PRO) {
1767 		snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1768 	} else {
1769 		snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1770 	}
1771 	if (rme96->wcreg & RME96_WCR_EMP) {
1772 		snd_iprintf(buffer, "  emphasis: on\n");
1773 	} else {
1774 		snd_iprintf(buffer, "  emphasis: off\n");
1775 	}
1776 	if (rme96->wcreg & RME96_WCR_DOLBY) {
1777 		snd_iprintf(buffer, "  non-audio (dolby): on\n");
1778 	} else {
1779 		snd_iprintf(buffer, "  non-audio (dolby): off\n");
1780 	}
1781 	if (RME96_HAS_ANALOG_IN(rme96)) {
1782 		snd_iprintf(buffer, "\nAnalog output settings\n");
1783 		switch (snd_rme96_getmontracks(rme96)) {
1784 		case RME96_MONITOR_TRACKS_1_2:
1785 			snd_iprintf(buffer, "  monitored ADAT tracks: 1+2\n");
1786 			break;
1787 		case RME96_MONITOR_TRACKS_3_4:
1788 			snd_iprintf(buffer, "  monitored ADAT tracks: 3+4\n");
1789 			break;
1790 		case RME96_MONITOR_TRACKS_5_6:
1791 			snd_iprintf(buffer, "  monitored ADAT tracks: 5+6\n");
1792 			break;
1793 		case RME96_MONITOR_TRACKS_7_8:
1794 			snd_iprintf(buffer, "  monitored ADAT tracks: 7+8\n");
1795 			break;
1796 		}
1797 		switch (snd_rme96_getattenuation(rme96)) {
1798 		case RME96_ATTENUATION_0:
1799 			snd_iprintf(buffer, "  attenuation: 0 dB\n");
1800 			break;
1801 		case RME96_ATTENUATION_6:
1802 			snd_iprintf(buffer, "  attenuation: -6 dB\n");
1803 			break;
1804 		case RME96_ATTENUATION_12:
1805 			snd_iprintf(buffer, "  attenuation: -12 dB\n");
1806 			break;
1807 		case RME96_ATTENUATION_18:
1808 			snd_iprintf(buffer, "  attenuation: -18 dB\n");
1809 			break;
1810 		}
1811 		snd_iprintf(buffer, "  volume left: %u\n", rme96->vol[0]);
1812 		snd_iprintf(buffer, "  volume right: %u\n", rme96->vol[1]);
1813 	}
1814 }
1815 
1816 static void __devinit
1817 snd_rme96_proc_init(struct rme96 *rme96)
1818 {
1819 	struct snd_info_entry *entry;
1820 
1821 	if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1822 		snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1823 }
1824 
1825 /*
1826  * control interface
1827  */
1828 
1829 static int
1830 snd_rme96_info_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1831 {
1832 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1833 	uinfo->count = 1;
1834 	uinfo->value.integer.min = 0;
1835 	uinfo->value.integer.max = 1;
1836 	return 0;
1837 }
1838 static int
1839 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1840 {
1841 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1842 
1843 	spin_lock_irq(&rme96->lock);
1844 	ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1845 	spin_unlock_irq(&rme96->lock);
1846 	return 0;
1847 }
1848 static int
1849 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1850 {
1851 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1852 	unsigned int val;
1853 	int change;
1854 
1855 	val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1856 	spin_lock_irq(&rme96->lock);
1857 	val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1858 	change = val != rme96->wcreg;
1859 	rme96->wcreg = val;
1860 	writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1861 	spin_unlock_irq(&rme96->lock);
1862 	return change;
1863 }
1864 
1865 static int
1866 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1867 {
1868 	static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1869 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1870 	char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1871 
1872 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1873 	uinfo->count = 1;
1874 	switch (rme96->pci->device) {
1875 	case PCI_DEVICE_ID_RME_DIGI96:
1876 	case PCI_DEVICE_ID_RME_DIGI96_8:
1877 		uinfo->value.enumerated.items = 3;
1878 		break;
1879 	case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1880 		uinfo->value.enumerated.items = 4;
1881 		break;
1882 	case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1883 		if (rme96->rev > 4) {
1884 			/* PST */
1885 			uinfo->value.enumerated.items = 4;
1886 			texts[3] = _texts[4]; /* Analog instead of XLR */
1887 		} else {
1888 			/* PAD */
1889 			uinfo->value.enumerated.items = 5;
1890 		}
1891 		break;
1892 	default:
1893 		snd_BUG();
1894 		break;
1895 	}
1896 	if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1897 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1898 	}
1899 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1900 	return 0;
1901 }
1902 static int
1903 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1904 {
1905 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1906 	unsigned int items = 3;
1907 
1908 	spin_lock_irq(&rme96->lock);
1909 	ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1910 
1911 	switch (rme96->pci->device) {
1912 	case PCI_DEVICE_ID_RME_DIGI96:
1913 	case PCI_DEVICE_ID_RME_DIGI96_8:
1914 		items = 3;
1915 		break;
1916 	case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1917 		items = 4;
1918 		break;
1919 	case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1920 		if (rme96->rev > 4) {
1921 			/* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1922 			if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1923 				ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1924 			}
1925 			items = 4;
1926 		} else {
1927 			items = 5;
1928 		}
1929 		break;
1930 	default:
1931 		snd_BUG();
1932 		break;
1933 	}
1934 	if (ucontrol->value.enumerated.item[0] >= items) {
1935 		ucontrol->value.enumerated.item[0] = items - 1;
1936 	}
1937 
1938 	spin_unlock_irq(&rme96->lock);
1939 	return 0;
1940 }
1941 static int
1942 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1943 {
1944 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1945 	unsigned int val;
1946 	int change, items = 3;
1947 
1948 	switch (rme96->pci->device) {
1949 	case PCI_DEVICE_ID_RME_DIGI96:
1950 	case PCI_DEVICE_ID_RME_DIGI96_8:
1951 		items = 3;
1952 		break;
1953 	case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1954 		items = 4;
1955 		break;
1956 	case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1957 		if (rme96->rev > 4) {
1958 			items = 4;
1959 		} else {
1960 			items = 5;
1961 		}
1962 		break;
1963 	default:
1964 		snd_BUG();
1965 		break;
1966 	}
1967 	val = ucontrol->value.enumerated.item[0] % items;
1968 
1969 	/* special case for PST */
1970 	if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1971 		if (val == RME96_INPUT_XLR) {
1972 			val = RME96_INPUT_ANALOG;
1973 		}
1974 	}
1975 
1976 	spin_lock_irq(&rme96->lock);
1977 	change = (int)val != snd_rme96_getinputtype(rme96);
1978 	snd_rme96_setinputtype(rme96, val);
1979 	spin_unlock_irq(&rme96->lock);
1980 	return change;
1981 }
1982 
1983 static int
1984 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1985 {
1986 	static char *texts[3] = { "AutoSync", "Internal", "Word" };
1987 
1988 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1989 	uinfo->count = 1;
1990 	uinfo->value.enumerated.items = 3;
1991 	if (uinfo->value.enumerated.item > 2) {
1992 		uinfo->value.enumerated.item = 2;
1993 	}
1994 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1995 	return 0;
1996 }
1997 static int
1998 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1999 {
2000 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2001 
2002 	spin_lock_irq(&rme96->lock);
2003 	ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
2004 	spin_unlock_irq(&rme96->lock);
2005 	return 0;
2006 }
2007 static int
2008 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2009 {
2010 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2011 	unsigned int val;
2012 	int change;
2013 
2014 	val = ucontrol->value.enumerated.item[0] % 3;
2015 	spin_lock_irq(&rme96->lock);
2016 	change = (int)val != snd_rme96_getclockmode(rme96);
2017 	snd_rme96_setclockmode(rme96, val);
2018 	spin_unlock_irq(&rme96->lock);
2019 	return change;
2020 }
2021 
2022 static int
2023 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2024 {
2025 	static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2026 
2027 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2028 	uinfo->count = 1;
2029 	uinfo->value.enumerated.items = 4;
2030 	if (uinfo->value.enumerated.item > 3) {
2031 		uinfo->value.enumerated.item = 3;
2032 	}
2033 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2034 	return 0;
2035 }
2036 static int
2037 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2038 {
2039 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2040 
2041 	spin_lock_irq(&rme96->lock);
2042 	ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2043 	spin_unlock_irq(&rme96->lock);
2044 	return 0;
2045 }
2046 static int
2047 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2048 {
2049 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2050 	unsigned int val;
2051 	int change;
2052 
2053 	val = ucontrol->value.enumerated.item[0] % 4;
2054 	spin_lock_irq(&rme96->lock);
2055 
2056 	change = (int)val != snd_rme96_getattenuation(rme96);
2057 	snd_rme96_setattenuation(rme96, val);
2058 	spin_unlock_irq(&rme96->lock);
2059 	return change;
2060 }
2061 
2062 static int
2063 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2064 {
2065 	static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2066 
2067 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2068 	uinfo->count = 1;
2069 	uinfo->value.enumerated.items = 4;
2070 	if (uinfo->value.enumerated.item > 3) {
2071 		uinfo->value.enumerated.item = 3;
2072 	}
2073 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2074 	return 0;
2075 }
2076 static int
2077 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2078 {
2079 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2080 
2081 	spin_lock_irq(&rme96->lock);
2082 	ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2083 	spin_unlock_irq(&rme96->lock);
2084 	return 0;
2085 }
2086 static int
2087 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2088 {
2089 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2090 	unsigned int val;
2091 	int change;
2092 
2093 	val = ucontrol->value.enumerated.item[0] % 4;
2094 	spin_lock_irq(&rme96->lock);
2095 	change = (int)val != snd_rme96_getmontracks(rme96);
2096 	snd_rme96_setmontracks(rme96, val);
2097 	spin_unlock_irq(&rme96->lock);
2098 	return change;
2099 }
2100 
2101 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2102 {
2103 	u32 val = 0;
2104 	val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2105 	val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2106 	if (val & RME96_WCR_PRO)
2107 		val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2108 	else
2109 		val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2110 	return val;
2111 }
2112 
2113 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2114 {
2115 	aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2116 			 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2117 	if (val & RME96_WCR_PRO)
2118 		aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2119 	else
2120 		aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2121 }
2122 
2123 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2124 {
2125 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2126 	uinfo->count = 1;
2127 	return 0;
2128 }
2129 
2130 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2131 {
2132 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2133 
2134 	snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2135 	return 0;
2136 }
2137 
2138 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2139 {
2140 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2141 	int change;
2142 	u32 val;
2143 
2144 	val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2145 	spin_lock_irq(&rme96->lock);
2146 	change = val != rme96->wcreg_spdif;
2147 	rme96->wcreg_spdif = val;
2148 	spin_unlock_irq(&rme96->lock);
2149 	return change;
2150 }
2151 
2152 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2153 {
2154 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2155 	uinfo->count = 1;
2156 	return 0;
2157 }
2158 
2159 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2160 {
2161 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2162 
2163 	snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2164 	return 0;
2165 }
2166 
2167 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2168 {
2169 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2170 	int change;
2171 	u32 val;
2172 
2173 	val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2174 	spin_lock_irq(&rme96->lock);
2175 	change = val != rme96->wcreg_spdif_stream;
2176 	rme96->wcreg_spdif_stream = val;
2177 	rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2178 	rme96->wcreg |= val;
2179 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2180 	spin_unlock_irq(&rme96->lock);
2181 	return change;
2182 }
2183 
2184 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2185 {
2186 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2187 	uinfo->count = 1;
2188 	return 0;
2189 }
2190 
2191 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2192 {
2193 	ucontrol->value.iec958.status[0] = kcontrol->private_value;
2194 	return 0;
2195 }
2196 
2197 static int
2198 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2199 {
2200 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2201 
2202         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2203         uinfo->count = 2;
2204         uinfo->value.integer.min = 0;
2205 	uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2206         return 0;
2207 }
2208 
2209 static int
2210 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2211 {
2212 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2213 
2214 	spin_lock_irq(&rme96->lock);
2215         u->value.integer.value[0] = rme96->vol[0];
2216         u->value.integer.value[1] = rme96->vol[1];
2217 	spin_unlock_irq(&rme96->lock);
2218 
2219         return 0;
2220 }
2221 
2222 static int
2223 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2224 {
2225 	struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2226         int change = 0;
2227 
2228 	if (!RME96_HAS_ANALOG_OUT(rme96)) {
2229 		return -EINVAL;
2230 	}
2231 	spin_lock_irq(&rme96->lock);
2232         if (u->value.integer.value[0] != rme96->vol[0]) {
2233 		rme96->vol[0] = u->value.integer.value[0];
2234                 change = 1;
2235         }
2236         if (u->value.integer.value[1] != rme96->vol[1]) {
2237 		rme96->vol[1] = u->value.integer.value[1];
2238                 change = 1;
2239         }
2240 	if (change) {
2241 		snd_rme96_apply_dac_volume(rme96);
2242 	}
2243 	spin_unlock_irq(&rme96->lock);
2244 
2245         return change;
2246 }
2247 
2248 static struct snd_kcontrol_new snd_rme96_controls[] = {
2249 {
2250 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2251 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2252 	.info =		snd_rme96_control_spdif_info,
2253 	.get =		snd_rme96_control_spdif_get,
2254 	.put =		snd_rme96_control_spdif_put
2255 },
2256 {
2257 	.access =	SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2258 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2259 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2260 	.info =		snd_rme96_control_spdif_stream_info,
2261 	.get =		snd_rme96_control_spdif_stream_get,
2262 	.put =		snd_rme96_control_spdif_stream_put
2263 },
2264 {
2265 	.access =	SNDRV_CTL_ELEM_ACCESS_READ,
2266 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2267 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2268 	.info =		snd_rme96_control_spdif_mask_info,
2269 	.get =		snd_rme96_control_spdif_mask_get,
2270 	.private_value = IEC958_AES0_NONAUDIO |
2271 			IEC958_AES0_PROFESSIONAL |
2272 			IEC958_AES0_CON_EMPHASIS
2273 },
2274 {
2275 	.access =	SNDRV_CTL_ELEM_ACCESS_READ,
2276 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2277 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2278 	.info =		snd_rme96_control_spdif_mask_info,
2279 	.get =		snd_rme96_control_spdif_mask_get,
2280 	.private_value = IEC958_AES0_NONAUDIO |
2281 			IEC958_AES0_PROFESSIONAL |
2282 			IEC958_AES0_PRO_EMPHASIS
2283 },
2284 {
2285         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2286 	.name =         "Input Connector",
2287 	.info =         snd_rme96_info_inputtype_control,
2288 	.get =          snd_rme96_get_inputtype_control,
2289 	.put =          snd_rme96_put_inputtype_control
2290 },
2291 {
2292         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2293 	.name =         "Loopback Input",
2294 	.info =         snd_rme96_info_loopback_control,
2295 	.get =          snd_rme96_get_loopback_control,
2296 	.put =          snd_rme96_put_loopback_control
2297 },
2298 {
2299         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2300 	.name =         "Sample Clock Source",
2301 	.info =         snd_rme96_info_clockmode_control,
2302 	.get =          snd_rme96_get_clockmode_control,
2303 	.put =          snd_rme96_put_clockmode_control
2304 },
2305 {
2306         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2307 	.name =         "Monitor Tracks",
2308 	.info =         snd_rme96_info_montracks_control,
2309 	.get =          snd_rme96_get_montracks_control,
2310 	.put =          snd_rme96_put_montracks_control
2311 },
2312 {
2313         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2314 	.name =         "Attenuation",
2315 	.info =         snd_rme96_info_attenuation_control,
2316 	.get =          snd_rme96_get_attenuation_control,
2317 	.put =          snd_rme96_put_attenuation_control
2318 },
2319 {
2320         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
2321 	.name =         "DAC Playback Volume",
2322 	.info =         snd_rme96_dac_volume_info,
2323 	.get =          snd_rme96_dac_volume_get,
2324 	.put =          snd_rme96_dac_volume_put
2325 }
2326 };
2327 
2328 static int
2329 snd_rme96_create_switches(struct snd_card *card,
2330 			  struct rme96 *rme96)
2331 {
2332 	int idx, err;
2333 	struct snd_kcontrol *kctl;
2334 
2335 	for (idx = 0; idx < 7; idx++) {
2336 		if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2337 			return err;
2338 		if (idx == 1)	/* IEC958 (S/PDIF) Stream */
2339 			rme96->spdif_ctl = kctl;
2340 	}
2341 
2342 	if (RME96_HAS_ANALOG_OUT(rme96)) {
2343 		for (idx = 7; idx < 10; idx++)
2344 			if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2345 				return err;
2346 	}
2347 
2348 	return 0;
2349 }
2350 
2351 /*
2352  * Card initialisation
2353  */
2354 
2355 static void snd_rme96_card_free(struct snd_card *card)
2356 {
2357 	snd_rme96_free(card->private_data);
2358 }
2359 
2360 static int __devinit
2361 snd_rme96_probe(struct pci_dev *pci,
2362 		const struct pci_device_id *pci_id)
2363 {
2364 	static int dev;
2365 	struct rme96 *rme96;
2366 	struct snd_card *card;
2367 	int err;
2368 	u8 val;
2369 
2370 	if (dev >= SNDRV_CARDS) {
2371 		return -ENODEV;
2372 	}
2373 	if (!enable[dev]) {
2374 		dev++;
2375 		return -ENOENT;
2376 	}
2377 	if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2378 				 sizeof(struct rme96))) == NULL)
2379 		return -ENOMEM;
2380 	card->private_free = snd_rme96_card_free;
2381 	rme96 = (struct rme96 *)card->private_data;
2382 	rme96->card = card;
2383 	rme96->pci = pci;
2384 	snd_card_set_dev(card, &pci->dev);
2385 	if ((err = snd_rme96_create(rme96)) < 0) {
2386 		snd_card_free(card);
2387 		return err;
2388 	}
2389 
2390 	strcpy(card->driver, "Digi96");
2391 	switch (rme96->pci->device) {
2392 	case PCI_DEVICE_ID_RME_DIGI96:
2393 		strcpy(card->shortname, "RME Digi96");
2394 		break;
2395 	case PCI_DEVICE_ID_RME_DIGI96_8:
2396 		strcpy(card->shortname, "RME Digi96/8");
2397 		break;
2398 	case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2399 		strcpy(card->shortname, "RME Digi96/8 PRO");
2400 		break;
2401 	case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2402 		pci_read_config_byte(rme96->pci, 8, &val);
2403 		if (val < 5) {
2404 			strcpy(card->shortname, "RME Digi96/8 PAD");
2405 		} else {
2406 			strcpy(card->shortname, "RME Digi96/8 PST");
2407 		}
2408 		break;
2409 	}
2410 	sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2411 		rme96->port, rme96->irq);
2412 
2413 	if ((err = snd_card_register(card)) < 0) {
2414 		snd_card_free(card);
2415 		return err;
2416 	}
2417 	pci_set_drvdata(pci, card);
2418 	dev++;
2419 	return 0;
2420 }
2421 
2422 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2423 {
2424 	snd_card_free(pci_get_drvdata(pci));
2425 	pci_set_drvdata(pci, NULL);
2426 }
2427 
2428 static struct pci_driver driver = {
2429 	.name = "RME Digi96",
2430 	.id_table = snd_rme96_ids,
2431 	.probe = snd_rme96_probe,
2432 	.remove = __devexit_p(snd_rme96_remove),
2433 };
2434 
2435 static int __init alsa_card_rme96_init(void)
2436 {
2437 	return pci_register_driver(&driver);
2438 }
2439 
2440 static void __exit alsa_card_rme96_exit(void)
2441 {
2442 	pci_unregister_driver(&driver);
2443 }
2444 
2445 module_init(alsa_card_rme96_init)
2446 module_exit(alsa_card_rme96_exit)
2447