1 /* 2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio 3 * interfaces 4 * 5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se> 6 * 7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control 8 * code. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26 #include <sound/driver.h> 27 #include <linux/delay.h> 28 #include <linux/init.h> 29 #include <linux/interrupt.h> 30 #include <linux/pci.h> 31 #include <linux/slab.h> 32 #include <linux/moduleparam.h> 33 34 #include <sound/core.h> 35 #include <sound/info.h> 36 #include <sound/control.h> 37 #include <sound/pcm.h> 38 #include <sound/pcm_params.h> 39 #include <sound/asoundef.h> 40 #include <sound/initval.h> 41 42 #include <asm/io.h> 43 44 /* note, two last pcis should be equal, it is not a bug */ 45 46 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>"); 47 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, " 48 "Digi96/8 PAD"); 49 MODULE_LICENSE("GPL"); 50 MODULE_SUPPORTED_DEVICE("{{RME,Digi96}," 51 "{RME,Digi96/8}," 52 "{RME,Digi96/8 PRO}," 53 "{RME,Digi96/8 PST}," 54 "{RME,Digi96/8 PAD}}"); 55 56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 59 60 module_param_array(index, int, NULL, 0444); 61 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard."); 62 module_param_array(id, charp, NULL, 0444); 63 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard."); 64 module_param_array(enable, bool, NULL, 0444); 65 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard."); 66 67 /* 68 * Defines for RME Digi96 series, from internal RME reference documents 69 * dated 12.01.00 70 */ 71 72 #define RME96_SPDIF_NCHANNELS 2 73 74 /* Playback and capture buffer size */ 75 #define RME96_BUFFER_SIZE 0x10000 76 77 /* IO area size */ 78 #define RME96_IO_SIZE 0x60000 79 80 /* IO area offsets */ 81 #define RME96_IO_PLAY_BUFFER 0x0 82 #define RME96_IO_REC_BUFFER 0x10000 83 #define RME96_IO_CONTROL_REGISTER 0x20000 84 #define RME96_IO_ADDITIONAL_REG 0x20004 85 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 86 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C 87 #define RME96_IO_SET_PLAY_POS 0x40000 88 #define RME96_IO_RESET_PLAY_POS 0x4FFFC 89 #define RME96_IO_SET_REC_POS 0x50000 90 #define RME96_IO_RESET_REC_POS 0x5FFFC 91 #define RME96_IO_GET_PLAY_POS 0x20000 92 #define RME96_IO_GET_REC_POS 0x30000 93 94 /* Write control register bits */ 95 #define RME96_WCR_START (1 << 0) 96 #define RME96_WCR_START_2 (1 << 1) 97 #define RME96_WCR_GAIN_0 (1 << 2) 98 #define RME96_WCR_GAIN_1 (1 << 3) 99 #define RME96_WCR_MODE24 (1 << 4) 100 #define RME96_WCR_MODE24_2 (1 << 5) 101 #define RME96_WCR_BM (1 << 6) 102 #define RME96_WCR_BM_2 (1 << 7) 103 #define RME96_WCR_ADAT (1 << 8) 104 #define RME96_WCR_FREQ_0 (1 << 9) 105 #define RME96_WCR_FREQ_1 (1 << 10) 106 #define RME96_WCR_DS (1 << 11) 107 #define RME96_WCR_PRO (1 << 12) 108 #define RME96_WCR_EMP (1 << 13) 109 #define RME96_WCR_SEL (1 << 14) 110 #define RME96_WCR_MASTER (1 << 15) 111 #define RME96_WCR_PD (1 << 16) 112 #define RME96_WCR_INP_0 (1 << 17) 113 #define RME96_WCR_INP_1 (1 << 18) 114 #define RME96_WCR_THRU_0 (1 << 19) 115 #define RME96_WCR_THRU_1 (1 << 20) 116 #define RME96_WCR_THRU_2 (1 << 21) 117 #define RME96_WCR_THRU_3 (1 << 22) 118 #define RME96_WCR_THRU_4 (1 << 23) 119 #define RME96_WCR_THRU_5 (1 << 24) 120 #define RME96_WCR_THRU_6 (1 << 25) 121 #define RME96_WCR_THRU_7 (1 << 26) 122 #define RME96_WCR_DOLBY (1 << 27) 123 #define RME96_WCR_MONITOR_0 (1 << 28) 124 #define RME96_WCR_MONITOR_1 (1 << 29) 125 #define RME96_WCR_ISEL (1 << 30) 126 #define RME96_WCR_IDIS (1 << 31) 127 128 #define RME96_WCR_BITPOS_GAIN_0 2 129 #define RME96_WCR_BITPOS_GAIN_1 3 130 #define RME96_WCR_BITPOS_FREQ_0 9 131 #define RME96_WCR_BITPOS_FREQ_1 10 132 #define RME96_WCR_BITPOS_INP_0 17 133 #define RME96_WCR_BITPOS_INP_1 18 134 #define RME96_WCR_BITPOS_MONITOR_0 28 135 #define RME96_WCR_BITPOS_MONITOR_1 29 136 137 /* Read control register bits */ 138 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF 139 #define RME96_RCR_IRQ_2 (1 << 16) 140 #define RME96_RCR_T_OUT (1 << 17) 141 #define RME96_RCR_DEV_ID_0 (1 << 21) 142 #define RME96_RCR_DEV_ID_1 (1 << 22) 143 #define RME96_RCR_LOCK (1 << 23) 144 #define RME96_RCR_VERF (1 << 26) 145 #define RME96_RCR_F0 (1 << 27) 146 #define RME96_RCR_F1 (1 << 28) 147 #define RME96_RCR_F2 (1 << 29) 148 #define RME96_RCR_AUTOSYNC (1 << 30) 149 #define RME96_RCR_IRQ (1 << 31) 150 151 #define RME96_RCR_BITPOS_F0 27 152 #define RME96_RCR_BITPOS_F1 28 153 #define RME96_RCR_BITPOS_F2 29 154 155 /* Additonal register bits */ 156 #define RME96_AR_WSEL (1 << 0) 157 #define RME96_AR_ANALOG (1 << 1) 158 #define RME96_AR_FREQPAD_0 (1 << 2) 159 #define RME96_AR_FREQPAD_1 (1 << 3) 160 #define RME96_AR_FREQPAD_2 (1 << 4) 161 #define RME96_AR_PD2 (1 << 5) 162 #define RME96_AR_DAC_EN (1 << 6) 163 #define RME96_AR_CLATCH (1 << 7) 164 #define RME96_AR_CCLK (1 << 8) 165 #define RME96_AR_CDATA (1 << 9) 166 167 #define RME96_AR_BITPOS_F0 2 168 #define RME96_AR_BITPOS_F1 3 169 #define RME96_AR_BITPOS_F2 4 170 171 /* Monitor tracks */ 172 #define RME96_MONITOR_TRACKS_1_2 0 173 #define RME96_MONITOR_TRACKS_3_4 1 174 #define RME96_MONITOR_TRACKS_5_6 2 175 #define RME96_MONITOR_TRACKS_7_8 3 176 177 /* Attenuation */ 178 #define RME96_ATTENUATION_0 0 179 #define RME96_ATTENUATION_6 1 180 #define RME96_ATTENUATION_12 2 181 #define RME96_ATTENUATION_18 3 182 183 /* Input types */ 184 #define RME96_INPUT_OPTICAL 0 185 #define RME96_INPUT_COAXIAL 1 186 #define RME96_INPUT_INTERNAL 2 187 #define RME96_INPUT_XLR 3 188 #define RME96_INPUT_ANALOG 4 189 190 /* Clock modes */ 191 #define RME96_CLOCKMODE_SLAVE 0 192 #define RME96_CLOCKMODE_MASTER 1 193 #define RME96_CLOCKMODE_WORDCLOCK 2 194 195 /* Block sizes in bytes */ 196 #define RME96_SMALL_BLOCK_SIZE 2048 197 #define RME96_LARGE_BLOCK_SIZE 8192 198 199 /* Volume control */ 200 #define RME96_AD1852_VOL_BITS 14 201 #define RME96_AD1855_VOL_BITS 10 202 203 /* 204 * PCI vendor/device ids, could in the future be defined in <linux/pci.h>, 205 * therefore #ifndef is used. 206 */ 207 #ifndef PCI_VENDOR_ID_XILINX 208 #define PCI_VENDOR_ID_XILINX 0x10ee 209 #endif 210 #ifndef PCI_DEVICE_ID_DIGI96 211 #define PCI_DEVICE_ID_DIGI96 0x3fc0 212 #endif 213 #ifndef PCI_DEVICE_ID_DIGI96_8 214 #define PCI_DEVICE_ID_DIGI96_8 0x3fc1 215 #endif 216 #ifndef PCI_DEVICE_ID_DIGI96_8_PRO 217 #define PCI_DEVICE_ID_DIGI96_8_PRO 0x3fc2 218 #endif 219 #ifndef PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST 220 #define PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST 0x3fc3 221 #endif 222 223 typedef struct snd_rme96 { 224 spinlock_t lock; 225 int irq; 226 unsigned long port; 227 void __iomem *iobase; 228 229 u32 wcreg; /* cached write control register value */ 230 u32 wcreg_spdif; /* S/PDIF setup */ 231 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ 232 u32 rcreg; /* cached read control register value */ 233 u32 areg; /* cached additional register value */ 234 u16 vol[2]; /* cached volume of analog output */ 235 236 u8 rev; /* card revision number */ 237 238 snd_pcm_substream_t *playback_substream; 239 snd_pcm_substream_t *capture_substream; 240 241 int playback_frlog; /* log2 of framesize */ 242 int capture_frlog; 243 244 size_t playback_periodsize; /* in bytes, zero if not used */ 245 size_t capture_periodsize; /* in bytes, zero if not used */ 246 247 snd_card_t *card; 248 snd_pcm_t *spdif_pcm; 249 snd_pcm_t *adat_pcm; 250 struct pci_dev *pci; 251 snd_kcontrol_t *spdif_ctl; 252 } rme96_t; 253 254 static struct pci_device_id snd_rme96_ids[] = { 255 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96, 256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, 257 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8, 258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, 259 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PRO, 260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, 261 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST, 262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, 263 { 0, } 264 }; 265 266 MODULE_DEVICE_TABLE(pci, snd_rme96_ids); 267 268 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START) 269 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2) 270 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST) 271 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO || \ 272 (rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST) 273 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4) 274 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \ 275 ((rme96)->pci->device == PCI_DEVICE_ID_DIGI96_8_PRO && (rme96)->rev == 2)) 276 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1) 277 278 static int 279 snd_rme96_playback_prepare(snd_pcm_substream_t *substream); 280 281 static int 282 snd_rme96_capture_prepare(snd_pcm_substream_t *substream); 283 284 static int 285 snd_rme96_playback_trigger(snd_pcm_substream_t *substream, 286 int cmd); 287 288 static int 289 snd_rme96_capture_trigger(snd_pcm_substream_t *substream, 290 int cmd); 291 292 static snd_pcm_uframes_t 293 snd_rme96_playback_pointer(snd_pcm_substream_t *substream); 294 295 static snd_pcm_uframes_t 296 snd_rme96_capture_pointer(snd_pcm_substream_t *substream); 297 298 static void __devinit 299 snd_rme96_proc_init(rme96_t *rme96); 300 301 static int 302 snd_rme96_create_switches(snd_card_t *card, 303 rme96_t *rme96); 304 305 static int 306 snd_rme96_getinputtype(rme96_t *rme96); 307 308 static inline unsigned int 309 snd_rme96_playback_ptr(rme96_t *rme96) 310 { 311 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 312 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog; 313 } 314 315 static inline unsigned int 316 snd_rme96_capture_ptr(rme96_t *rme96) 317 { 318 return (readl(rme96->iobase + RME96_IO_GET_REC_POS) 319 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog; 320 } 321 322 static int 323 snd_rme96_ratecode(int rate) 324 { 325 switch (rate) { 326 case 32000: return SNDRV_PCM_RATE_32000; 327 case 44100: return SNDRV_PCM_RATE_44100; 328 case 48000: return SNDRV_PCM_RATE_48000; 329 case 64000: return SNDRV_PCM_RATE_64000; 330 case 88200: return SNDRV_PCM_RATE_88200; 331 case 96000: return SNDRV_PCM_RATE_96000; 332 } 333 return 0; 334 } 335 336 static int 337 snd_rme96_playback_silence(snd_pcm_substream_t *substream, 338 int channel, /* not used (interleaved data) */ 339 snd_pcm_uframes_t pos, 340 snd_pcm_uframes_t count) 341 { 342 rme96_t *rme96 = snd_pcm_substream_chip(substream); 343 count <<= rme96->playback_frlog; 344 pos <<= rme96->playback_frlog; 345 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 346 0, count); 347 return 0; 348 } 349 350 static int 351 snd_rme96_playback_copy(snd_pcm_substream_t *substream, 352 int channel, /* not used (interleaved data) */ 353 snd_pcm_uframes_t pos, 354 void __user *src, 355 snd_pcm_uframes_t count) 356 { 357 rme96_t *rme96 = snd_pcm_substream_chip(substream); 358 count <<= rme96->playback_frlog; 359 pos <<= rme96->playback_frlog; 360 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, 361 count); 362 return 0; 363 } 364 365 static int 366 snd_rme96_capture_copy(snd_pcm_substream_t *substream, 367 int channel, /* not used (interleaved data) */ 368 snd_pcm_uframes_t pos, 369 void __user *dst, 370 snd_pcm_uframes_t count) 371 { 372 rme96_t *rme96 = snd_pcm_substream_chip(substream); 373 count <<= rme96->capture_frlog; 374 pos <<= rme96->capture_frlog; 375 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, 376 count); 377 return 0; 378 } 379 380 /* 381 * Digital output capabilites (S/PDIF) 382 */ 383 static snd_pcm_hardware_t snd_rme96_playback_spdif_info = 384 { 385 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 386 SNDRV_PCM_INFO_MMAP_VALID | 387 SNDRV_PCM_INFO_INTERLEAVED | 388 SNDRV_PCM_INFO_PAUSE), 389 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 390 SNDRV_PCM_FMTBIT_S32_LE), 391 .rates = (SNDRV_PCM_RATE_32000 | 392 SNDRV_PCM_RATE_44100 | 393 SNDRV_PCM_RATE_48000 | 394 SNDRV_PCM_RATE_64000 | 395 SNDRV_PCM_RATE_88200 | 396 SNDRV_PCM_RATE_96000), 397 .rate_min = 32000, 398 .rate_max = 96000, 399 .channels_min = 2, 400 .channels_max = 2, 401 .buffer_bytes_max = RME96_BUFFER_SIZE, 402 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 403 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 404 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 405 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 406 .fifo_size = 0, 407 }; 408 409 /* 410 * Digital input capabilites (S/PDIF) 411 */ 412 static snd_pcm_hardware_t snd_rme96_capture_spdif_info = 413 { 414 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 415 SNDRV_PCM_INFO_MMAP_VALID | 416 SNDRV_PCM_INFO_INTERLEAVED | 417 SNDRV_PCM_INFO_PAUSE), 418 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 419 SNDRV_PCM_FMTBIT_S32_LE), 420 .rates = (SNDRV_PCM_RATE_32000 | 421 SNDRV_PCM_RATE_44100 | 422 SNDRV_PCM_RATE_48000 | 423 SNDRV_PCM_RATE_64000 | 424 SNDRV_PCM_RATE_88200 | 425 SNDRV_PCM_RATE_96000), 426 .rate_min = 32000, 427 .rate_max = 96000, 428 .channels_min = 2, 429 .channels_max = 2, 430 .buffer_bytes_max = RME96_BUFFER_SIZE, 431 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 432 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 433 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 434 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 435 .fifo_size = 0, 436 }; 437 438 /* 439 * Digital output capabilites (ADAT) 440 */ 441 static snd_pcm_hardware_t snd_rme96_playback_adat_info = 442 { 443 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 444 SNDRV_PCM_INFO_MMAP_VALID | 445 SNDRV_PCM_INFO_INTERLEAVED | 446 SNDRV_PCM_INFO_PAUSE), 447 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 448 SNDRV_PCM_FMTBIT_S32_LE), 449 .rates = (SNDRV_PCM_RATE_44100 | 450 SNDRV_PCM_RATE_48000), 451 .rate_min = 44100, 452 .rate_max = 48000, 453 .channels_min = 8, 454 .channels_max = 8, 455 .buffer_bytes_max = RME96_BUFFER_SIZE, 456 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 457 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 458 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 459 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 460 .fifo_size = 0, 461 }; 462 463 /* 464 * Digital input capabilites (ADAT) 465 */ 466 static snd_pcm_hardware_t snd_rme96_capture_adat_info = 467 { 468 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 469 SNDRV_PCM_INFO_MMAP_VALID | 470 SNDRV_PCM_INFO_INTERLEAVED | 471 SNDRV_PCM_INFO_PAUSE), 472 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 473 SNDRV_PCM_FMTBIT_S32_LE), 474 .rates = (SNDRV_PCM_RATE_44100 | 475 SNDRV_PCM_RATE_48000), 476 .rate_min = 44100, 477 .rate_max = 48000, 478 .channels_min = 8, 479 .channels_max = 8, 480 .buffer_bytes_max = RME96_BUFFER_SIZE, 481 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 482 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 483 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 484 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 485 .fifo_size = 0, 486 }; 487 488 /* 489 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface 490 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up 491 * on the falling edge of CCLK and be stable on the rising edge. The rising 492 * edge of CLATCH after the last data bit clocks in the whole data word. 493 * A fast processor could probably drive the SPI interface faster than the 494 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1) 495 * limits the data rate to 500KHz and only causes a delay of 33 microsecs. 496 * 497 * NOTE: increased delay from 1 to 10, since there where problems setting 498 * the volume. 499 */ 500 static void 501 snd_rme96_write_SPI(rme96_t *rme96, u16 val) 502 { 503 int i; 504 505 for (i = 0; i < 16; i++) { 506 if (val & 0x8000) { 507 rme96->areg |= RME96_AR_CDATA; 508 } else { 509 rme96->areg &= ~RME96_AR_CDATA; 510 } 511 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH); 512 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 513 udelay(10); 514 rme96->areg |= RME96_AR_CCLK; 515 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 516 udelay(10); 517 val <<= 1; 518 } 519 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA); 520 rme96->areg |= RME96_AR_CLATCH; 521 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 522 udelay(10); 523 rme96->areg &= ~RME96_AR_CLATCH; 524 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 525 } 526 527 static void 528 snd_rme96_apply_dac_volume(rme96_t *rme96) 529 { 530 if (RME96_DAC_IS_1852(rme96)) { 531 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0); 532 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2); 533 } else if (RME96_DAC_IS_1855(rme96)) { 534 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000); 535 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400); 536 } 537 } 538 539 static void 540 snd_rme96_reset_dac(rme96_t *rme96) 541 { 542 writel(rme96->wcreg | RME96_WCR_PD, 543 rme96->iobase + RME96_IO_CONTROL_REGISTER); 544 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 545 } 546 547 static int 548 snd_rme96_getmontracks(rme96_t *rme96) 549 { 550 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + 551 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); 552 } 553 554 static int 555 snd_rme96_setmontracks(rme96_t *rme96, 556 int montracks) 557 { 558 if (montracks & 1) { 559 rme96->wcreg |= RME96_WCR_MONITOR_0; 560 } else { 561 rme96->wcreg &= ~RME96_WCR_MONITOR_0; 562 } 563 if (montracks & 2) { 564 rme96->wcreg |= RME96_WCR_MONITOR_1; 565 } else { 566 rme96->wcreg &= ~RME96_WCR_MONITOR_1; 567 } 568 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 569 return 0; 570 } 571 572 static int 573 snd_rme96_getattenuation(rme96_t *rme96) 574 { 575 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + 576 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); 577 } 578 579 static int 580 snd_rme96_setattenuation(rme96_t *rme96, 581 int attenuation) 582 { 583 switch (attenuation) { 584 case 0: 585 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & 586 ~RME96_WCR_GAIN_1; 587 break; 588 case 1: 589 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & 590 ~RME96_WCR_GAIN_1; 591 break; 592 case 2: 593 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | 594 RME96_WCR_GAIN_1; 595 break; 596 case 3: 597 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | 598 RME96_WCR_GAIN_1; 599 break; 600 default: 601 return -EINVAL; 602 } 603 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 604 return 0; 605 } 606 607 static int 608 snd_rme96_capture_getrate(rme96_t *rme96, 609 int *is_adat) 610 { 611 int n, rate; 612 613 *is_adat = 0; 614 if (rme96->areg & RME96_AR_ANALOG) { 615 /* Analog input, overrides S/PDIF setting */ 616 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) + 617 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1); 618 switch (n) { 619 case 1: 620 rate = 32000; 621 break; 622 case 2: 623 rate = 44100; 624 break; 625 case 3: 626 rate = 48000; 627 break; 628 default: 629 return -1; 630 } 631 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate; 632 } 633 634 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 635 if (rme96->rcreg & RME96_RCR_LOCK) { 636 /* ADAT rate */ 637 *is_adat = 1; 638 if (rme96->rcreg & RME96_RCR_T_OUT) { 639 return 48000; 640 } 641 return 44100; 642 } 643 644 if (rme96->rcreg & RME96_RCR_VERF) { 645 return -1; 646 } 647 648 /* S/PDIF rate */ 649 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) + 650 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) + 651 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2); 652 653 switch (n) { 654 case 0: 655 if (rme96->rcreg & RME96_RCR_T_OUT) { 656 return 64000; 657 } 658 return -1; 659 case 3: return 96000; 660 case 4: return 88200; 661 case 5: return 48000; 662 case 6: return 44100; 663 case 7: return 32000; 664 default: 665 break; 666 } 667 return -1; 668 } 669 670 static int 671 snd_rme96_playback_getrate(rme96_t *rme96) 672 { 673 int rate, dummy; 674 675 if (!(rme96->wcreg & RME96_WCR_MASTER) && 676 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 677 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 678 { 679 /* slave clock */ 680 return rate; 681 } 682 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + 683 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); 684 switch (rate) { 685 case 1: 686 rate = 32000; 687 break; 688 case 2: 689 rate = 44100; 690 break; 691 case 3: 692 rate = 48000; 693 break; 694 default: 695 return -1; 696 } 697 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; 698 } 699 700 static int 701 snd_rme96_playback_setrate(rme96_t *rme96, 702 int rate) 703 { 704 int ds; 705 706 ds = rme96->wcreg & RME96_WCR_DS; 707 switch (rate) { 708 case 32000: 709 rme96->wcreg &= ~RME96_WCR_DS; 710 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 711 ~RME96_WCR_FREQ_1; 712 break; 713 case 44100: 714 rme96->wcreg &= ~RME96_WCR_DS; 715 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 716 ~RME96_WCR_FREQ_0; 717 break; 718 case 48000: 719 rme96->wcreg &= ~RME96_WCR_DS; 720 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 721 RME96_WCR_FREQ_1; 722 break; 723 case 64000: 724 rme96->wcreg |= RME96_WCR_DS; 725 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 726 ~RME96_WCR_FREQ_1; 727 break; 728 case 88200: 729 rme96->wcreg |= RME96_WCR_DS; 730 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 731 ~RME96_WCR_FREQ_0; 732 break; 733 case 96000: 734 rme96->wcreg |= RME96_WCR_DS; 735 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 736 RME96_WCR_FREQ_1; 737 break; 738 default: 739 return -EINVAL; 740 } 741 if ((!ds && rme96->wcreg & RME96_WCR_DS) || 742 (ds && !(rme96->wcreg & RME96_WCR_DS))) 743 { 744 /* change to/from double-speed: reset the DAC (if available) */ 745 snd_rme96_reset_dac(rme96); 746 } else { 747 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 748 } 749 return 0; 750 } 751 752 static int 753 snd_rme96_capture_analog_setrate(rme96_t *rme96, 754 int rate) 755 { 756 switch (rate) { 757 case 32000: 758 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 759 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 760 break; 761 case 44100: 762 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 763 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 764 break; 765 case 48000: 766 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 767 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 768 break; 769 case 64000: 770 if (rme96->rev < 4) { 771 return -EINVAL; 772 } 773 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 774 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 775 break; 776 case 88200: 777 if (rme96->rev < 4) { 778 return -EINVAL; 779 } 780 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 781 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 782 break; 783 case 96000: 784 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 785 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 786 break; 787 default: 788 return -EINVAL; 789 } 790 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 791 return 0; 792 } 793 794 static int 795 snd_rme96_setclockmode(rme96_t *rme96, 796 int mode) 797 { 798 switch (mode) { 799 case RME96_CLOCKMODE_SLAVE: 800 /* AutoSync */ 801 rme96->wcreg &= ~RME96_WCR_MASTER; 802 rme96->areg &= ~RME96_AR_WSEL; 803 break; 804 case RME96_CLOCKMODE_MASTER: 805 /* Internal */ 806 rme96->wcreg |= RME96_WCR_MASTER; 807 rme96->areg &= ~RME96_AR_WSEL; 808 break; 809 case RME96_CLOCKMODE_WORDCLOCK: 810 /* Word clock is a master mode */ 811 rme96->wcreg |= RME96_WCR_MASTER; 812 rme96->areg |= RME96_AR_WSEL; 813 break; 814 default: 815 return -EINVAL; 816 } 817 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 818 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 819 return 0; 820 } 821 822 static int 823 snd_rme96_getclockmode(rme96_t *rme96) 824 { 825 if (rme96->areg & RME96_AR_WSEL) { 826 return RME96_CLOCKMODE_WORDCLOCK; 827 } 828 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : 829 RME96_CLOCKMODE_SLAVE; 830 } 831 832 static int 833 snd_rme96_setinputtype(rme96_t *rme96, 834 int type) 835 { 836 int n; 837 838 switch (type) { 839 case RME96_INPUT_OPTICAL: 840 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & 841 ~RME96_WCR_INP_1; 842 break; 843 case RME96_INPUT_COAXIAL: 844 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & 845 ~RME96_WCR_INP_1; 846 break; 847 case RME96_INPUT_INTERNAL: 848 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | 849 RME96_WCR_INP_1; 850 break; 851 case RME96_INPUT_XLR: 852 if ((rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && 853 rme96->pci->device != PCI_DEVICE_ID_DIGI96_8_PRO) || 854 (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && 855 rme96->rev > 4)) 856 { 857 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */ 858 return -EINVAL; 859 } 860 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | 861 RME96_WCR_INP_1; 862 break; 863 case RME96_INPUT_ANALOG: 864 if (!RME96_HAS_ANALOG_IN(rme96)) { 865 return -EINVAL; 866 } 867 rme96->areg |= RME96_AR_ANALOG; 868 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 869 if (rme96->rev < 4) { 870 /* 871 * Revision less than 004 does not support 64 and 872 * 88.2 kHz 873 */ 874 if (snd_rme96_capture_getrate(rme96, &n) == 88200) { 875 snd_rme96_capture_analog_setrate(rme96, 44100); 876 } 877 if (snd_rme96_capture_getrate(rme96, &n) == 64000) { 878 snd_rme96_capture_analog_setrate(rme96, 32000); 879 } 880 } 881 return 0; 882 default: 883 return -EINVAL; 884 } 885 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) { 886 rme96->areg &= ~RME96_AR_ANALOG; 887 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 888 } 889 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 890 return 0; 891 } 892 893 static int 894 snd_rme96_getinputtype(rme96_t *rme96) 895 { 896 if (rme96->areg & RME96_AR_ANALOG) { 897 return RME96_INPUT_ANALOG; 898 } 899 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + 900 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); 901 } 902 903 static void 904 snd_rme96_setframelog(rme96_t *rme96, 905 int n_channels, 906 int is_playback) 907 { 908 int frlog; 909 910 if (n_channels == 2) { 911 frlog = 1; 912 } else { 913 /* assume 8 channels */ 914 frlog = 3; 915 } 916 if (is_playback) { 917 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; 918 rme96->playback_frlog = frlog; 919 } else { 920 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; 921 rme96->capture_frlog = frlog; 922 } 923 } 924 925 static int 926 snd_rme96_playback_setformat(rme96_t *rme96, 927 int format) 928 { 929 switch (format) { 930 case SNDRV_PCM_FORMAT_S16_LE: 931 rme96->wcreg &= ~RME96_WCR_MODE24; 932 break; 933 case SNDRV_PCM_FORMAT_S32_LE: 934 rme96->wcreg |= RME96_WCR_MODE24; 935 break; 936 default: 937 return -EINVAL; 938 } 939 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 940 return 0; 941 } 942 943 static int 944 snd_rme96_capture_setformat(rme96_t *rme96, 945 int format) 946 { 947 switch (format) { 948 case SNDRV_PCM_FORMAT_S16_LE: 949 rme96->wcreg &= ~RME96_WCR_MODE24_2; 950 break; 951 case SNDRV_PCM_FORMAT_S32_LE: 952 rme96->wcreg |= RME96_WCR_MODE24_2; 953 break; 954 default: 955 return -EINVAL; 956 } 957 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 958 return 0; 959 } 960 961 static void 962 snd_rme96_set_period_properties(rme96_t *rme96, 963 size_t period_bytes) 964 { 965 switch (period_bytes) { 966 case RME96_LARGE_BLOCK_SIZE: 967 rme96->wcreg &= ~RME96_WCR_ISEL; 968 break; 969 case RME96_SMALL_BLOCK_SIZE: 970 rme96->wcreg |= RME96_WCR_ISEL; 971 break; 972 default: 973 snd_BUG(); 974 break; 975 } 976 rme96->wcreg &= ~RME96_WCR_IDIS; 977 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 978 } 979 980 static int 981 snd_rme96_playback_hw_params(snd_pcm_substream_t *substream, 982 snd_pcm_hw_params_t *params) 983 { 984 rme96_t *rme96 = snd_pcm_substream_chip(substream); 985 snd_pcm_runtime_t *runtime = substream->runtime; 986 int err, rate, dummy; 987 988 runtime->dma_area = (void *)(rme96->iobase + RME96_IO_PLAY_BUFFER); 989 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER; 990 runtime->dma_bytes = RME96_BUFFER_SIZE; 991 992 spin_lock_irq(&rme96->lock); 993 if (!(rme96->wcreg & RME96_WCR_MASTER) && 994 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 995 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 996 { 997 /* slave clock */ 998 if ((int)params_rate(params) != rate) { 999 spin_unlock_irq(&rme96->lock); 1000 return -EIO; 1001 } 1002 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) { 1003 spin_unlock_irq(&rme96->lock); 1004 return err; 1005 } 1006 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) { 1007 spin_unlock_irq(&rme96->lock); 1008 return err; 1009 } 1010 snd_rme96_setframelog(rme96, params_channels(params), 1); 1011 if (rme96->capture_periodsize != 0) { 1012 if (params_period_size(params) << rme96->playback_frlog != 1013 rme96->capture_periodsize) 1014 { 1015 spin_unlock_irq(&rme96->lock); 1016 return -EBUSY; 1017 } 1018 } 1019 rme96->playback_periodsize = 1020 params_period_size(params) << rme96->playback_frlog; 1021 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize); 1022 /* S/PDIF setup */ 1023 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { 1024 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 1025 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1026 } 1027 spin_unlock_irq(&rme96->lock); 1028 1029 return 0; 1030 } 1031 1032 static int 1033 snd_rme96_capture_hw_params(snd_pcm_substream_t *substream, 1034 snd_pcm_hw_params_t *params) 1035 { 1036 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1037 snd_pcm_runtime_t *runtime = substream->runtime; 1038 int err, isadat, rate; 1039 1040 runtime->dma_area = (void *)(rme96->iobase + RME96_IO_REC_BUFFER); 1041 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER; 1042 runtime->dma_bytes = RME96_BUFFER_SIZE; 1043 1044 spin_lock_irq(&rme96->lock); 1045 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) { 1046 spin_unlock_irq(&rme96->lock); 1047 return err; 1048 } 1049 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1050 if ((err = snd_rme96_capture_analog_setrate(rme96, 1051 params_rate(params))) < 0) 1052 { 1053 spin_unlock_irq(&rme96->lock); 1054 return err; 1055 } 1056 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { 1057 if ((int)params_rate(params) != rate) { 1058 spin_unlock_irq(&rme96->lock); 1059 return -EIO; 1060 } 1061 if ((isadat && runtime->hw.channels_min == 2) || 1062 (!isadat && runtime->hw.channels_min == 8)) 1063 { 1064 spin_unlock_irq(&rme96->lock); 1065 return -EIO; 1066 } 1067 } 1068 snd_rme96_setframelog(rme96, params_channels(params), 0); 1069 if (rme96->playback_periodsize != 0) { 1070 if (params_period_size(params) << rme96->capture_frlog != 1071 rme96->playback_periodsize) 1072 { 1073 spin_unlock_irq(&rme96->lock); 1074 return -EBUSY; 1075 } 1076 } 1077 rme96->capture_periodsize = 1078 params_period_size(params) << rme96->capture_frlog; 1079 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize); 1080 spin_unlock_irq(&rme96->lock); 1081 1082 return 0; 1083 } 1084 1085 static void 1086 snd_rme96_playback_start(rme96_t *rme96, 1087 int from_pause) 1088 { 1089 if (!from_pause) { 1090 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1091 } 1092 1093 rme96->wcreg |= RME96_WCR_START; 1094 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1095 } 1096 1097 static void 1098 snd_rme96_capture_start(rme96_t *rme96, 1099 int from_pause) 1100 { 1101 if (!from_pause) { 1102 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1103 } 1104 1105 rme96->wcreg |= RME96_WCR_START_2; 1106 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1107 } 1108 1109 static void 1110 snd_rme96_playback_stop(rme96_t *rme96) 1111 { 1112 /* 1113 * Check if there is an unconfirmed IRQ, if so confirm it, or else 1114 * the hardware will not stop generating interrupts 1115 */ 1116 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1117 if (rme96->rcreg & RME96_RCR_IRQ) { 1118 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1119 } 1120 rme96->wcreg &= ~RME96_WCR_START; 1121 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1122 } 1123 1124 static void 1125 snd_rme96_capture_stop(rme96_t *rme96) 1126 { 1127 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1128 if (rme96->rcreg & RME96_RCR_IRQ_2) { 1129 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1130 } 1131 rme96->wcreg &= ~RME96_WCR_START_2; 1132 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1133 } 1134 1135 static irqreturn_t 1136 snd_rme96_interrupt(int irq, 1137 void *dev_id, 1138 struct pt_regs *regs) 1139 { 1140 rme96_t *rme96 = (rme96_t *)dev_id; 1141 1142 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1143 /* fastpath out, to ease interrupt sharing */ 1144 if (!((rme96->rcreg & RME96_RCR_IRQ) || 1145 (rme96->rcreg & RME96_RCR_IRQ_2))) 1146 { 1147 return IRQ_NONE; 1148 } 1149 1150 if (rme96->rcreg & RME96_RCR_IRQ) { 1151 /* playback */ 1152 snd_pcm_period_elapsed(rme96->playback_substream); 1153 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1154 } 1155 if (rme96->rcreg & RME96_RCR_IRQ_2) { 1156 /* capture */ 1157 snd_pcm_period_elapsed(rme96->capture_substream); 1158 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1159 } 1160 return IRQ_HANDLED; 1161 } 1162 1163 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE }; 1164 1165 static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = { 1166 .count = ARRAY_SIZE(period_bytes), 1167 .list = period_bytes, 1168 .mask = 0 1169 }; 1170 1171 static int 1172 snd_rme96_playback_spdif_open(snd_pcm_substream_t *substream) 1173 { 1174 int rate, dummy; 1175 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1176 snd_pcm_runtime_t *runtime = substream->runtime; 1177 1178 snd_pcm_set_sync(substream); 1179 1180 spin_lock_irq(&rme96->lock); 1181 if (rme96->playback_substream != NULL) { 1182 spin_unlock_irq(&rme96->lock); 1183 return -EBUSY; 1184 } 1185 rme96->wcreg &= ~RME96_WCR_ADAT; 1186 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1187 rme96->playback_substream = substream; 1188 spin_unlock_irq(&rme96->lock); 1189 1190 runtime->hw = snd_rme96_playback_spdif_info; 1191 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1192 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1193 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 1194 { 1195 /* slave clock */ 1196 runtime->hw.rates = snd_rme96_ratecode(rate); 1197 runtime->hw.rate_min = rate; 1198 runtime->hw.rate_max = rate; 1199 } 1200 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE); 1201 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes); 1202 1203 rme96->wcreg_spdif_stream = rme96->wcreg_spdif; 1204 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1205 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1206 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1207 return 0; 1208 } 1209 1210 static int 1211 snd_rme96_capture_spdif_open(snd_pcm_substream_t *substream) 1212 { 1213 int isadat, rate; 1214 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1215 snd_pcm_runtime_t *runtime = substream->runtime; 1216 1217 snd_pcm_set_sync(substream); 1218 1219 runtime->hw = snd_rme96_capture_spdif_info; 1220 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1221 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) 1222 { 1223 if (isadat) { 1224 return -EIO; 1225 } 1226 runtime->hw.rates = snd_rme96_ratecode(rate); 1227 runtime->hw.rate_min = rate; 1228 runtime->hw.rate_max = rate; 1229 } 1230 1231 spin_lock_irq(&rme96->lock); 1232 if (rme96->capture_substream != NULL) { 1233 spin_unlock_irq(&rme96->lock); 1234 return -EBUSY; 1235 } 1236 rme96->capture_substream = substream; 1237 spin_unlock_irq(&rme96->lock); 1238 1239 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE); 1240 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes); 1241 1242 return 0; 1243 } 1244 1245 static int 1246 snd_rme96_playback_adat_open(snd_pcm_substream_t *substream) 1247 { 1248 int rate, dummy; 1249 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1250 snd_pcm_runtime_t *runtime = substream->runtime; 1251 1252 snd_pcm_set_sync(substream); 1253 1254 spin_lock_irq(&rme96->lock); 1255 if (rme96->playback_substream != NULL) { 1256 spin_unlock_irq(&rme96->lock); 1257 return -EBUSY; 1258 } 1259 rme96->wcreg |= RME96_WCR_ADAT; 1260 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1261 rme96->playback_substream = substream; 1262 spin_unlock_irq(&rme96->lock); 1263 1264 runtime->hw = snd_rme96_playback_adat_info; 1265 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1266 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1267 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 1268 { 1269 /* slave clock */ 1270 runtime->hw.rates = snd_rme96_ratecode(rate); 1271 runtime->hw.rate_min = rate; 1272 runtime->hw.rate_max = rate; 1273 } 1274 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE); 1275 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes); 1276 return 0; 1277 } 1278 1279 static int 1280 snd_rme96_capture_adat_open(snd_pcm_substream_t *substream) 1281 { 1282 int isadat, rate; 1283 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1284 snd_pcm_runtime_t *runtime = substream->runtime; 1285 1286 snd_pcm_set_sync(substream); 1287 1288 runtime->hw = snd_rme96_capture_adat_info; 1289 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1290 /* makes no sense to use analog input. Note that analog 1291 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */ 1292 return -EIO; 1293 } 1294 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { 1295 if (!isadat) { 1296 return -EIO; 1297 } 1298 runtime->hw.rates = snd_rme96_ratecode(rate); 1299 runtime->hw.rate_min = rate; 1300 runtime->hw.rate_max = rate; 1301 } 1302 1303 spin_lock_irq(&rme96->lock); 1304 if (rme96->capture_substream != NULL) { 1305 spin_unlock_irq(&rme96->lock); 1306 return -EBUSY; 1307 } 1308 rme96->capture_substream = substream; 1309 spin_unlock_irq(&rme96->lock); 1310 1311 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE); 1312 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes); 1313 return 0; 1314 } 1315 1316 static int 1317 snd_rme96_playback_close(snd_pcm_substream_t *substream) 1318 { 1319 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1320 int spdif = 0; 1321 1322 spin_lock_irq(&rme96->lock); 1323 if (RME96_ISPLAYING(rme96)) { 1324 snd_rme96_playback_stop(rme96); 1325 } 1326 rme96->playback_substream = NULL; 1327 rme96->playback_periodsize = 0; 1328 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; 1329 spin_unlock_irq(&rme96->lock); 1330 if (spdif) { 1331 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1332 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1333 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1334 } 1335 return 0; 1336 } 1337 1338 static int 1339 snd_rme96_capture_close(snd_pcm_substream_t *substream) 1340 { 1341 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1342 1343 spin_lock_irq(&rme96->lock); 1344 if (RME96_ISRECORDING(rme96)) { 1345 snd_rme96_capture_stop(rme96); 1346 } 1347 rme96->capture_substream = NULL; 1348 rme96->capture_periodsize = 0; 1349 spin_unlock_irq(&rme96->lock); 1350 return 0; 1351 } 1352 1353 static int 1354 snd_rme96_playback_prepare(snd_pcm_substream_t *substream) 1355 { 1356 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1357 1358 spin_lock_irq(&rme96->lock); 1359 if (RME96_ISPLAYING(rme96)) { 1360 snd_rme96_playback_stop(rme96); 1361 } 1362 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1363 spin_unlock_irq(&rme96->lock); 1364 return 0; 1365 } 1366 1367 static int 1368 snd_rme96_capture_prepare(snd_pcm_substream_t *substream) 1369 { 1370 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1371 1372 spin_lock_irq(&rme96->lock); 1373 if (RME96_ISRECORDING(rme96)) { 1374 snd_rme96_capture_stop(rme96); 1375 } 1376 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1377 spin_unlock_irq(&rme96->lock); 1378 return 0; 1379 } 1380 1381 static int 1382 snd_rme96_playback_trigger(snd_pcm_substream_t *substream, 1383 int cmd) 1384 { 1385 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1386 1387 switch (cmd) { 1388 case SNDRV_PCM_TRIGGER_START: 1389 if (!RME96_ISPLAYING(rme96)) { 1390 if (substream != rme96->playback_substream) { 1391 return -EBUSY; 1392 } 1393 snd_rme96_playback_start(rme96, 0); 1394 } 1395 break; 1396 1397 case SNDRV_PCM_TRIGGER_STOP: 1398 if (RME96_ISPLAYING(rme96)) { 1399 if (substream != rme96->playback_substream) { 1400 return -EBUSY; 1401 } 1402 snd_rme96_playback_stop(rme96); 1403 } 1404 break; 1405 1406 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1407 if (RME96_ISPLAYING(rme96)) { 1408 snd_rme96_playback_stop(rme96); 1409 } 1410 break; 1411 1412 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1413 if (!RME96_ISPLAYING(rme96)) { 1414 snd_rme96_playback_start(rme96, 1); 1415 } 1416 break; 1417 1418 default: 1419 return -EINVAL; 1420 } 1421 return 0; 1422 } 1423 1424 static int 1425 snd_rme96_capture_trigger(snd_pcm_substream_t *substream, 1426 int cmd) 1427 { 1428 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1429 1430 switch (cmd) { 1431 case SNDRV_PCM_TRIGGER_START: 1432 if (!RME96_ISRECORDING(rme96)) { 1433 if (substream != rme96->capture_substream) { 1434 return -EBUSY; 1435 } 1436 snd_rme96_capture_start(rme96, 0); 1437 } 1438 break; 1439 1440 case SNDRV_PCM_TRIGGER_STOP: 1441 if (RME96_ISRECORDING(rme96)) { 1442 if (substream != rme96->capture_substream) { 1443 return -EBUSY; 1444 } 1445 snd_rme96_capture_stop(rme96); 1446 } 1447 break; 1448 1449 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1450 if (RME96_ISRECORDING(rme96)) { 1451 snd_rme96_capture_stop(rme96); 1452 } 1453 break; 1454 1455 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1456 if (!RME96_ISRECORDING(rme96)) { 1457 snd_rme96_capture_start(rme96, 1); 1458 } 1459 break; 1460 1461 default: 1462 return -EINVAL; 1463 } 1464 1465 return 0; 1466 } 1467 1468 static snd_pcm_uframes_t 1469 snd_rme96_playback_pointer(snd_pcm_substream_t *substream) 1470 { 1471 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1472 return snd_rme96_playback_ptr(rme96); 1473 } 1474 1475 static snd_pcm_uframes_t 1476 snd_rme96_capture_pointer(snd_pcm_substream_t *substream) 1477 { 1478 rme96_t *rme96 = snd_pcm_substream_chip(substream); 1479 return snd_rme96_capture_ptr(rme96); 1480 } 1481 1482 static snd_pcm_ops_t snd_rme96_playback_spdif_ops = { 1483 .open = snd_rme96_playback_spdif_open, 1484 .close = snd_rme96_playback_close, 1485 .ioctl = snd_pcm_lib_ioctl, 1486 .hw_params = snd_rme96_playback_hw_params, 1487 .prepare = snd_rme96_playback_prepare, 1488 .trigger = snd_rme96_playback_trigger, 1489 .pointer = snd_rme96_playback_pointer, 1490 .copy = snd_rme96_playback_copy, 1491 .silence = snd_rme96_playback_silence, 1492 .mmap = snd_pcm_lib_mmap_iomem, 1493 }; 1494 1495 static snd_pcm_ops_t snd_rme96_capture_spdif_ops = { 1496 .open = snd_rme96_capture_spdif_open, 1497 .close = snd_rme96_capture_close, 1498 .ioctl = snd_pcm_lib_ioctl, 1499 .hw_params = snd_rme96_capture_hw_params, 1500 .prepare = snd_rme96_capture_prepare, 1501 .trigger = snd_rme96_capture_trigger, 1502 .pointer = snd_rme96_capture_pointer, 1503 .copy = snd_rme96_capture_copy, 1504 .mmap = snd_pcm_lib_mmap_iomem, 1505 }; 1506 1507 static snd_pcm_ops_t snd_rme96_playback_adat_ops = { 1508 .open = snd_rme96_playback_adat_open, 1509 .close = snd_rme96_playback_close, 1510 .ioctl = snd_pcm_lib_ioctl, 1511 .hw_params = snd_rme96_playback_hw_params, 1512 .prepare = snd_rme96_playback_prepare, 1513 .trigger = snd_rme96_playback_trigger, 1514 .pointer = snd_rme96_playback_pointer, 1515 .copy = snd_rme96_playback_copy, 1516 .silence = snd_rme96_playback_silence, 1517 .mmap = snd_pcm_lib_mmap_iomem, 1518 }; 1519 1520 static snd_pcm_ops_t snd_rme96_capture_adat_ops = { 1521 .open = snd_rme96_capture_adat_open, 1522 .close = snd_rme96_capture_close, 1523 .ioctl = snd_pcm_lib_ioctl, 1524 .hw_params = snd_rme96_capture_hw_params, 1525 .prepare = snd_rme96_capture_prepare, 1526 .trigger = snd_rme96_capture_trigger, 1527 .pointer = snd_rme96_capture_pointer, 1528 .copy = snd_rme96_capture_copy, 1529 .mmap = snd_pcm_lib_mmap_iomem, 1530 }; 1531 1532 static void 1533 snd_rme96_free(void *private_data) 1534 { 1535 rme96_t *rme96 = (rme96_t *)private_data; 1536 1537 if (rme96 == NULL) { 1538 return; 1539 } 1540 if (rme96->irq >= 0) { 1541 snd_rme96_playback_stop(rme96); 1542 snd_rme96_capture_stop(rme96); 1543 rme96->areg &= ~RME96_AR_DAC_EN; 1544 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1545 free_irq(rme96->irq, (void *)rme96); 1546 rme96->irq = -1; 1547 } 1548 if (rme96->iobase) { 1549 iounmap(rme96->iobase); 1550 rme96->iobase = NULL; 1551 } 1552 if (rme96->port) { 1553 pci_release_regions(rme96->pci); 1554 rme96->port = 0; 1555 } 1556 pci_disable_device(rme96->pci); 1557 } 1558 1559 static void 1560 snd_rme96_free_spdif_pcm(snd_pcm_t *pcm) 1561 { 1562 rme96_t *rme96 = (rme96_t *) pcm->private_data; 1563 rme96->spdif_pcm = NULL; 1564 } 1565 1566 static void 1567 snd_rme96_free_adat_pcm(snd_pcm_t *pcm) 1568 { 1569 rme96_t *rme96 = (rme96_t *) pcm->private_data; 1570 rme96->adat_pcm = NULL; 1571 } 1572 1573 static int __devinit 1574 snd_rme96_create(rme96_t *rme96) 1575 { 1576 struct pci_dev *pci = rme96->pci; 1577 int err; 1578 1579 rme96->irq = -1; 1580 spin_lock_init(&rme96->lock); 1581 1582 if ((err = pci_enable_device(pci)) < 0) 1583 return err; 1584 1585 if ((err = pci_request_regions(pci, "RME96")) < 0) 1586 return err; 1587 rme96->port = pci_resource_start(rme96->pci, 0); 1588 1589 if (request_irq(pci->irq, snd_rme96_interrupt, SA_INTERRUPT|SA_SHIRQ, "RME96", (void *)rme96)) { 1590 snd_printk("unable to grab IRQ %d\n", pci->irq); 1591 return -EBUSY; 1592 } 1593 rme96->irq = pci->irq; 1594 1595 if ((rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) { 1596 snd_printk("unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1); 1597 return -ENOMEM; 1598 } 1599 1600 /* read the card's revision number */ 1601 pci_read_config_byte(pci, 8, &rme96->rev); 1602 1603 /* set up ALSA pcm device for S/PDIF */ 1604 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0, 1605 1, 1, &rme96->spdif_pcm)) < 0) 1606 { 1607 return err; 1608 } 1609 rme96->spdif_pcm->private_data = rme96; 1610 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm; 1611 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958"); 1612 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops); 1613 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops); 1614 1615 rme96->spdif_pcm->info_flags = 0; 1616 1617 /* set up ALSA pcm device for ADAT */ 1618 if (pci->device == PCI_DEVICE_ID_DIGI96) { 1619 /* ADAT is not available on the base model */ 1620 rme96->adat_pcm = NULL; 1621 } else { 1622 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1, 1623 1, 1, &rme96->adat_pcm)) < 0) 1624 { 1625 return err; 1626 } 1627 rme96->adat_pcm->private_data = rme96; 1628 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm; 1629 strcpy(rme96->adat_pcm->name, "Digi96 ADAT"); 1630 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops); 1631 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops); 1632 1633 rme96->adat_pcm->info_flags = 0; 1634 } 1635 1636 rme96->playback_periodsize = 0; 1637 rme96->capture_periodsize = 0; 1638 1639 /* make sure playback/capture is stopped, if by some reason active */ 1640 snd_rme96_playback_stop(rme96); 1641 snd_rme96_capture_stop(rme96); 1642 1643 /* set default values in registers */ 1644 rme96->wcreg = 1645 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */ 1646 RME96_WCR_SEL | /* normal playback */ 1647 RME96_WCR_MASTER | /* set to master clock mode */ 1648 RME96_WCR_INP_0; /* set coaxial input */ 1649 1650 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */ 1651 1652 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1653 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1654 1655 /* reset the ADC */ 1656 writel(rme96->areg | RME96_AR_PD2, 1657 rme96->iobase + RME96_IO_ADDITIONAL_REG); 1658 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1659 1660 /* reset and enable the DAC (order is important). */ 1661 snd_rme96_reset_dac(rme96); 1662 rme96->areg |= RME96_AR_DAC_EN; 1663 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1664 1665 /* reset playback and record buffer pointers */ 1666 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1667 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1668 1669 /* reset volume */ 1670 rme96->vol[0] = rme96->vol[1] = 0; 1671 if (RME96_HAS_ANALOG_OUT(rme96)) { 1672 snd_rme96_apply_dac_volume(rme96); 1673 } 1674 1675 /* init switch interface */ 1676 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) { 1677 return err; 1678 } 1679 1680 /* init proc interface */ 1681 snd_rme96_proc_init(rme96); 1682 1683 return 0; 1684 } 1685 1686 /* 1687 * proc interface 1688 */ 1689 1690 static void 1691 snd_rme96_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer) 1692 { 1693 int n; 1694 rme96_t *rme96 = (rme96_t *)entry->private_data; 1695 1696 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1697 1698 snd_iprintf(buffer, rme96->card->longname); 1699 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1); 1700 1701 snd_iprintf(buffer, "\nGeneral settings\n"); 1702 if (rme96->wcreg & RME96_WCR_IDIS) { 1703 snd_iprintf(buffer, " period size: N/A (interrupts " 1704 "disabled)\n"); 1705 } else if (rme96->wcreg & RME96_WCR_ISEL) { 1706 snd_iprintf(buffer, " period size: 2048 bytes\n"); 1707 } else { 1708 snd_iprintf(buffer, " period size: 8192 bytes\n"); 1709 } 1710 snd_iprintf(buffer, "\nInput settings\n"); 1711 switch (snd_rme96_getinputtype(rme96)) { 1712 case RME96_INPUT_OPTICAL: 1713 snd_iprintf(buffer, " input: optical"); 1714 break; 1715 case RME96_INPUT_COAXIAL: 1716 snd_iprintf(buffer, " input: coaxial"); 1717 break; 1718 case RME96_INPUT_INTERNAL: 1719 snd_iprintf(buffer, " input: internal"); 1720 break; 1721 case RME96_INPUT_XLR: 1722 snd_iprintf(buffer, " input: XLR"); 1723 break; 1724 case RME96_INPUT_ANALOG: 1725 snd_iprintf(buffer, " input: analog"); 1726 break; 1727 } 1728 if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1729 snd_iprintf(buffer, "\n sample rate: no valid signal\n"); 1730 } else { 1731 if (n) { 1732 snd_iprintf(buffer, " (8 channels)\n"); 1733 } else { 1734 snd_iprintf(buffer, " (2 channels)\n"); 1735 } 1736 snd_iprintf(buffer, " sample rate: %d Hz\n", 1737 snd_rme96_capture_getrate(rme96, &n)); 1738 } 1739 if (rme96->wcreg & RME96_WCR_MODE24_2) { 1740 snd_iprintf(buffer, " sample format: 24 bit\n"); 1741 } else { 1742 snd_iprintf(buffer, " sample format: 16 bit\n"); 1743 } 1744 1745 snd_iprintf(buffer, "\nOutput settings\n"); 1746 if (rme96->wcreg & RME96_WCR_SEL) { 1747 snd_iprintf(buffer, " output signal: normal playback\n"); 1748 } else { 1749 snd_iprintf(buffer, " output signal: same as input\n"); 1750 } 1751 snd_iprintf(buffer, " sample rate: %d Hz\n", 1752 snd_rme96_playback_getrate(rme96)); 1753 if (rme96->wcreg & RME96_WCR_MODE24) { 1754 snd_iprintf(buffer, " sample format: 24 bit\n"); 1755 } else { 1756 snd_iprintf(buffer, " sample format: 16 bit\n"); 1757 } 1758 if (rme96->areg & RME96_AR_WSEL) { 1759 snd_iprintf(buffer, " sample clock source: word clock\n"); 1760 } else if (rme96->wcreg & RME96_WCR_MASTER) { 1761 snd_iprintf(buffer, " sample clock source: internal\n"); 1762 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1763 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n"); 1764 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1765 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n"); 1766 } else { 1767 snd_iprintf(buffer, " sample clock source: autosync\n"); 1768 } 1769 if (rme96->wcreg & RME96_WCR_PRO) { 1770 snd_iprintf(buffer, " format: AES/EBU (professional)\n"); 1771 } else { 1772 snd_iprintf(buffer, " format: IEC958 (consumer)\n"); 1773 } 1774 if (rme96->wcreg & RME96_WCR_EMP) { 1775 snd_iprintf(buffer, " emphasis: on\n"); 1776 } else { 1777 snd_iprintf(buffer, " emphasis: off\n"); 1778 } 1779 if (rme96->wcreg & RME96_WCR_DOLBY) { 1780 snd_iprintf(buffer, " non-audio (dolby): on\n"); 1781 } else { 1782 snd_iprintf(buffer, " non-audio (dolby): off\n"); 1783 } 1784 if (RME96_HAS_ANALOG_IN(rme96)) { 1785 snd_iprintf(buffer, "\nAnalog output settings\n"); 1786 switch (snd_rme96_getmontracks(rme96)) { 1787 case RME96_MONITOR_TRACKS_1_2: 1788 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n"); 1789 break; 1790 case RME96_MONITOR_TRACKS_3_4: 1791 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n"); 1792 break; 1793 case RME96_MONITOR_TRACKS_5_6: 1794 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n"); 1795 break; 1796 case RME96_MONITOR_TRACKS_7_8: 1797 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n"); 1798 break; 1799 } 1800 switch (snd_rme96_getattenuation(rme96)) { 1801 case RME96_ATTENUATION_0: 1802 snd_iprintf(buffer, " attenuation: 0 dB\n"); 1803 break; 1804 case RME96_ATTENUATION_6: 1805 snd_iprintf(buffer, " attenuation: -6 dB\n"); 1806 break; 1807 case RME96_ATTENUATION_12: 1808 snd_iprintf(buffer, " attenuation: -12 dB\n"); 1809 break; 1810 case RME96_ATTENUATION_18: 1811 snd_iprintf(buffer, " attenuation: -18 dB\n"); 1812 break; 1813 } 1814 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]); 1815 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]); 1816 } 1817 } 1818 1819 static void __devinit 1820 snd_rme96_proc_init(rme96_t *rme96) 1821 { 1822 snd_info_entry_t *entry; 1823 1824 if (! snd_card_proc_new(rme96->card, "rme96", &entry)) 1825 snd_info_set_text_ops(entry, rme96, 1024, snd_rme96_proc_read); 1826 } 1827 1828 /* 1829 * control interface 1830 */ 1831 1832 static int 1833 snd_rme96_info_loopback_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1834 { 1835 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1836 uinfo->count = 1; 1837 uinfo->value.integer.min = 0; 1838 uinfo->value.integer.max = 1; 1839 return 0; 1840 } 1841 static int 1842 snd_rme96_get_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1843 { 1844 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 1845 1846 spin_lock_irq(&rme96->lock); 1847 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; 1848 spin_unlock_irq(&rme96->lock); 1849 return 0; 1850 } 1851 static int 1852 snd_rme96_put_loopback_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1853 { 1854 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 1855 unsigned int val; 1856 int change; 1857 1858 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; 1859 spin_lock_irq(&rme96->lock); 1860 val = (rme96->wcreg & ~RME96_WCR_SEL) | val; 1861 change = val != rme96->wcreg; 1862 rme96->wcreg = val; 1863 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1864 spin_unlock_irq(&rme96->lock); 1865 return change; 1866 } 1867 1868 static int 1869 snd_rme96_info_inputtype_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1870 { 1871 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" }; 1872 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 1873 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] }; 1874 1875 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1876 uinfo->count = 1; 1877 switch (rme96->pci->device) { 1878 case PCI_DEVICE_ID_DIGI96: 1879 case PCI_DEVICE_ID_DIGI96_8: 1880 uinfo->value.enumerated.items = 3; 1881 break; 1882 case PCI_DEVICE_ID_DIGI96_8_PRO: 1883 uinfo->value.enumerated.items = 4; 1884 break; 1885 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST: 1886 if (rme96->rev > 4) { 1887 /* PST */ 1888 uinfo->value.enumerated.items = 4; 1889 texts[3] = _texts[4]; /* Analog instead of XLR */ 1890 } else { 1891 /* PAD */ 1892 uinfo->value.enumerated.items = 5; 1893 } 1894 break; 1895 default: 1896 snd_BUG(); 1897 break; 1898 } 1899 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) { 1900 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1901 } 1902 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1903 return 0; 1904 } 1905 static int 1906 snd_rme96_get_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1907 { 1908 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 1909 unsigned int items = 3; 1910 1911 spin_lock_irq(&rme96->lock); 1912 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96); 1913 1914 switch (rme96->pci->device) { 1915 case PCI_DEVICE_ID_DIGI96: 1916 case PCI_DEVICE_ID_DIGI96_8: 1917 items = 3; 1918 break; 1919 case PCI_DEVICE_ID_DIGI96_8_PRO: 1920 items = 4; 1921 break; 1922 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST: 1923 if (rme96->rev > 4) { 1924 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */ 1925 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) { 1926 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR; 1927 } 1928 items = 4; 1929 } else { 1930 items = 5; 1931 } 1932 break; 1933 default: 1934 snd_BUG(); 1935 break; 1936 } 1937 if (ucontrol->value.enumerated.item[0] >= items) { 1938 ucontrol->value.enumerated.item[0] = items - 1; 1939 } 1940 1941 spin_unlock_irq(&rme96->lock); 1942 return 0; 1943 } 1944 static int 1945 snd_rme96_put_inputtype_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1946 { 1947 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 1948 unsigned int val; 1949 int change, items = 3; 1950 1951 switch (rme96->pci->device) { 1952 case PCI_DEVICE_ID_DIGI96: 1953 case PCI_DEVICE_ID_DIGI96_8: 1954 items = 3; 1955 break; 1956 case PCI_DEVICE_ID_DIGI96_8_PRO: 1957 items = 4; 1958 break; 1959 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST: 1960 if (rme96->rev > 4) { 1961 items = 4; 1962 } else { 1963 items = 5; 1964 } 1965 break; 1966 default: 1967 snd_BUG(); 1968 break; 1969 } 1970 val = ucontrol->value.enumerated.item[0] % items; 1971 1972 /* special case for PST */ 1973 if (rme96->pci->device == PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST && rme96->rev > 4) { 1974 if (val == RME96_INPUT_XLR) { 1975 val = RME96_INPUT_ANALOG; 1976 } 1977 } 1978 1979 spin_lock_irq(&rme96->lock); 1980 change = (int)val != snd_rme96_getinputtype(rme96); 1981 snd_rme96_setinputtype(rme96, val); 1982 spin_unlock_irq(&rme96->lock); 1983 return change; 1984 } 1985 1986 static int 1987 snd_rme96_info_clockmode_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1988 { 1989 static char *texts[3] = { "AutoSync", "Internal", "Word" }; 1990 1991 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1992 uinfo->count = 1; 1993 uinfo->value.enumerated.items = 3; 1994 if (uinfo->value.enumerated.item > 2) { 1995 uinfo->value.enumerated.item = 2; 1996 } 1997 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1998 return 0; 1999 } 2000 static int 2001 snd_rme96_get_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2002 { 2003 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2004 2005 spin_lock_irq(&rme96->lock); 2006 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96); 2007 spin_unlock_irq(&rme96->lock); 2008 return 0; 2009 } 2010 static int 2011 snd_rme96_put_clockmode_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2012 { 2013 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2014 unsigned int val; 2015 int change; 2016 2017 val = ucontrol->value.enumerated.item[0] % 3; 2018 spin_lock_irq(&rme96->lock); 2019 change = (int)val != snd_rme96_getclockmode(rme96); 2020 snd_rme96_setclockmode(rme96, val); 2021 spin_unlock_irq(&rme96->lock); 2022 return change; 2023 } 2024 2025 static int 2026 snd_rme96_info_attenuation_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2027 { 2028 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" }; 2029 2030 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2031 uinfo->count = 1; 2032 uinfo->value.enumerated.items = 4; 2033 if (uinfo->value.enumerated.item > 3) { 2034 uinfo->value.enumerated.item = 3; 2035 } 2036 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2037 return 0; 2038 } 2039 static int 2040 snd_rme96_get_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2041 { 2042 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2043 2044 spin_lock_irq(&rme96->lock); 2045 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96); 2046 spin_unlock_irq(&rme96->lock); 2047 return 0; 2048 } 2049 static int 2050 snd_rme96_put_attenuation_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2051 { 2052 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2053 unsigned int val; 2054 int change; 2055 2056 val = ucontrol->value.enumerated.item[0] % 4; 2057 spin_lock_irq(&rme96->lock); 2058 2059 change = (int)val != snd_rme96_getattenuation(rme96); 2060 snd_rme96_setattenuation(rme96, val); 2061 spin_unlock_irq(&rme96->lock); 2062 return change; 2063 } 2064 2065 static int 2066 snd_rme96_info_montracks_control(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2067 { 2068 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" }; 2069 2070 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2071 uinfo->count = 1; 2072 uinfo->value.enumerated.items = 4; 2073 if (uinfo->value.enumerated.item > 3) { 2074 uinfo->value.enumerated.item = 3; 2075 } 2076 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2077 return 0; 2078 } 2079 static int 2080 snd_rme96_get_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2081 { 2082 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2083 2084 spin_lock_irq(&rme96->lock); 2085 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96); 2086 spin_unlock_irq(&rme96->lock); 2087 return 0; 2088 } 2089 static int 2090 snd_rme96_put_montracks_control(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2091 { 2092 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2093 unsigned int val; 2094 int change; 2095 2096 val = ucontrol->value.enumerated.item[0] % 4; 2097 spin_lock_irq(&rme96->lock); 2098 change = (int)val != snd_rme96_getmontracks(rme96); 2099 snd_rme96_setmontracks(rme96, val); 2100 spin_unlock_irq(&rme96->lock); 2101 return change; 2102 } 2103 2104 static u32 snd_rme96_convert_from_aes(snd_aes_iec958_t *aes) 2105 { 2106 u32 val = 0; 2107 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; 2108 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; 2109 if (val & RME96_WCR_PRO) 2110 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2111 else 2112 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2113 return val; 2114 } 2115 2116 static void snd_rme96_convert_to_aes(snd_aes_iec958_t *aes, u32 val) 2117 { 2118 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | 2119 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); 2120 if (val & RME96_WCR_PRO) 2121 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 2122 else 2123 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 2124 } 2125 2126 static int snd_rme96_control_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2127 { 2128 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2129 uinfo->count = 1; 2130 return 0; 2131 } 2132 2133 static int snd_rme96_control_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2134 { 2135 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2136 2137 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif); 2138 return 0; 2139 } 2140 2141 static int snd_rme96_control_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2142 { 2143 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2144 int change; 2145 u32 val; 2146 2147 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2148 spin_lock_irq(&rme96->lock); 2149 change = val != rme96->wcreg_spdif; 2150 rme96->wcreg_spdif = val; 2151 spin_unlock_irq(&rme96->lock); 2152 return change; 2153 } 2154 2155 static int snd_rme96_control_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2156 { 2157 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2158 uinfo->count = 1; 2159 return 0; 2160 } 2161 2162 static int snd_rme96_control_spdif_stream_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2163 { 2164 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2165 2166 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream); 2167 return 0; 2168 } 2169 2170 static int snd_rme96_control_spdif_stream_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2171 { 2172 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2173 int change; 2174 u32 val; 2175 2176 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2177 spin_lock_irq(&rme96->lock); 2178 change = val != rme96->wcreg_spdif_stream; 2179 rme96->wcreg_spdif_stream = val; 2180 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 2181 rme96->wcreg |= val; 2182 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 2183 spin_unlock_irq(&rme96->lock); 2184 return change; 2185 } 2186 2187 static int snd_rme96_control_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2188 { 2189 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2190 uinfo->count = 1; 2191 return 0; 2192 } 2193 2194 static int snd_rme96_control_spdif_mask_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2195 { 2196 ucontrol->value.iec958.status[0] = kcontrol->private_value; 2197 return 0; 2198 } 2199 2200 static int 2201 snd_rme96_dac_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 2202 { 2203 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2204 2205 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2206 uinfo->count = 2; 2207 uinfo->value.integer.min = 0; 2208 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96); 2209 return 0; 2210 } 2211 2212 static int 2213 snd_rme96_dac_volume_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u) 2214 { 2215 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2216 2217 spin_lock_irq(&rme96->lock); 2218 u->value.integer.value[0] = rme96->vol[0]; 2219 u->value.integer.value[1] = rme96->vol[1]; 2220 spin_unlock_irq(&rme96->lock); 2221 2222 return 0; 2223 } 2224 2225 static int 2226 snd_rme96_dac_volume_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *u) 2227 { 2228 rme96_t *rme96 = snd_kcontrol_chip(kcontrol); 2229 int change = 0; 2230 2231 if (!RME96_HAS_ANALOG_OUT(rme96)) { 2232 return -EINVAL; 2233 } 2234 spin_lock_irq(&rme96->lock); 2235 if (u->value.integer.value[0] != rme96->vol[0]) { 2236 rme96->vol[0] = u->value.integer.value[0]; 2237 change = 1; 2238 } 2239 if (u->value.integer.value[1] != rme96->vol[1]) { 2240 rme96->vol[1] = u->value.integer.value[1]; 2241 change = 1; 2242 } 2243 if (change) { 2244 snd_rme96_apply_dac_volume(rme96); 2245 } 2246 spin_unlock_irq(&rme96->lock); 2247 2248 return change; 2249 } 2250 2251 static snd_kcontrol_new_t snd_rme96_controls[] = { 2252 { 2253 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2254 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2255 .info = snd_rme96_control_spdif_info, 2256 .get = snd_rme96_control_spdif_get, 2257 .put = snd_rme96_control_spdif_put 2258 }, 2259 { 2260 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2261 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2262 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2263 .info = snd_rme96_control_spdif_stream_info, 2264 .get = snd_rme96_control_spdif_stream_get, 2265 .put = snd_rme96_control_spdif_stream_put 2266 }, 2267 { 2268 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2269 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2270 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 2271 .info = snd_rme96_control_spdif_mask_info, 2272 .get = snd_rme96_control_spdif_mask_get, 2273 .private_value = IEC958_AES0_NONAUDIO | 2274 IEC958_AES0_PROFESSIONAL | 2275 IEC958_AES0_CON_EMPHASIS 2276 }, 2277 { 2278 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2279 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2280 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 2281 .info = snd_rme96_control_spdif_mask_info, 2282 .get = snd_rme96_control_spdif_mask_get, 2283 .private_value = IEC958_AES0_NONAUDIO | 2284 IEC958_AES0_PROFESSIONAL | 2285 IEC958_AES0_PRO_EMPHASIS 2286 }, 2287 { 2288 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2289 .name = "Input Connector", 2290 .info = snd_rme96_info_inputtype_control, 2291 .get = snd_rme96_get_inputtype_control, 2292 .put = snd_rme96_put_inputtype_control 2293 }, 2294 { 2295 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2296 .name = "Loopback Input", 2297 .info = snd_rme96_info_loopback_control, 2298 .get = snd_rme96_get_loopback_control, 2299 .put = snd_rme96_put_loopback_control 2300 }, 2301 { 2302 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2303 .name = "Sample Clock Source", 2304 .info = snd_rme96_info_clockmode_control, 2305 .get = snd_rme96_get_clockmode_control, 2306 .put = snd_rme96_put_clockmode_control 2307 }, 2308 { 2309 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2310 .name = "Monitor Tracks", 2311 .info = snd_rme96_info_montracks_control, 2312 .get = snd_rme96_get_montracks_control, 2313 .put = snd_rme96_put_montracks_control 2314 }, 2315 { 2316 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2317 .name = "Attenuation", 2318 .info = snd_rme96_info_attenuation_control, 2319 .get = snd_rme96_get_attenuation_control, 2320 .put = snd_rme96_put_attenuation_control 2321 }, 2322 { 2323 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2324 .name = "DAC Playback Volume", 2325 .info = snd_rme96_dac_volume_info, 2326 .get = snd_rme96_dac_volume_get, 2327 .put = snd_rme96_dac_volume_put 2328 } 2329 }; 2330 2331 static int 2332 snd_rme96_create_switches(snd_card_t *card, 2333 rme96_t *rme96) 2334 { 2335 int idx, err; 2336 snd_kcontrol_t *kctl; 2337 2338 for (idx = 0; idx < 7; idx++) { 2339 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) 2340 return err; 2341 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 2342 rme96->spdif_ctl = kctl; 2343 } 2344 2345 if (RME96_HAS_ANALOG_OUT(rme96)) { 2346 for (idx = 7; idx < 10; idx++) 2347 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) 2348 return err; 2349 } 2350 2351 return 0; 2352 } 2353 2354 /* 2355 * Card initialisation 2356 */ 2357 2358 static void snd_rme96_card_free(snd_card_t *card) 2359 { 2360 snd_rme96_free(card->private_data); 2361 } 2362 2363 static int __devinit 2364 snd_rme96_probe(struct pci_dev *pci, 2365 const struct pci_device_id *pci_id) 2366 { 2367 static int dev; 2368 rme96_t *rme96; 2369 snd_card_t *card; 2370 int err; 2371 u8 val; 2372 2373 if (dev >= SNDRV_CARDS) { 2374 return -ENODEV; 2375 } 2376 if (!enable[dev]) { 2377 dev++; 2378 return -ENOENT; 2379 } 2380 if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE, 2381 sizeof(rme96_t))) == NULL) 2382 return -ENOMEM; 2383 card->private_free = snd_rme96_card_free; 2384 rme96 = (rme96_t *)card->private_data; 2385 rme96->card = card; 2386 rme96->pci = pci; 2387 snd_card_set_dev(card, &pci->dev); 2388 if ((err = snd_rme96_create(rme96)) < 0) { 2389 snd_card_free(card); 2390 return err; 2391 } 2392 2393 strcpy(card->driver, "Digi96"); 2394 switch (rme96->pci->device) { 2395 case PCI_DEVICE_ID_DIGI96: 2396 strcpy(card->shortname, "RME Digi96"); 2397 break; 2398 case PCI_DEVICE_ID_DIGI96_8: 2399 strcpy(card->shortname, "RME Digi96/8"); 2400 break; 2401 case PCI_DEVICE_ID_DIGI96_8_PRO: 2402 strcpy(card->shortname, "RME Digi96/8 PRO"); 2403 break; 2404 case PCI_DEVICE_ID_DIGI96_8_PAD_OR_PST: 2405 pci_read_config_byte(rme96->pci, 8, &val); 2406 if (val < 5) { 2407 strcpy(card->shortname, "RME Digi96/8 PAD"); 2408 } else { 2409 strcpy(card->shortname, "RME Digi96/8 PST"); 2410 } 2411 break; 2412 } 2413 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, 2414 rme96->port, rme96->irq); 2415 2416 if ((err = snd_card_register(card)) < 0) { 2417 snd_card_free(card); 2418 return err; 2419 } 2420 pci_set_drvdata(pci, card); 2421 dev++; 2422 return 0; 2423 } 2424 2425 static void __devexit snd_rme96_remove(struct pci_dev *pci) 2426 { 2427 snd_card_free(pci_get_drvdata(pci)); 2428 pci_set_drvdata(pci, NULL); 2429 } 2430 2431 static struct pci_driver driver = { 2432 .name = "RME Digi96", 2433 .id_table = snd_rme96_ids, 2434 .probe = snd_rme96_probe, 2435 .remove = __devexit_p(snd_rme96_remove), 2436 }; 2437 2438 static int __init alsa_card_rme96_init(void) 2439 { 2440 return pci_module_init(&driver); 2441 } 2442 2443 static void __exit alsa_card_rme96_exit(void) 2444 { 2445 pci_unregister_driver(&driver); 2446 } 2447 2448 module_init(alsa_card_rme96_init) 2449 module_exit(alsa_card_rme96_exit) 2450