xref: /openbmc/linux/sound/pci/rme32.c (revision e868d61272caa648214046a096e5a6bfc068dc8c)
1 /*
2  *   ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
3  *
4  *      Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
5  *                              Pilo Chambert <pilo.c@wanadoo.fr>
6  *
7  *      Thanks to :        Anders Torger <torger@ludd.luth.se>,
8  *                         Henk Hesselink <henk@anda.nl>
9  *                         for writing the digi96-driver
10  *                         and RME for all informations.
11  *
12  *   This program is free software; you can redistribute it and/or modify
13  *   it under the terms of the GNU General Public License as published by
14  *   the Free Software Foundation; either version 2 of the License, or
15  *   (at your option) any later version.
16  *
17  *   This program is distributed in the hope that it will be useful,
18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20  *   GNU General Public License for more details.
21  *
22  *   You should have received a copy of the GNU General Public License
23  *   along with this program; if not, write to the Free Software
24  *   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25  *
26  *
27  * ****************************************************************************
28  *
29  * Note #1 "Sek'd models" ................................... martin 2002-12-07
30  *
31  * Identical soundcards by Sek'd were labeled:
32  * RME Digi 32     = Sek'd Prodif 32
33  * RME Digi 32 Pro = Sek'd Prodif 96
34  * RME Digi 32/8   = Sek'd Prodif Gold
35  *
36  * ****************************************************************************
37  *
38  * Note #2 "full duplex mode" ............................... martin 2002-12-07
39  *
40  * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
41  * in this mode. Rec data and play data are using the same buffer therefore. At
42  * first you have got the playing bits in the buffer and then (after playing
43  * them) they were overwitten by the captured sound of the CS8412/14. Both
44  * modes (play/record) are running harmonically hand in hand in the same buffer
45  * and you have only one start bit plus one interrupt bit to control this
46  * paired action.
47  * This is opposite to the latter rme96 where playing and capturing is totally
48  * separated and so their full duplex mode is supported by alsa (using two
49  * start bits and two interrupts for two different buffers).
50  * But due to the wrong sequence of playing and capturing ALSA shows no solved
51  * full duplex support for the rme32 at the moment. That's bad, but I'm not
52  * able to solve it. Are you motivated enough to solve this problem now? Your
53  * patch would be welcome!
54  *
55  * ****************************************************************************
56  *
57  * "The story after the long seeking" -- tiwai
58  *
59  * Ok, the situation regarding the full duplex is now improved a bit.
60  * In the fullduplex mode (given by the module parameter), the hardware buffer
61  * is split to halves for read and write directions at the DMA pointer.
62  * That is, the half above the current DMA pointer is used for write, and
63  * the half below is used for read.  To mangle this strange behavior, an
64  * software intermediate buffer is introduced.  This is, of course, not good
65  * from the viewpoint of the data transfer efficiency.  However, this allows
66  * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
67  *
68  * ****************************************************************************
69  */
70 
71 
72 #include <sound/driver.h>
73 #include <linux/delay.h>
74 #include <linux/init.h>
75 #include <linux/interrupt.h>
76 #include <linux/pci.h>
77 #include <linux/slab.h>
78 #include <linux/moduleparam.h>
79 
80 #include <sound/core.h>
81 #include <sound/info.h>
82 #include <sound/control.h>
83 #include <sound/pcm.h>
84 #include <sound/pcm_params.h>
85 #include <sound/pcm-indirect.h>
86 #include <sound/asoundef.h>
87 #include <sound/initval.h>
88 
89 #include <asm/io.h>
90 
91 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
92 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
93 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable this card */
94 static int fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
95 
96 module_param_array(index, int, NULL, 0444);
97 MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
98 module_param_array(id, charp, NULL, 0444);
99 MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
100 module_param_array(enable, bool, NULL, 0444);
101 MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
102 module_param_array(fullduplex, bool, NULL, 0444);
103 MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
104 MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
105 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
106 MODULE_LICENSE("GPL");
107 MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
108 
109 /* Defines for RME Digi32 series */
110 #define RME32_SPDIF_NCHANNELS 2
111 
112 /* Playback and capture buffer size */
113 #define RME32_BUFFER_SIZE 0x20000
114 
115 /* IO area size */
116 #define RME32_IO_SIZE 0x30000
117 
118 /* IO area offsets */
119 #define RME32_IO_DATA_BUFFER        0x0
120 #define RME32_IO_CONTROL_REGISTER   0x20000
121 #define RME32_IO_GET_POS            0x20000
122 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
123 #define RME32_IO_RESET_POS          0x20100
124 
125 /* Write control register bits */
126 #define RME32_WCR_START     (1 << 0)    /* startbit */
127 #define RME32_WCR_MONO      (1 << 1)    /* 0=stereo, 1=mono
128                                            Setting the whole card to mono
129                                            doesn't seem to be very useful.
130                                            A software-solution can handle
131                                            full-duplex with one direction in
132                                            stereo and the other way in mono.
133                                            So, the hardware should work all
134                                            the time in stereo! */
135 #define RME32_WCR_MODE24    (1 << 2)    /* 0=16bit, 1=32bit */
136 #define RME32_WCR_SEL       (1 << 3)    /* 0=input on output, 1=normal playback/capture */
137 #define RME32_WCR_FREQ_0    (1 << 4)    /* frequency (play) */
138 #define RME32_WCR_FREQ_1    (1 << 5)
139 #define RME32_WCR_INP_0     (1 << 6)    /* input switch */
140 #define RME32_WCR_INP_1     (1 << 7)
141 #define RME32_WCR_RESET     (1 << 8)    /* Reset address */
142 #define RME32_WCR_MUTE      (1 << 9)    /* digital mute for output */
143 #define RME32_WCR_PRO       (1 << 10)   /* 1=professional, 0=consumer */
144 #define RME32_WCR_DS_BM     (1 << 11)	/* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
145 #define RME32_WCR_ADAT      (1 << 12)	/* Adat Mode (only Adat-Version) */
146 #define RME32_WCR_AUTOSYNC  (1 << 13)   /* AutoSync */
147 #define RME32_WCR_PD        (1 << 14)	/* DAC Reset (only PRO-Version) */
148 #define RME32_WCR_EMP       (1 << 15)	/* 1=Emphasis on (only PRO-Version) */
149 
150 #define RME32_WCR_BITPOS_FREQ_0 4
151 #define RME32_WCR_BITPOS_FREQ_1 5
152 #define RME32_WCR_BITPOS_INP_0 6
153 #define RME32_WCR_BITPOS_INP_1 7
154 
155 /* Read control register bits */
156 #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
157 #define RME32_RCR_LOCK      (1 << 23)   /* 1=locked, 0=not locked */
158 #define RME32_RCR_ERF       (1 << 26)   /* 1=Error, 0=no Error */
159 #define RME32_RCR_FREQ_0    (1 << 27)   /* CS841x frequency (record) */
160 #define RME32_RCR_FREQ_1    (1 << 28)
161 #define RME32_RCR_FREQ_2    (1 << 29)
162 #define RME32_RCR_KMODE     (1 << 30)   /* card mode: 1=PLL, 0=quartz */
163 #define RME32_RCR_IRQ       (1 << 31)   /* interrupt */
164 
165 #define RME32_RCR_BITPOS_F0 27
166 #define RME32_RCR_BITPOS_F1 28
167 #define RME32_RCR_BITPOS_F2 29
168 
169 /* Input types */
170 #define RME32_INPUT_OPTICAL 0
171 #define RME32_INPUT_COAXIAL 1
172 #define RME32_INPUT_INTERNAL 2
173 #define RME32_INPUT_XLR 3
174 
175 /* Clock modes */
176 #define RME32_CLOCKMODE_SLAVE 0
177 #define RME32_CLOCKMODE_MASTER_32 1
178 #define RME32_CLOCKMODE_MASTER_44 2
179 #define RME32_CLOCKMODE_MASTER_48 3
180 
181 /* Block sizes in bytes */
182 #define RME32_BLOCK_SIZE 8192
183 
184 /* Software intermediate buffer (max) size */
185 #define RME32_MID_BUFFER_SIZE (1024*1024)
186 
187 /* Hardware revisions */
188 #define RME32_32_REVISION 192
189 #define RME32_328_REVISION_OLD 100
190 #define RME32_328_REVISION_NEW 101
191 #define RME32_PRO_REVISION_WITH_8412 192
192 #define RME32_PRO_REVISION_WITH_8414 150
193 
194 
195 struct rme32 {
196 	spinlock_t lock;
197 	int irq;
198 	unsigned long port;
199 	void __iomem *iobase;
200 
201 	u32 wcreg;		/* cached write control register value */
202 	u32 wcreg_spdif;	/* S/PDIF setup */
203 	u32 wcreg_spdif_stream;	/* S/PDIF setup (temporary) */
204 	u32 rcreg;		/* cached read control register value */
205 
206 	u8 rev;			/* card revision number */
207 
208 	struct snd_pcm_substream *playback_substream;
209 	struct snd_pcm_substream *capture_substream;
210 
211 	int playback_frlog;	/* log2 of framesize */
212 	int capture_frlog;
213 
214 	size_t playback_periodsize;	/* in bytes, zero if not used */
215 	size_t capture_periodsize;	/* in bytes, zero if not used */
216 
217 	unsigned int fullduplex_mode;
218 	int running;
219 
220 	struct snd_pcm_indirect playback_pcm;
221 	struct snd_pcm_indirect capture_pcm;
222 
223 	struct snd_card *card;
224 	struct snd_pcm *spdif_pcm;
225 	struct snd_pcm *adat_pcm;
226 	struct pci_dev *pci;
227 	struct snd_kcontrol *spdif_ctl;
228 };
229 
230 static struct pci_device_id snd_rme32_ids[] = {
231 	{PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32,
232 	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
233 	{PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8,
234 	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
235 	{PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO,
236 	 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
237 	{0,}
238 };
239 
240 MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
241 
242 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
243 #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
244 
245 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
246 
247 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
248 
249 static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
250 
251 static void snd_rme32_proc_init(struct rme32 * rme32);
252 
253 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
254 
255 static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
256 {
257 	return (readl(rme32->iobase + RME32_IO_GET_POS)
258 		& RME32_RCR_AUDIO_ADDR_MASK);
259 }
260 
261 static int snd_rme32_ratecode(int rate)
262 {
263 	switch (rate) {
264 	case 32000: return SNDRV_PCM_RATE_32000;
265 	case 44100: return SNDRV_PCM_RATE_44100;
266 	case 48000: return SNDRV_PCM_RATE_48000;
267 	case 64000: return SNDRV_PCM_RATE_64000;
268 	case 88200: return SNDRV_PCM_RATE_88200;
269 	case 96000: return SNDRV_PCM_RATE_96000;
270 	}
271 	return 0;
272 }
273 
274 /* silence callback for halfduplex mode */
275 static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, int channel,	/* not used (interleaved data) */
276 				      snd_pcm_uframes_t pos,
277 				      snd_pcm_uframes_t count)
278 {
279 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
280 	count <<= rme32->playback_frlog;
281 	pos <<= rme32->playback_frlog;
282 	memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
283 	return 0;
284 }
285 
286 /* copy callback for halfduplex mode */
287 static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, int channel,	/* not used (interleaved data) */
288 				   snd_pcm_uframes_t pos,
289 				   void __user *src, snd_pcm_uframes_t count)
290 {
291 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
292 	count <<= rme32->playback_frlog;
293 	pos <<= rme32->playback_frlog;
294 	if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
295 			    src, count))
296 		return -EFAULT;
297 	return 0;
298 }
299 
300 /* copy callback for halfduplex mode */
301 static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, int channel,	/* not used (interleaved data) */
302 				  snd_pcm_uframes_t pos,
303 				  void __user *dst, snd_pcm_uframes_t count)
304 {
305 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
306 	count <<= rme32->capture_frlog;
307 	pos <<= rme32->capture_frlog;
308 	if (copy_to_user_fromio(dst,
309 			    rme32->iobase + RME32_IO_DATA_BUFFER + pos,
310 			    count))
311 		return -EFAULT;
312 	return 0;
313 }
314 
315 /*
316  * SPDIF I/O capabilities (half-duplex mode)
317  */
318 static struct snd_pcm_hardware snd_rme32_spdif_info = {
319 	.info =		(SNDRV_PCM_INFO_MMAP_IOMEM |
320 			 SNDRV_PCM_INFO_MMAP_VALID |
321 			 SNDRV_PCM_INFO_INTERLEAVED |
322 			 SNDRV_PCM_INFO_PAUSE |
323 			 SNDRV_PCM_INFO_SYNC_START),
324 	.formats =	(SNDRV_PCM_FMTBIT_S16_LE |
325 			 SNDRV_PCM_FMTBIT_S32_LE),
326 	.rates =	(SNDRV_PCM_RATE_32000 |
327 			 SNDRV_PCM_RATE_44100 |
328 			 SNDRV_PCM_RATE_48000),
329 	.rate_min =	32000,
330 	.rate_max =	48000,
331 	.channels_min =	2,
332 	.channels_max =	2,
333 	.buffer_bytes_max = RME32_BUFFER_SIZE,
334 	.period_bytes_min = RME32_BLOCK_SIZE,
335 	.period_bytes_max = RME32_BLOCK_SIZE,
336 	.periods_min =	RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
337 	.periods_max =	RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
338 	.fifo_size =	0,
339 };
340 
341 /*
342  * ADAT I/O capabilities (half-duplex mode)
343  */
344 static struct snd_pcm_hardware snd_rme32_adat_info =
345 {
346 	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
347 			      SNDRV_PCM_INFO_MMAP_VALID |
348 			      SNDRV_PCM_INFO_INTERLEAVED |
349 			      SNDRV_PCM_INFO_PAUSE |
350 			      SNDRV_PCM_INFO_SYNC_START),
351 	.formats=            SNDRV_PCM_FMTBIT_S16_LE,
352 	.rates =             (SNDRV_PCM_RATE_44100 |
353 			      SNDRV_PCM_RATE_48000),
354 	.rate_min =          44100,
355 	.rate_max =          48000,
356 	.channels_min =      8,
357 	.channels_max =	     8,
358 	.buffer_bytes_max =  RME32_BUFFER_SIZE,
359 	.period_bytes_min =  RME32_BLOCK_SIZE,
360 	.period_bytes_max =  RME32_BLOCK_SIZE,
361 	.periods_min =	    RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
362 	.periods_max =	    RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
363 	.fifo_size =	    0,
364 };
365 
366 /*
367  * SPDIF I/O capabilities (full-duplex mode)
368  */
369 static struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
370 	.info =		(SNDRV_PCM_INFO_MMAP |
371 			 SNDRV_PCM_INFO_MMAP_VALID |
372 			 SNDRV_PCM_INFO_INTERLEAVED |
373 			 SNDRV_PCM_INFO_PAUSE |
374 			 SNDRV_PCM_INFO_SYNC_START),
375 	.formats =	(SNDRV_PCM_FMTBIT_S16_LE |
376 			 SNDRV_PCM_FMTBIT_S32_LE),
377 	.rates =	(SNDRV_PCM_RATE_32000 |
378 			 SNDRV_PCM_RATE_44100 |
379 			 SNDRV_PCM_RATE_48000),
380 	.rate_min =	32000,
381 	.rate_max =	48000,
382 	.channels_min =	2,
383 	.channels_max =	2,
384 	.buffer_bytes_max = RME32_MID_BUFFER_SIZE,
385 	.period_bytes_min = RME32_BLOCK_SIZE,
386 	.period_bytes_max = RME32_BLOCK_SIZE,
387 	.periods_min =	2,
388 	.periods_max =	RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
389 	.fifo_size =	0,
390 };
391 
392 /*
393  * ADAT I/O capabilities (full-duplex mode)
394  */
395 static struct snd_pcm_hardware snd_rme32_adat_fd_info =
396 {
397 	.info =		     (SNDRV_PCM_INFO_MMAP |
398 			      SNDRV_PCM_INFO_MMAP_VALID |
399 			      SNDRV_PCM_INFO_INTERLEAVED |
400 			      SNDRV_PCM_INFO_PAUSE |
401 			      SNDRV_PCM_INFO_SYNC_START),
402 	.formats=            SNDRV_PCM_FMTBIT_S16_LE,
403 	.rates =             (SNDRV_PCM_RATE_44100 |
404 			      SNDRV_PCM_RATE_48000),
405 	.rate_min =          44100,
406 	.rate_max =          48000,
407 	.channels_min =      8,
408 	.channels_max =	     8,
409 	.buffer_bytes_max =  RME32_MID_BUFFER_SIZE,
410 	.period_bytes_min =  RME32_BLOCK_SIZE,
411 	.period_bytes_max =  RME32_BLOCK_SIZE,
412 	.periods_min =	    2,
413 	.periods_max =	    RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
414 	.fifo_size =	    0,
415 };
416 
417 static void snd_rme32_reset_dac(struct rme32 *rme32)
418 {
419         writel(rme32->wcreg | RME32_WCR_PD,
420                rme32->iobase + RME32_IO_CONTROL_REGISTER);
421         writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
422 }
423 
424 static int snd_rme32_playback_getrate(struct rme32 * rme32)
425 {
426 	int rate;
427 
428 	rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
429 	       (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
430 	switch (rate) {
431 	case 1:
432 		rate = 32000;
433 		break;
434 	case 2:
435 		rate = 44100;
436 		break;
437 	case 3:
438 		rate = 48000;
439 		break;
440 	default:
441 		return -1;
442 	}
443 	return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
444 }
445 
446 static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
447 {
448 	int n;
449 
450 	*is_adat = 0;
451 	if (rme32->rcreg & RME32_RCR_LOCK) {
452                 /* ADAT rate */
453                 *is_adat = 1;
454 	}
455 	if (rme32->rcreg & RME32_RCR_ERF) {
456 		return -1;
457 	}
458 
459         /* S/PDIF rate */
460 	n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
461 		(((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
462 		(((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
463 
464 	if (RME32_PRO_WITH_8414(rme32))
465 		switch (n) {	/* supporting the CS8414 */
466 		case 0:
467 		case 1:
468 		case 2:
469 			return -1;
470 		case 3:
471 			return 96000;
472 		case 4:
473 			return 88200;
474 		case 5:
475 			return 48000;
476 		case 6:
477 			return 44100;
478 		case 7:
479 			return 32000;
480 		default:
481 			return -1;
482 			break;
483 		}
484 	else
485 		switch (n) {	/* supporting the CS8412 */
486 		case 0:
487 			return -1;
488 		case 1:
489 			return 48000;
490 		case 2:
491 			return 44100;
492 		case 3:
493 			return 32000;
494 		case 4:
495 			return 48000;
496 		case 5:
497 			return 44100;
498 		case 6:
499 			return 44056;
500 		case 7:
501 			return 32000;
502 		default:
503 			break;
504 		}
505 	return -1;
506 }
507 
508 static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
509 {
510         int ds;
511 
512         ds = rme32->wcreg & RME32_WCR_DS_BM;
513 	switch (rate) {
514 	case 32000:
515 		rme32->wcreg &= ~RME32_WCR_DS_BM;
516 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
517 			~RME32_WCR_FREQ_1;
518 		break;
519 	case 44100:
520 		rme32->wcreg &= ~RME32_WCR_DS_BM;
521 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
522 			~RME32_WCR_FREQ_0;
523 		break;
524 	case 48000:
525 		rme32->wcreg &= ~RME32_WCR_DS_BM;
526 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
527 			RME32_WCR_FREQ_1;
528 		break;
529 	case 64000:
530 		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
531 			return -EINVAL;
532 		rme32->wcreg |= RME32_WCR_DS_BM;
533 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
534 			~RME32_WCR_FREQ_1;
535 		break;
536 	case 88200:
537 		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
538 			return -EINVAL;
539 		rme32->wcreg |= RME32_WCR_DS_BM;
540 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
541 			~RME32_WCR_FREQ_0;
542 		break;
543 	case 96000:
544 		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
545 			return -EINVAL;
546 		rme32->wcreg |= RME32_WCR_DS_BM;
547 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
548 			RME32_WCR_FREQ_1;
549 		break;
550 	default:
551 		return -EINVAL;
552 	}
553         if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
554             (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
555         {
556                 /* change to/from double-speed: reset the DAC (if available) */
557                 snd_rme32_reset_dac(rme32);
558         } else {
559                 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
560 	}
561 	return 0;
562 }
563 
564 static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
565 {
566 	switch (mode) {
567 	case RME32_CLOCKMODE_SLAVE:
568 		/* AutoSync */
569 		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
570 			~RME32_WCR_FREQ_1;
571 		break;
572 	case RME32_CLOCKMODE_MASTER_32:
573 		/* Internal 32.0kHz */
574 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
575 			~RME32_WCR_FREQ_1;
576 		break;
577 	case RME32_CLOCKMODE_MASTER_44:
578 		/* Internal 44.1kHz */
579 		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
580 			RME32_WCR_FREQ_1;
581 		break;
582 	case RME32_CLOCKMODE_MASTER_48:
583 		/* Internal 48.0kHz */
584 		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
585 			RME32_WCR_FREQ_1;
586 		break;
587 	default:
588 		return -EINVAL;
589 	}
590 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
591 	return 0;
592 }
593 
594 static int snd_rme32_getclockmode(struct rme32 * rme32)
595 {
596 	return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
597 	    (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
598 }
599 
600 static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
601 {
602 	switch (type) {
603 	case RME32_INPUT_OPTICAL:
604 		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
605 			~RME32_WCR_INP_1;
606 		break;
607 	case RME32_INPUT_COAXIAL:
608 		rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
609 			~RME32_WCR_INP_1;
610 		break;
611 	case RME32_INPUT_INTERNAL:
612 		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
613 			RME32_WCR_INP_1;
614 		break;
615 	case RME32_INPUT_XLR:
616 		rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
617 			RME32_WCR_INP_1;
618 		break;
619 	default:
620 		return -EINVAL;
621 	}
622 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
623 	return 0;
624 }
625 
626 static int snd_rme32_getinputtype(struct rme32 * rme32)
627 {
628 	return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
629 	    (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
630 }
631 
632 static void
633 snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
634 {
635 	int frlog;
636 
637 	if (n_channels == 2) {
638 		frlog = 1;
639 	} else {
640 		/* assume 8 channels */
641 		frlog = 3;
642 	}
643 	if (is_playback) {
644 		frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
645 		rme32->playback_frlog = frlog;
646 	} else {
647 		frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
648 		rme32->capture_frlog = frlog;
649 	}
650 }
651 
652 static int snd_rme32_setformat(struct rme32 * rme32, int format)
653 {
654 	switch (format) {
655 	case SNDRV_PCM_FORMAT_S16_LE:
656 		rme32->wcreg &= ~RME32_WCR_MODE24;
657 		break;
658 	case SNDRV_PCM_FORMAT_S32_LE:
659 		rme32->wcreg |= RME32_WCR_MODE24;
660 		break;
661 	default:
662 		return -EINVAL;
663 	}
664 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
665 	return 0;
666 }
667 
668 static int
669 snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
670 			     struct snd_pcm_hw_params *params)
671 {
672 	int err, rate, dummy;
673 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
674 	struct snd_pcm_runtime *runtime = substream->runtime;
675 
676 	if (rme32->fullduplex_mode) {
677 		err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
678 		if (err < 0)
679 			return err;
680 	} else {
681 		runtime->dma_area = (void __force *)(rme32->iobase +
682 						     RME32_IO_DATA_BUFFER);
683 		runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
684 		runtime->dma_bytes = RME32_BUFFER_SIZE;
685 	}
686 
687 	spin_lock_irq(&rme32->lock);
688 	if ((rme32->rcreg & RME32_RCR_KMODE) &&
689 	    (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
690 		/* AutoSync */
691 		if ((int)params_rate(params) != rate) {
692 			spin_unlock_irq(&rme32->lock);
693 			return -EIO;
694 		}
695 	} else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
696 		spin_unlock_irq(&rme32->lock);
697 		return err;
698 	}
699 	if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
700 		spin_unlock_irq(&rme32->lock);
701 		return err;
702 	}
703 
704 	snd_rme32_setframelog(rme32, params_channels(params), 1);
705 	if (rme32->capture_periodsize != 0) {
706 		if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
707 			spin_unlock_irq(&rme32->lock);
708 			return -EBUSY;
709 		}
710 	}
711 	rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
712 	/* S/PDIF setup */
713 	if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
714 		rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
715 		rme32->wcreg |= rme32->wcreg_spdif_stream;
716 		writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
717 	}
718 	spin_unlock_irq(&rme32->lock);
719 
720 	return 0;
721 }
722 
723 static int
724 snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
725 			    struct snd_pcm_hw_params *params)
726 {
727 	int err, isadat, rate;
728 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
729 	struct snd_pcm_runtime *runtime = substream->runtime;
730 
731 	if (rme32->fullduplex_mode) {
732 		err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
733 		if (err < 0)
734 			return err;
735 	} else {
736 		runtime->dma_area = (void __force *)rme32->iobase +
737 					RME32_IO_DATA_BUFFER;
738 		runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
739 		runtime->dma_bytes = RME32_BUFFER_SIZE;
740 	}
741 
742 	spin_lock_irq(&rme32->lock);
743 	/* enable AutoSync for record-preparing */
744 	rme32->wcreg |= RME32_WCR_AUTOSYNC;
745 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
746 
747 	if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
748 		spin_unlock_irq(&rme32->lock);
749 		return err;
750 	}
751 	if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
752 		spin_unlock_irq(&rme32->lock);
753 		return err;
754 	}
755 	if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
756                 if ((int)params_rate(params) != rate) {
757 			spin_unlock_irq(&rme32->lock);
758                         return -EIO;
759                 }
760                 if ((isadat && runtime->hw.channels_min == 2) ||
761                     (!isadat && runtime->hw.channels_min == 8)) {
762 			spin_unlock_irq(&rme32->lock);
763                         return -EIO;
764                 }
765 	}
766 	/* AutoSync off for recording */
767 	rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
768 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
769 
770 	snd_rme32_setframelog(rme32, params_channels(params), 0);
771 	if (rme32->playback_periodsize != 0) {
772 		if (params_period_size(params) << rme32->capture_frlog !=
773 		    rme32->playback_periodsize) {
774 			spin_unlock_irq(&rme32->lock);
775 			return -EBUSY;
776 		}
777 	}
778 	rme32->capture_periodsize =
779 	    params_period_size(params) << rme32->capture_frlog;
780 	spin_unlock_irq(&rme32->lock);
781 
782 	return 0;
783 }
784 
785 static int snd_rme32_pcm_hw_free(struct snd_pcm_substream *substream)
786 {
787 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
788 	if (! rme32->fullduplex_mode)
789 		return 0;
790 	return snd_pcm_lib_free_pages(substream);
791 }
792 
793 static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
794 {
795 	if (!from_pause) {
796 		writel(0, rme32->iobase + RME32_IO_RESET_POS);
797 	}
798 
799 	rme32->wcreg |= RME32_WCR_START;
800 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
801 }
802 
803 static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
804 {
805 	/*
806 	 * Check if there is an unconfirmed IRQ, if so confirm it, or else
807 	 * the hardware will not stop generating interrupts
808 	 */
809 	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
810 	if (rme32->rcreg & RME32_RCR_IRQ) {
811 		writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
812 	}
813 	rme32->wcreg &= ~RME32_WCR_START;
814 	if (rme32->wcreg & RME32_WCR_SEL)
815 		rme32->wcreg |= RME32_WCR_MUTE;
816 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
817 	if (! to_pause)
818 		writel(0, rme32->iobase + RME32_IO_RESET_POS);
819 }
820 
821 static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
822 {
823 	struct rme32 *rme32 = (struct rme32 *) dev_id;
824 
825 	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
826 	if (!(rme32->rcreg & RME32_RCR_IRQ)) {
827 		return IRQ_NONE;
828 	} else {
829 		if (rme32->capture_substream) {
830 			snd_pcm_period_elapsed(rme32->capture_substream);
831 		}
832 		if (rme32->playback_substream) {
833 			snd_pcm_period_elapsed(rme32->playback_substream);
834 		}
835 		writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
836 	}
837 	return IRQ_HANDLED;
838 }
839 
840 static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
841 
842 
843 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
844 	.count = ARRAY_SIZE(period_bytes),
845 	.list = period_bytes,
846 	.mask = 0
847 };
848 
849 static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
850 {
851 	if (! rme32->fullduplex_mode) {
852 		snd_pcm_hw_constraint_minmax(runtime,
853 					     SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
854 					     RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
855 		snd_pcm_hw_constraint_list(runtime, 0,
856 					   SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
857 					   &hw_constraints_period_bytes);
858 	}
859 }
860 
861 static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
862 {
863 	int rate, dummy;
864 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
865 	struct snd_pcm_runtime *runtime = substream->runtime;
866 
867 	snd_pcm_set_sync(substream);
868 
869 	spin_lock_irq(&rme32->lock);
870 	if (rme32->playback_substream != NULL) {
871 		spin_unlock_irq(&rme32->lock);
872 		return -EBUSY;
873 	}
874 	rme32->wcreg &= ~RME32_WCR_ADAT;
875 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
876 	rme32->playback_substream = substream;
877 	spin_unlock_irq(&rme32->lock);
878 
879 	if (rme32->fullduplex_mode)
880 		runtime->hw = snd_rme32_spdif_fd_info;
881 	else
882 		runtime->hw = snd_rme32_spdif_info;
883 	if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
884 		runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
885 		runtime->hw.rate_max = 96000;
886 	}
887 	if ((rme32->rcreg & RME32_RCR_KMODE) &&
888 	    (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
889 		/* AutoSync */
890 		runtime->hw.rates = snd_rme32_ratecode(rate);
891 		runtime->hw.rate_min = rate;
892 		runtime->hw.rate_max = rate;
893 	}
894 
895 	snd_rme32_set_buffer_constraint(rme32, runtime);
896 
897 	rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
898 	rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
899 	snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
900 		       SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
901 	return 0;
902 }
903 
904 static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
905 {
906 	int isadat, rate;
907 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
908 	struct snd_pcm_runtime *runtime = substream->runtime;
909 
910 	snd_pcm_set_sync(substream);
911 
912 	spin_lock_irq(&rme32->lock);
913         if (rme32->capture_substream != NULL) {
914 		spin_unlock_irq(&rme32->lock);
915                 return -EBUSY;
916         }
917 	rme32->capture_substream = substream;
918 	spin_unlock_irq(&rme32->lock);
919 
920 	if (rme32->fullduplex_mode)
921 		runtime->hw = snd_rme32_spdif_fd_info;
922 	else
923 		runtime->hw = snd_rme32_spdif_info;
924 	if (RME32_PRO_WITH_8414(rme32)) {
925 		runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
926 		runtime->hw.rate_max = 96000;
927 	}
928 	if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
929 		if (isadat) {
930 			return -EIO;
931 		}
932 		runtime->hw.rates = snd_rme32_ratecode(rate);
933 		runtime->hw.rate_min = rate;
934 		runtime->hw.rate_max = rate;
935 	}
936 
937 	snd_rme32_set_buffer_constraint(rme32, runtime);
938 
939 	return 0;
940 }
941 
942 static int
943 snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
944 {
945 	int rate, dummy;
946 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
947 	struct snd_pcm_runtime *runtime = substream->runtime;
948 
949 	snd_pcm_set_sync(substream);
950 
951 	spin_lock_irq(&rme32->lock);
952         if (rme32->playback_substream != NULL) {
953 		spin_unlock_irq(&rme32->lock);
954                 return -EBUSY;
955         }
956 	rme32->wcreg |= RME32_WCR_ADAT;
957 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
958 	rme32->playback_substream = substream;
959 	spin_unlock_irq(&rme32->lock);
960 
961 	if (rme32->fullduplex_mode)
962 		runtime->hw = snd_rme32_adat_fd_info;
963 	else
964 		runtime->hw = snd_rme32_adat_info;
965 	if ((rme32->rcreg & RME32_RCR_KMODE) &&
966 	    (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
967                 /* AutoSync */
968                 runtime->hw.rates = snd_rme32_ratecode(rate);
969                 runtime->hw.rate_min = rate;
970                 runtime->hw.rate_max = rate;
971 	}
972 
973 	snd_rme32_set_buffer_constraint(rme32, runtime);
974 	return 0;
975 }
976 
977 static int
978 snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
979 {
980 	int isadat, rate;
981 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
982 	struct snd_pcm_runtime *runtime = substream->runtime;
983 
984 	if (rme32->fullduplex_mode)
985 		runtime->hw = snd_rme32_adat_fd_info;
986 	else
987 		runtime->hw = snd_rme32_adat_info;
988 	if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
989 		if (!isadat) {
990 			return -EIO;
991 		}
992                 runtime->hw.rates = snd_rme32_ratecode(rate);
993                 runtime->hw.rate_min = rate;
994                 runtime->hw.rate_max = rate;
995         }
996 
997 	snd_pcm_set_sync(substream);
998 
999 	spin_lock_irq(&rme32->lock);
1000 	if (rme32->capture_substream != NULL) {
1001 		spin_unlock_irq(&rme32->lock);
1002 		return -EBUSY;
1003         }
1004 	rme32->capture_substream = substream;
1005 	spin_unlock_irq(&rme32->lock);
1006 
1007 	snd_rme32_set_buffer_constraint(rme32, runtime);
1008 	return 0;
1009 }
1010 
1011 static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
1012 {
1013 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1014 	int spdif = 0;
1015 
1016 	spin_lock_irq(&rme32->lock);
1017 	rme32->playback_substream = NULL;
1018 	rme32->playback_periodsize = 0;
1019 	spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1020 	spin_unlock_irq(&rme32->lock);
1021 	if (spdif) {
1022 		rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1023 		snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1024 			       SNDRV_CTL_EVENT_MASK_INFO,
1025 			       &rme32->spdif_ctl->id);
1026 	}
1027 	return 0;
1028 }
1029 
1030 static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1031 {
1032 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1033 
1034 	spin_lock_irq(&rme32->lock);
1035 	rme32->capture_substream = NULL;
1036 	rme32->capture_periodsize = 0;
1037 	spin_unlock(&rme32->lock);
1038 	return 0;
1039 }
1040 
1041 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1042 {
1043 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1044 
1045 	spin_lock_irq(&rme32->lock);
1046 	if (rme32->fullduplex_mode) {
1047 		memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1048 		rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1049 		rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1050 	} else {
1051 		writel(0, rme32->iobase + RME32_IO_RESET_POS);
1052 	}
1053 	if (rme32->wcreg & RME32_WCR_SEL)
1054 		rme32->wcreg &= ~RME32_WCR_MUTE;
1055 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1056 	spin_unlock_irq(&rme32->lock);
1057 	return 0;
1058 }
1059 
1060 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1061 {
1062 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1063 
1064 	spin_lock_irq(&rme32->lock);
1065 	if (rme32->fullduplex_mode) {
1066 		memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1067 		rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1068 		rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1069 		rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1070 	} else {
1071 		writel(0, rme32->iobase + RME32_IO_RESET_POS);
1072 	}
1073 	spin_unlock_irq(&rme32->lock);
1074 	return 0;
1075 }
1076 
1077 static int
1078 snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1079 {
1080 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1081 	struct snd_pcm_substream *s;
1082 
1083 	spin_lock(&rme32->lock);
1084 	snd_pcm_group_for_each_entry(s, substream) {
1085 		if (s != rme32->playback_substream &&
1086 		    s != rme32->capture_substream)
1087 			continue;
1088 		switch (cmd) {
1089 		case SNDRV_PCM_TRIGGER_START:
1090 			rme32->running |= (1 << s->stream);
1091 			if (rme32->fullduplex_mode) {
1092 				/* remember the current DMA position */
1093 				if (s == rme32->playback_substream) {
1094 					rme32->playback_pcm.hw_io =
1095 					rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1096 				} else {
1097 					rme32->capture_pcm.hw_io =
1098 					rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1099 				}
1100 			}
1101 			break;
1102 		case SNDRV_PCM_TRIGGER_STOP:
1103 			rme32->running &= ~(1 << s->stream);
1104 			break;
1105 		}
1106 		snd_pcm_trigger_done(s, substream);
1107 	}
1108 
1109 	/* prefill playback buffer */
1110 	if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) {
1111 		snd_pcm_group_for_each_entry(s, substream) {
1112 			if (s == rme32->playback_substream) {
1113 				s->ops->ack(s);
1114 				break;
1115 			}
1116 		}
1117 	}
1118 
1119 	switch (cmd) {
1120 	case SNDRV_PCM_TRIGGER_START:
1121 		if (rme32->running && ! RME32_ISWORKING(rme32))
1122 			snd_rme32_pcm_start(rme32, 0);
1123 		break;
1124 	case SNDRV_PCM_TRIGGER_STOP:
1125 		if (! rme32->running && RME32_ISWORKING(rme32))
1126 			snd_rme32_pcm_stop(rme32, 0);
1127 		break;
1128 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1129 		if (rme32->running && RME32_ISWORKING(rme32))
1130 			snd_rme32_pcm_stop(rme32, 1);
1131 		break;
1132 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1133 		if (rme32->running && ! RME32_ISWORKING(rme32))
1134 			snd_rme32_pcm_start(rme32, 1);
1135 		break;
1136 	}
1137 	spin_unlock(&rme32->lock);
1138 	return 0;
1139 }
1140 
1141 /* pointer callback for halfduplex mode */
1142 static snd_pcm_uframes_t
1143 snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1144 {
1145 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1146 	return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1147 }
1148 
1149 static snd_pcm_uframes_t
1150 snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1151 {
1152 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1153 	return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1154 }
1155 
1156 
1157 /* ack and pointer callbacks for fullduplex mode */
1158 static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1159 				    struct snd_pcm_indirect *rec, size_t bytes)
1160 {
1161 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1162 	memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1163 		    substream->runtime->dma_area + rec->sw_data, bytes);
1164 }
1165 
1166 static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1167 {
1168 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1169 	struct snd_pcm_indirect *rec, *cprec;
1170 
1171 	rec = &rme32->playback_pcm;
1172 	cprec = &rme32->capture_pcm;
1173 	spin_lock(&rme32->lock);
1174 	rec->hw_queue_size = RME32_BUFFER_SIZE;
1175 	if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1176 		rec->hw_queue_size -= cprec->hw_ready;
1177 	spin_unlock(&rme32->lock);
1178 	snd_pcm_indirect_playback_transfer(substream, rec,
1179 					   snd_rme32_pb_trans_copy);
1180 	return 0;
1181 }
1182 
1183 static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1184 				    struct snd_pcm_indirect *rec, size_t bytes)
1185 {
1186 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1187 	memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1188 		      rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1189 		      bytes);
1190 }
1191 
1192 static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1193 {
1194 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1195 	snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1196 					  snd_rme32_cp_trans_copy);
1197 	return 0;
1198 }
1199 
1200 static snd_pcm_uframes_t
1201 snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1202 {
1203 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1204 	return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1205 						 snd_rme32_pcm_byteptr(rme32));
1206 }
1207 
1208 static snd_pcm_uframes_t
1209 snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1210 {
1211 	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1212 	return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1213 						snd_rme32_pcm_byteptr(rme32));
1214 }
1215 
1216 /* for halfduplex mode */
1217 static struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1218 	.open =		snd_rme32_playback_spdif_open,
1219 	.close =	snd_rme32_playback_close,
1220 	.ioctl =	snd_pcm_lib_ioctl,
1221 	.hw_params =	snd_rme32_playback_hw_params,
1222 	.hw_free =	snd_rme32_pcm_hw_free,
1223 	.prepare =	snd_rme32_playback_prepare,
1224 	.trigger =	snd_rme32_pcm_trigger,
1225 	.pointer =	snd_rme32_playback_pointer,
1226 	.copy =		snd_rme32_playback_copy,
1227 	.silence =	snd_rme32_playback_silence,
1228 	.mmap =		snd_pcm_lib_mmap_iomem,
1229 };
1230 
1231 static struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1232 	.open =		snd_rme32_capture_spdif_open,
1233 	.close =	snd_rme32_capture_close,
1234 	.ioctl =	snd_pcm_lib_ioctl,
1235 	.hw_params =	snd_rme32_capture_hw_params,
1236 	.hw_free =	snd_rme32_pcm_hw_free,
1237 	.prepare =	snd_rme32_capture_prepare,
1238 	.trigger =	snd_rme32_pcm_trigger,
1239 	.pointer =	snd_rme32_capture_pointer,
1240 	.copy =		snd_rme32_capture_copy,
1241 	.mmap =		snd_pcm_lib_mmap_iomem,
1242 };
1243 
1244 static struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1245 	.open =		snd_rme32_playback_adat_open,
1246 	.close =	snd_rme32_playback_close,
1247 	.ioctl =	snd_pcm_lib_ioctl,
1248 	.hw_params =	snd_rme32_playback_hw_params,
1249 	.prepare =	snd_rme32_playback_prepare,
1250 	.trigger =	snd_rme32_pcm_trigger,
1251 	.pointer =	snd_rme32_playback_pointer,
1252 	.copy =		snd_rme32_playback_copy,
1253 	.silence =	snd_rme32_playback_silence,
1254 	.mmap =		snd_pcm_lib_mmap_iomem,
1255 };
1256 
1257 static struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1258 	.open =		snd_rme32_capture_adat_open,
1259 	.close =	snd_rme32_capture_close,
1260 	.ioctl =	snd_pcm_lib_ioctl,
1261 	.hw_params =	snd_rme32_capture_hw_params,
1262 	.prepare =	snd_rme32_capture_prepare,
1263 	.trigger =	snd_rme32_pcm_trigger,
1264 	.pointer =	snd_rme32_capture_pointer,
1265 	.copy =		snd_rme32_capture_copy,
1266 	.mmap =		snd_pcm_lib_mmap_iomem,
1267 };
1268 
1269 /* for fullduplex mode */
1270 static struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1271 	.open =		snd_rme32_playback_spdif_open,
1272 	.close =	snd_rme32_playback_close,
1273 	.ioctl =	snd_pcm_lib_ioctl,
1274 	.hw_params =	snd_rme32_playback_hw_params,
1275 	.hw_free =	snd_rme32_pcm_hw_free,
1276 	.prepare =	snd_rme32_playback_prepare,
1277 	.trigger =	snd_rme32_pcm_trigger,
1278 	.pointer =	snd_rme32_playback_fd_pointer,
1279 	.ack =		snd_rme32_playback_fd_ack,
1280 };
1281 
1282 static struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1283 	.open =		snd_rme32_capture_spdif_open,
1284 	.close =	snd_rme32_capture_close,
1285 	.ioctl =	snd_pcm_lib_ioctl,
1286 	.hw_params =	snd_rme32_capture_hw_params,
1287 	.hw_free =	snd_rme32_pcm_hw_free,
1288 	.prepare =	snd_rme32_capture_prepare,
1289 	.trigger =	snd_rme32_pcm_trigger,
1290 	.pointer =	snd_rme32_capture_fd_pointer,
1291 	.ack =		snd_rme32_capture_fd_ack,
1292 };
1293 
1294 static struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1295 	.open =		snd_rme32_playback_adat_open,
1296 	.close =	snd_rme32_playback_close,
1297 	.ioctl =	snd_pcm_lib_ioctl,
1298 	.hw_params =	snd_rme32_playback_hw_params,
1299 	.prepare =	snd_rme32_playback_prepare,
1300 	.trigger =	snd_rme32_pcm_trigger,
1301 	.pointer =	snd_rme32_playback_fd_pointer,
1302 	.ack =		snd_rme32_playback_fd_ack,
1303 };
1304 
1305 static struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1306 	.open =		snd_rme32_capture_adat_open,
1307 	.close =	snd_rme32_capture_close,
1308 	.ioctl =	snd_pcm_lib_ioctl,
1309 	.hw_params =	snd_rme32_capture_hw_params,
1310 	.prepare =	snd_rme32_capture_prepare,
1311 	.trigger =	snd_rme32_pcm_trigger,
1312 	.pointer =	snd_rme32_capture_fd_pointer,
1313 	.ack =		snd_rme32_capture_fd_ack,
1314 };
1315 
1316 static void snd_rme32_free(void *private_data)
1317 {
1318 	struct rme32 *rme32 = (struct rme32 *) private_data;
1319 
1320 	if (rme32 == NULL) {
1321 		return;
1322 	}
1323 	if (rme32->irq >= 0) {
1324 		snd_rme32_pcm_stop(rme32, 0);
1325 		free_irq(rme32->irq, (void *) rme32);
1326 		rme32->irq = -1;
1327 	}
1328 	if (rme32->iobase) {
1329 		iounmap(rme32->iobase);
1330 		rme32->iobase = NULL;
1331 	}
1332 	if (rme32->port) {
1333 		pci_release_regions(rme32->pci);
1334 		rme32->port = 0;
1335 	}
1336 	pci_disable_device(rme32->pci);
1337 }
1338 
1339 static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1340 {
1341 	struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1342 	rme32->spdif_pcm = NULL;
1343 }
1344 
1345 static void
1346 snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1347 {
1348 	struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1349 	rme32->adat_pcm = NULL;
1350 }
1351 
1352 static int __devinit snd_rme32_create(struct rme32 * rme32)
1353 {
1354 	struct pci_dev *pci = rme32->pci;
1355 	int err;
1356 
1357 	rme32->irq = -1;
1358 	spin_lock_init(&rme32->lock);
1359 
1360 	if ((err = pci_enable_device(pci)) < 0)
1361 		return err;
1362 
1363 	if ((err = pci_request_regions(pci, "RME32")) < 0)
1364 		return err;
1365 	rme32->port = pci_resource_start(rme32->pci, 0);
1366 
1367 	if ((rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE)) == 0) {
1368 		snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n",
1369 			   rme32->port, rme32->port + RME32_IO_SIZE - 1);
1370 		return -ENOMEM;
1371 	}
1372 
1373 	if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED,
1374 			"RME32", rme32)) {
1375 		snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1376 		return -EBUSY;
1377 	}
1378 	rme32->irq = pci->irq;
1379 
1380 	/* read the card's revision number */
1381 	pci_read_config_byte(pci, 8, &rme32->rev);
1382 
1383 	/* set up ALSA pcm device for S/PDIF */
1384 	if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
1385 		return err;
1386 	}
1387 	rme32->spdif_pcm->private_data = rme32;
1388 	rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1389 	strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1390 	if (rme32->fullduplex_mode) {
1391 		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1392 				&snd_rme32_playback_spdif_fd_ops);
1393 		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1394 				&snd_rme32_capture_spdif_fd_ops);
1395 		snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1396 						      snd_dma_continuous_data(GFP_KERNEL),
1397 						      0, RME32_MID_BUFFER_SIZE);
1398 		rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1399 	} else {
1400 		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1401 				&snd_rme32_playback_spdif_ops);
1402 		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1403 				&snd_rme32_capture_spdif_ops);
1404 		rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1405 	}
1406 
1407 	/* set up ALSA pcm device for ADAT */
1408 	if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1409 	    (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1410 		/* ADAT is not available on DIGI32 and DIGI32 Pro */
1411 		rme32->adat_pcm = NULL;
1412 	}
1413 	else {
1414 		if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1415 				       1, 1, &rme32->adat_pcm)) < 0)
1416 		{
1417 			return err;
1418 		}
1419 		rme32->adat_pcm->private_data = rme32;
1420 		rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1421 		strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1422 		if (rme32->fullduplex_mode) {
1423 			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1424 					&snd_rme32_playback_adat_fd_ops);
1425 			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1426 					&snd_rme32_capture_adat_fd_ops);
1427 			snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1428 							      snd_dma_continuous_data(GFP_KERNEL),
1429 							      0, RME32_MID_BUFFER_SIZE);
1430 			rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1431 		} else {
1432 			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1433 					&snd_rme32_playback_adat_ops);
1434 			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
1435 					&snd_rme32_capture_adat_ops);
1436 			rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1437 		}
1438 	}
1439 
1440 
1441 	rme32->playback_periodsize = 0;
1442 	rme32->capture_periodsize = 0;
1443 
1444 	/* make sure playback/capture is stopped, if by some reason active */
1445 	snd_rme32_pcm_stop(rme32, 0);
1446 
1447         /* reset DAC */
1448         snd_rme32_reset_dac(rme32);
1449 
1450 	/* reset buffer pointer */
1451 	writel(0, rme32->iobase + RME32_IO_RESET_POS);
1452 
1453 	/* set default values in registers */
1454 	rme32->wcreg = RME32_WCR_SEL |	 /* normal playback */
1455 		RME32_WCR_INP_0 | /* input select */
1456 		RME32_WCR_MUTE;	 /* muting on */
1457 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1458 
1459 
1460 	/* init switch interface */
1461 	if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
1462 		return err;
1463 	}
1464 
1465 	/* init proc interface */
1466 	snd_rme32_proc_init(rme32);
1467 
1468 	rme32->capture_substream = NULL;
1469 	rme32->playback_substream = NULL;
1470 
1471 	return 0;
1472 }
1473 
1474 /*
1475  * proc interface
1476  */
1477 
1478 static void
1479 snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1480 {
1481 	int n;
1482 	struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1483 
1484 	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1485 
1486 	snd_iprintf(buffer, rme32->card->longname);
1487 	snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1488 
1489 	snd_iprintf(buffer, "\nGeneral settings\n");
1490 	if (rme32->fullduplex_mode)
1491 		snd_iprintf(buffer, "  Full-duplex mode\n");
1492 	else
1493 		snd_iprintf(buffer, "  Half-duplex mode\n");
1494 	if (RME32_PRO_WITH_8414(rme32)) {
1495 		snd_iprintf(buffer, "  receiver: CS8414\n");
1496 	} else {
1497 		snd_iprintf(buffer, "  receiver: CS8412\n");
1498 	}
1499 	if (rme32->wcreg & RME32_WCR_MODE24) {
1500 		snd_iprintf(buffer, "  format: 24 bit");
1501 	} else {
1502 		snd_iprintf(buffer, "  format: 16 bit");
1503 	}
1504 	if (rme32->wcreg & RME32_WCR_MONO) {
1505 		snd_iprintf(buffer, ", Mono\n");
1506 	} else {
1507 		snd_iprintf(buffer, ", Stereo\n");
1508 	}
1509 
1510 	snd_iprintf(buffer, "\nInput settings\n");
1511 	switch (snd_rme32_getinputtype(rme32)) {
1512 	case RME32_INPUT_OPTICAL:
1513 		snd_iprintf(buffer, "  input: optical");
1514 		break;
1515 	case RME32_INPUT_COAXIAL:
1516 		snd_iprintf(buffer, "  input: coaxial");
1517 		break;
1518 	case RME32_INPUT_INTERNAL:
1519 		snd_iprintf(buffer, "  input: internal");
1520 		break;
1521 	case RME32_INPUT_XLR:
1522 		snd_iprintf(buffer, "  input: XLR");
1523 		break;
1524 	}
1525 	if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1526 		snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1527 	} else {
1528 		if (n) {
1529 			snd_iprintf(buffer, " (8 channels)\n");
1530 		} else {
1531 			snd_iprintf(buffer, " (2 channels)\n");
1532 		}
1533 		snd_iprintf(buffer, "  sample rate: %d Hz\n",
1534 			    snd_rme32_capture_getrate(rme32, &n));
1535 	}
1536 
1537 	snd_iprintf(buffer, "\nOutput settings\n");
1538 	if (rme32->wcreg & RME32_WCR_SEL) {
1539 		snd_iprintf(buffer, "  output signal: normal playback");
1540 	} else {
1541 		snd_iprintf(buffer, "  output signal: same as input");
1542 	}
1543 	if (rme32->wcreg & RME32_WCR_MUTE) {
1544 		snd_iprintf(buffer, " (muted)\n");
1545 	} else {
1546 		snd_iprintf(buffer, "\n");
1547 	}
1548 
1549 	/* master output frequency */
1550 	if (!
1551 	    ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1552 	     && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1553 		snd_iprintf(buffer, "  sample rate: %d Hz\n",
1554 			    snd_rme32_playback_getrate(rme32));
1555 	}
1556 	if (rme32->rcreg & RME32_RCR_KMODE) {
1557 		snd_iprintf(buffer, "  sample clock source: AutoSync\n");
1558 	} else {
1559 		snd_iprintf(buffer, "  sample clock source: Internal\n");
1560 	}
1561 	if (rme32->wcreg & RME32_WCR_PRO) {
1562 		snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1563 	} else {
1564 		snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1565 	}
1566 	if (rme32->wcreg & RME32_WCR_EMP) {
1567 		snd_iprintf(buffer, "  emphasis: on\n");
1568 	} else {
1569 		snd_iprintf(buffer, "  emphasis: off\n");
1570 	}
1571 }
1572 
1573 static void __devinit snd_rme32_proc_init(struct rme32 * rme32)
1574 {
1575 	struct snd_info_entry *entry;
1576 
1577 	if (! snd_card_proc_new(rme32->card, "rme32", &entry))
1578 		snd_info_set_text_ops(entry, rme32, snd_rme32_proc_read);
1579 }
1580 
1581 /*
1582  * control interface
1583  */
1584 
1585 static int
1586 snd_rme32_info_loopback_control(struct snd_kcontrol *kcontrol,
1587 				struct snd_ctl_elem_info *uinfo)
1588 {
1589 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1590 	uinfo->count = 1;
1591 	uinfo->value.integer.min = 0;
1592 	uinfo->value.integer.max = 1;
1593 	return 0;
1594 }
1595 static int
1596 snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1597 			       struct snd_ctl_elem_value *ucontrol)
1598 {
1599 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1600 
1601 	spin_lock_irq(&rme32->lock);
1602 	ucontrol->value.integer.value[0] =
1603 	    rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1604 	spin_unlock_irq(&rme32->lock);
1605 	return 0;
1606 }
1607 static int
1608 snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1609 			       struct snd_ctl_elem_value *ucontrol)
1610 {
1611 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1612 	unsigned int val;
1613 	int change;
1614 
1615 	val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1616 	spin_lock_irq(&rme32->lock);
1617 	val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1618 	change = val != rme32->wcreg;
1619 	if (ucontrol->value.integer.value[0])
1620 		val &= ~RME32_WCR_MUTE;
1621 	else
1622 		val |= RME32_WCR_MUTE;
1623 	rme32->wcreg = val;
1624 	writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1625 	spin_unlock_irq(&rme32->lock);
1626 	return change;
1627 }
1628 
1629 static int
1630 snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1631 				 struct snd_ctl_elem_info *uinfo)
1632 {
1633 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1634 	static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" };
1635 
1636 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1637 	uinfo->count = 1;
1638 	switch (rme32->pci->device) {
1639 	case PCI_DEVICE_ID_RME_DIGI32:
1640 	case PCI_DEVICE_ID_RME_DIGI32_8:
1641 		uinfo->value.enumerated.items = 3;
1642 		break;
1643 	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1644 		uinfo->value.enumerated.items = 4;
1645 		break;
1646 	default:
1647 		snd_BUG();
1648 		break;
1649 	}
1650 	if (uinfo->value.enumerated.item >
1651 	    uinfo->value.enumerated.items - 1) {
1652 		uinfo->value.enumerated.item =
1653 		    uinfo->value.enumerated.items - 1;
1654 	}
1655 	strcpy(uinfo->value.enumerated.name,
1656 	       texts[uinfo->value.enumerated.item]);
1657 	return 0;
1658 }
1659 static int
1660 snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1661 				struct snd_ctl_elem_value *ucontrol)
1662 {
1663 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1664 	unsigned int items = 3;
1665 
1666 	spin_lock_irq(&rme32->lock);
1667 	ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1668 
1669 	switch (rme32->pci->device) {
1670 	case PCI_DEVICE_ID_RME_DIGI32:
1671 	case PCI_DEVICE_ID_RME_DIGI32_8:
1672 		items = 3;
1673 		break;
1674 	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1675 		items = 4;
1676 		break;
1677 	default:
1678 		snd_BUG();
1679 		break;
1680 	}
1681 	if (ucontrol->value.enumerated.item[0] >= items) {
1682 		ucontrol->value.enumerated.item[0] = items - 1;
1683 	}
1684 
1685 	spin_unlock_irq(&rme32->lock);
1686 	return 0;
1687 }
1688 static int
1689 snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1690 				struct snd_ctl_elem_value *ucontrol)
1691 {
1692 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1693 	unsigned int val;
1694 	int change, items = 3;
1695 
1696 	switch (rme32->pci->device) {
1697 	case PCI_DEVICE_ID_RME_DIGI32:
1698 	case PCI_DEVICE_ID_RME_DIGI32_8:
1699 		items = 3;
1700 		break;
1701 	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1702 		items = 4;
1703 		break;
1704 	default:
1705 		snd_BUG();
1706 		break;
1707 	}
1708 	val = ucontrol->value.enumerated.item[0] % items;
1709 
1710 	spin_lock_irq(&rme32->lock);
1711 	change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1712 	snd_rme32_setinputtype(rme32, val);
1713 	spin_unlock_irq(&rme32->lock);
1714 	return change;
1715 }
1716 
1717 static int
1718 snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1719 				 struct snd_ctl_elem_info *uinfo)
1720 {
1721 	static char *texts[4] = { "AutoSync",
1722 				  "Internal 32.0kHz",
1723 				  "Internal 44.1kHz",
1724 				  "Internal 48.0kHz" };
1725 
1726 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1727 	uinfo->count = 1;
1728 	uinfo->value.enumerated.items = 4;
1729 	if (uinfo->value.enumerated.item > 3) {
1730 		uinfo->value.enumerated.item = 3;
1731 	}
1732 	strcpy(uinfo->value.enumerated.name,
1733 	       texts[uinfo->value.enumerated.item]);
1734 	return 0;
1735 }
1736 static int
1737 snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1738 				struct snd_ctl_elem_value *ucontrol)
1739 {
1740 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1741 
1742 	spin_lock_irq(&rme32->lock);
1743 	ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1744 	spin_unlock_irq(&rme32->lock);
1745 	return 0;
1746 }
1747 static int
1748 snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1749 				struct snd_ctl_elem_value *ucontrol)
1750 {
1751 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1752 	unsigned int val;
1753 	int change;
1754 
1755 	val = ucontrol->value.enumerated.item[0] % 3;
1756 	spin_lock_irq(&rme32->lock);
1757 	change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1758 	snd_rme32_setclockmode(rme32, val);
1759 	spin_unlock_irq(&rme32->lock);
1760 	return change;
1761 }
1762 
1763 static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1764 {
1765 	u32 val = 0;
1766 	val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1767 	if (val & RME32_WCR_PRO)
1768 		val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1769 	else
1770 		val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1771 	return val;
1772 }
1773 
1774 static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1775 {
1776 	aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1777 	if (val & RME32_WCR_PRO)
1778 		aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1779 	else
1780 		aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1781 }
1782 
1783 static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1784 					struct snd_ctl_elem_info *uinfo)
1785 {
1786 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1787 	uinfo->count = 1;
1788 	return 0;
1789 }
1790 
1791 static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1792 				       struct snd_ctl_elem_value *ucontrol)
1793 {
1794 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1795 
1796 	snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1797 				 rme32->wcreg_spdif);
1798 	return 0;
1799 }
1800 
1801 static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1802 				       struct snd_ctl_elem_value *ucontrol)
1803 {
1804 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1805 	int change;
1806 	u32 val;
1807 
1808 	val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1809 	spin_lock_irq(&rme32->lock);
1810 	change = val != rme32->wcreg_spdif;
1811 	rme32->wcreg_spdif = val;
1812 	spin_unlock_irq(&rme32->lock);
1813 	return change;
1814 }
1815 
1816 static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1817 					       struct snd_ctl_elem_info *uinfo)
1818 {
1819 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1820 	uinfo->count = 1;
1821 	return 0;
1822 }
1823 
1824 static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1825 					      struct snd_ctl_elem_value *
1826 					      ucontrol)
1827 {
1828 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1829 
1830 	snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1831 				 rme32->wcreg_spdif_stream);
1832 	return 0;
1833 }
1834 
1835 static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1836 					      struct snd_ctl_elem_value *
1837 					      ucontrol)
1838 {
1839 	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1840 	int change;
1841 	u32 val;
1842 
1843 	val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1844 	spin_lock_irq(&rme32->lock);
1845 	change = val != rme32->wcreg_spdif_stream;
1846 	rme32->wcreg_spdif_stream = val;
1847 	rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1848 	rme32->wcreg |= val;
1849 	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1850 	spin_unlock_irq(&rme32->lock);
1851 	return change;
1852 }
1853 
1854 static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1855 					     struct snd_ctl_elem_info *uinfo)
1856 {
1857 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1858 	uinfo->count = 1;
1859 	return 0;
1860 }
1861 
1862 static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1863 					    struct snd_ctl_elem_value *
1864 					    ucontrol)
1865 {
1866 	ucontrol->value.iec958.status[0] = kcontrol->private_value;
1867 	return 0;
1868 }
1869 
1870 static struct snd_kcontrol_new snd_rme32_controls[] = {
1871 	{
1872 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1873 		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1874 		.info =	snd_rme32_control_spdif_info,
1875 		.get =	snd_rme32_control_spdif_get,
1876 		.put =	snd_rme32_control_spdif_put
1877 	},
1878 	{
1879 		.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1880 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1881 		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1882 		.info =	snd_rme32_control_spdif_stream_info,
1883 		.get =	snd_rme32_control_spdif_stream_get,
1884 		.put =	snd_rme32_control_spdif_stream_put
1885 	},
1886 	{
1887 		.access = SNDRV_CTL_ELEM_ACCESS_READ,
1888 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1889 		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1890 		.info =	snd_rme32_control_spdif_mask_info,
1891 		.get =	snd_rme32_control_spdif_mask_get,
1892 		.private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1893 	},
1894 	{
1895 		.access = SNDRV_CTL_ELEM_ACCESS_READ,
1896 		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1897 		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1898 		.info =	snd_rme32_control_spdif_mask_info,
1899 		.get =	snd_rme32_control_spdif_mask_get,
1900 		.private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1901 	},
1902 	{
1903 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1904 		.name =	"Input Connector",
1905 		.info =	snd_rme32_info_inputtype_control,
1906 		.get =	snd_rme32_get_inputtype_control,
1907 		.put =	snd_rme32_put_inputtype_control
1908 	},
1909 	{
1910 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1911 		.name =	"Loopback Input",
1912 		.info =	snd_rme32_info_loopback_control,
1913 		.get =	snd_rme32_get_loopback_control,
1914 		.put =	snd_rme32_put_loopback_control
1915 	},
1916 	{
1917 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1918 		.name =	"Sample Clock Source",
1919 		.info =	snd_rme32_info_clockmode_control,
1920 		.get =	snd_rme32_get_clockmode_control,
1921 		.put =	snd_rme32_put_clockmode_control
1922 	}
1923 };
1924 
1925 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1926 {
1927 	int idx, err;
1928 	struct snd_kcontrol *kctl;
1929 
1930 	for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1931 		if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
1932 			return err;
1933 		if (idx == 1)	/* IEC958 (S/PDIF) Stream */
1934 			rme32->spdif_ctl = kctl;
1935 	}
1936 
1937 	return 0;
1938 }
1939 
1940 /*
1941  * Card initialisation
1942  */
1943 
1944 static void snd_rme32_card_free(struct snd_card *card)
1945 {
1946 	snd_rme32_free(card->private_data);
1947 }
1948 
1949 static int __devinit
1950 snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1951 {
1952 	static int dev;
1953 	struct rme32 *rme32;
1954 	struct snd_card *card;
1955 	int err;
1956 
1957 	if (dev >= SNDRV_CARDS) {
1958 		return -ENODEV;
1959 	}
1960 	if (!enable[dev]) {
1961 		dev++;
1962 		return -ENOENT;
1963 	}
1964 
1965 	if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
1966 				 sizeof(struct rme32))) == NULL)
1967 		return -ENOMEM;
1968 	card->private_free = snd_rme32_card_free;
1969 	rme32 = (struct rme32 *) card->private_data;
1970 	rme32->card = card;
1971 	rme32->pci = pci;
1972 	snd_card_set_dev(card, &pci->dev);
1973         if (fullduplex[dev])
1974 		rme32->fullduplex_mode = 1;
1975 	if ((err = snd_rme32_create(rme32)) < 0) {
1976 		snd_card_free(card);
1977 		return err;
1978 	}
1979 
1980 	strcpy(card->driver, "Digi32");
1981 	switch (rme32->pci->device) {
1982 	case PCI_DEVICE_ID_RME_DIGI32:
1983 		strcpy(card->shortname, "RME Digi32");
1984 		break;
1985 	case PCI_DEVICE_ID_RME_DIGI32_8:
1986 		strcpy(card->shortname, "RME Digi32/8");
1987 		break;
1988 	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1989 		strcpy(card->shortname, "RME Digi32 PRO");
1990 		break;
1991 	}
1992 	sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1993 		card->shortname, rme32->rev, rme32->port, rme32->irq);
1994 
1995 	if ((err = snd_card_register(card)) < 0) {
1996 		snd_card_free(card);
1997 		return err;
1998 	}
1999 	pci_set_drvdata(pci, card);
2000 	dev++;
2001 	return 0;
2002 }
2003 
2004 static void __devexit snd_rme32_remove(struct pci_dev *pci)
2005 {
2006 	snd_card_free(pci_get_drvdata(pci));
2007 	pci_set_drvdata(pci, NULL);
2008 }
2009 
2010 static struct pci_driver driver = {
2011 	.name =		"RME Digi32",
2012 	.id_table =	snd_rme32_ids,
2013 	.probe =	snd_rme32_probe,
2014 	.remove =	__devexit_p(snd_rme32_remove),
2015 };
2016 
2017 static int __init alsa_card_rme32_init(void)
2018 {
2019 	return pci_register_driver(&driver);
2020 }
2021 
2022 static void __exit alsa_card_rme32_exit(void)
2023 {
2024 	pci_unregister_driver(&driver);
2025 }
2026 
2027 module_init(alsa_card_rme32_init)
2028 module_exit(alsa_card_rme32_exit)
2029