1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 266410bfdSClemens Ladisch #define CS4245_CHIP_ID 0x01 366410bfdSClemens Ladisch #define CS4245_POWER_CTRL 0x02 466410bfdSClemens Ladisch #define CS4245_DAC_CTRL_1 0x03 566410bfdSClemens Ladisch #define CS4245_ADC_CTRL 0x04 666410bfdSClemens Ladisch #define CS4245_MCLK_FREQ 0x05 766410bfdSClemens Ladisch #define CS4245_SIGNAL_SEL 0x06 866410bfdSClemens Ladisch #define CS4245_PGA_B_CTRL 0x07 966410bfdSClemens Ladisch #define CS4245_PGA_A_CTRL 0x08 1066410bfdSClemens Ladisch #define CS4245_ANALOG_IN 0x09 1166410bfdSClemens Ladisch #define CS4245_DAC_A_CTRL 0x0a 1266410bfdSClemens Ladisch #define CS4245_DAC_B_CTRL 0x0b 1366410bfdSClemens Ladisch #define CS4245_DAC_CTRL_2 0x0c 1466410bfdSClemens Ladisch #define CS4245_INT_STATUS 0x0d 1566410bfdSClemens Ladisch #define CS4245_INT_MASK 0x0e 1666410bfdSClemens Ladisch #define CS4245_INT_MODE_MSB 0x0f 1766410bfdSClemens Ladisch #define CS4245_INT_MODE_LSB 0x10 1866410bfdSClemens Ladisch 1966410bfdSClemens Ladisch /* Chip ID */ 2066410bfdSClemens Ladisch #define CS4245_CHIP_PART_MASK 0xf0 2166410bfdSClemens Ladisch #define CS4245_CHIP_REV_MASK 0x0f 2266410bfdSClemens Ladisch 2366410bfdSClemens Ladisch /* Power Control */ 2466410bfdSClemens Ladisch #define CS4245_FREEZE 0x80 2566410bfdSClemens Ladisch #define CS4245_PDN_MIC 0x08 2666410bfdSClemens Ladisch #define CS4245_PDN_ADC 0x04 2766410bfdSClemens Ladisch #define CS4245_PDN_DAC 0x02 2866410bfdSClemens Ladisch #define CS4245_PDN 0x01 2966410bfdSClemens Ladisch 3066410bfdSClemens Ladisch /* DAC Control */ 3166410bfdSClemens Ladisch #define CS4245_DAC_FM_MASK 0xc0 3266410bfdSClemens Ladisch #define CS4245_DAC_FM_SINGLE 0x00 3366410bfdSClemens Ladisch #define CS4245_DAC_FM_DOUBLE 0x40 3466410bfdSClemens Ladisch #define CS4245_DAC_FM_QUAD 0x80 3566410bfdSClemens Ladisch #define CS4245_DAC_DIF_MASK 0x30 3666410bfdSClemens Ladisch #define CS4245_DAC_DIF_LJUST 0x00 3766410bfdSClemens Ladisch #define CS4245_DAC_DIF_I2S 0x10 3866410bfdSClemens Ladisch #define CS4245_DAC_DIF_RJUST_16 0x20 3966410bfdSClemens Ladisch #define CS4245_DAC_DIF_RJUST_24 0x30 4066410bfdSClemens Ladisch #define CS4245_RESERVED_1 0x08 4166410bfdSClemens Ladisch #define CS4245_MUTE_DAC 0x04 4266410bfdSClemens Ladisch #define CS4245_DEEMPH 0x02 4366410bfdSClemens Ladisch #define CS4245_DAC_MASTER 0x01 4466410bfdSClemens Ladisch 4566410bfdSClemens Ladisch /* ADC Control */ 4666410bfdSClemens Ladisch #define CS4245_ADC_FM_MASK 0xc0 4766410bfdSClemens Ladisch #define CS4245_ADC_FM_SINGLE 0x00 4866410bfdSClemens Ladisch #define CS4245_ADC_FM_DOUBLE 0x40 4966410bfdSClemens Ladisch #define CS4245_ADC_FM_QUAD 0x80 5066410bfdSClemens Ladisch #define CS4245_ADC_DIF_MASK 0x10 5166410bfdSClemens Ladisch #define CS4245_ADC_DIF_LJUST 0x00 5266410bfdSClemens Ladisch #define CS4245_ADC_DIF_I2S 0x10 5366410bfdSClemens Ladisch #define CS4245_MUTE_ADC 0x04 5466410bfdSClemens Ladisch #define CS4245_HPF_FREEZE 0x02 5566410bfdSClemens Ladisch #define CS4245_ADC_MASTER 0x01 5666410bfdSClemens Ladisch 5766410bfdSClemens Ladisch /* MCLK Frequency */ 5866410bfdSClemens Ladisch #define CS4245_MCLK1_MASK 0x70 5966410bfdSClemens Ladisch #define CS4245_MCLK1_SHIFT 4 6066410bfdSClemens Ladisch #define CS4245_MCLK2_MASK 0x07 6166410bfdSClemens Ladisch #define CS4245_MCLK2_SHIFT 0 6266410bfdSClemens Ladisch #define CS4245_MCLK_1 0 6366410bfdSClemens Ladisch #define CS4245_MCLK_1_5 1 6466410bfdSClemens Ladisch #define CS4245_MCLK_2 2 6566410bfdSClemens Ladisch #define CS4245_MCLK_3 3 6666410bfdSClemens Ladisch #define CS4245_MCLK_4 4 6766410bfdSClemens Ladisch 6866410bfdSClemens Ladisch /* Signal Selection */ 6966410bfdSClemens Ladisch #define CS4245_A_OUT_SEL_MASK 0x60 7066410bfdSClemens Ladisch #define CS4245_A_OUT_SEL_HIZ 0x00 7166410bfdSClemens Ladisch #define CS4245_A_OUT_SEL_DAC 0x20 7266410bfdSClemens Ladisch #define CS4245_A_OUT_SEL_PGA 0x40 7366410bfdSClemens Ladisch #define CS4245_LOOP 0x02 7466410bfdSClemens Ladisch #define CS4245_ASYNCH 0x01 7566410bfdSClemens Ladisch 7666410bfdSClemens Ladisch /* Channel B/A PGA Control */ 7766410bfdSClemens Ladisch #define CS4245_PGA_GAIN_MASK 0x3f 7866410bfdSClemens Ladisch 7966410bfdSClemens Ladisch /* ADC Input Control */ 8066410bfdSClemens Ladisch #define CS4245_PGA_SOFT 0x10 8166410bfdSClemens Ladisch #define CS4245_PGA_ZERO 0x08 8266410bfdSClemens Ladisch #define CS4245_SEL_MASK 0x07 8366410bfdSClemens Ladisch #define CS4245_SEL_MIC 0x00 8466410bfdSClemens Ladisch #define CS4245_SEL_INPUT_1 0x01 8566410bfdSClemens Ladisch #define CS4245_SEL_INPUT_2 0x02 8666410bfdSClemens Ladisch #define CS4245_SEL_INPUT_3 0x03 8766410bfdSClemens Ladisch #define CS4245_SEL_INPUT_4 0x04 8866410bfdSClemens Ladisch #define CS4245_SEL_INPUT_5 0x05 8966410bfdSClemens Ladisch #define CS4245_SEL_INPUT_6 0x06 9066410bfdSClemens Ladisch 9166410bfdSClemens Ladisch /* DAC Channel A/B Volume Control */ 9266410bfdSClemens Ladisch #define CS4245_VOL_MASK 0xff 9366410bfdSClemens Ladisch 9466410bfdSClemens Ladisch /* DAC Control 2 */ 9566410bfdSClemens Ladisch #define CS4245_DAC_SOFT 0x80 9666410bfdSClemens Ladisch #define CS4245_DAC_ZERO 0x40 9766410bfdSClemens Ladisch #define CS4245_INVERT_DAC 0x20 9866410bfdSClemens Ladisch #define CS4245_INT_ACTIVE_HIGH 0x01 9966410bfdSClemens Ladisch 10066410bfdSClemens Ladisch /* Interrupt Status/Mask/Mode */ 10166410bfdSClemens Ladisch #define CS4245_ADC_CLK_ERR 0x08 10266410bfdSClemens Ladisch #define CS4245_DAC_CLK_ERR 0x04 10366410bfdSClemens Ladisch #define CS4245_ADC_OVFL 0x02 10466410bfdSClemens Ladisch #define CS4245_ADC_UNDRFL 0x01 10566410bfdSClemens Ladisch 106bed61935SRoman Volkov #define CS4245_SPI_ADDRESS_S (0x9e << 16) 107bed61935SRoman Volkov #define CS4245_SPI_WRITE_S (0 << 16) 10866410bfdSClemens Ladisch 109bed61935SRoman Volkov #define CS4245_SPI_ADDRESS 0x9e 110bed61935SRoman Volkov #define CS4245_SPI_WRITE 0 111bed61935SRoman Volkov #define CS4245_SPI_READ 1 112