1 /* 2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards. 3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net> 4 * Takashi Iwai <tiwai@suse.de> 5 * 6 * Most of the hardware init stuffs are based on maestro3 driver for 7 * OSS/Free by Zach Brown. Many thanks to Zach! 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 * 24 * ChangeLog: 25 * Aug. 27, 2001 26 * - Fixed deadlock on capture 27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org> 28 * 29 */ 30 31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2" 32 #define DRIVER_NAME "Maestro3" 33 34 #include <sound/driver.h> 35 #include <asm/io.h> 36 #include <linux/delay.h> 37 #include <linux/interrupt.h> 38 #include <linux/init.h> 39 #include <linux/pci.h> 40 #include <linux/slab.h> 41 #include <linux/vmalloc.h> 42 #include <linux/moduleparam.h> 43 #include <sound/core.h> 44 #include <sound/info.h> 45 #include <sound/control.h> 46 #include <sound/pcm.h> 47 #include <sound/mpu401.h> 48 #include <sound/ac97_codec.h> 49 #include <sound/initval.h> 50 51 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>"); 52 MODULE_DESCRIPTION("ESS Maestro3 PCI"); 53 MODULE_LICENSE("GPL"); 54 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI}," 55 "{ESS,ES1988}," 56 "{ESS,Allegro PCI}," 57 "{ESS,Allegro-1 PCI}," 58 "{ESS,Canyon3D-2/LE PCI}}"); 59 60 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 61 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 62 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */ 63 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1}; 64 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1}; 65 66 module_param_array(index, int, NULL, 0444); 67 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); 68 module_param_array(id, charp, NULL, 0444); 69 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); 70 module_param_array(enable, bool, NULL, 0444); 71 MODULE_PARM_DESC(enable, "Enable this soundcard."); 72 module_param_array(external_amp, bool, NULL, 0444); 73 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard."); 74 module_param_array(amp_gpio, int, NULL, 0444); 75 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)"); 76 77 #define MAX_PLAYBACKS 2 78 #define MAX_CAPTURES 1 79 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES) 80 81 82 /* 83 * maestro3 registers 84 */ 85 86 /* Allegro PCI configuration registers */ 87 #define PCI_LEGACY_AUDIO_CTRL 0x40 88 #define SOUND_BLASTER_ENABLE 0x00000001 89 #define FM_SYNTHESIS_ENABLE 0x00000002 90 #define GAME_PORT_ENABLE 0x00000004 91 #define MPU401_IO_ENABLE 0x00000008 92 #define MPU401_IRQ_ENABLE 0x00000010 93 #define ALIAS_10BIT_IO 0x00000020 94 #define SB_DMA_MASK 0x000000C0 95 #define SB_DMA_0 0x00000040 96 #define SB_DMA_1 0x00000040 97 #define SB_DMA_R 0x00000080 98 #define SB_DMA_3 0x000000C0 99 #define SB_IRQ_MASK 0x00000700 100 #define SB_IRQ_5 0x00000000 101 #define SB_IRQ_7 0x00000100 102 #define SB_IRQ_9 0x00000200 103 #define SB_IRQ_10 0x00000300 104 #define MIDI_IRQ_MASK 0x00003800 105 #define SERIAL_IRQ_ENABLE 0x00004000 106 #define DISABLE_LEGACY 0x00008000 107 108 #define PCI_ALLEGRO_CONFIG 0x50 109 #define SB_ADDR_240 0x00000004 110 #define MPU_ADDR_MASK 0x00000018 111 #define MPU_ADDR_330 0x00000000 112 #define MPU_ADDR_300 0x00000008 113 #define MPU_ADDR_320 0x00000010 114 #define MPU_ADDR_340 0x00000018 115 #define USE_PCI_TIMING 0x00000040 116 #define POSTED_WRITE_ENABLE 0x00000080 117 #define DMA_POLICY_MASK 0x00000700 118 #define DMA_DDMA 0x00000000 119 #define DMA_TDMA 0x00000100 120 #define DMA_PCPCI 0x00000200 121 #define DMA_WBDMA16 0x00000400 122 #define DMA_WBDMA4 0x00000500 123 #define DMA_WBDMA2 0x00000600 124 #define DMA_WBDMA1 0x00000700 125 #define DMA_SAFE_GUARD 0x00000800 126 #define HI_PERF_GP_ENABLE 0x00001000 127 #define PIC_SNOOP_MODE_0 0x00002000 128 #define PIC_SNOOP_MODE_1 0x00004000 129 #define SOUNDBLASTER_IRQ_MASK 0x00008000 130 #define RING_IN_ENABLE 0x00010000 131 #define SPDIF_TEST_MODE 0x00020000 132 #define CLK_MULT_MODE_SELECT_2 0x00040000 133 #define EEPROM_WRITE_ENABLE 0x00080000 134 #define CODEC_DIR_IN 0x00100000 135 #define HV_BUTTON_FROM_GD 0x00200000 136 #define REDUCED_DEBOUNCE 0x00400000 137 #define HV_CTRL_ENABLE 0x00800000 138 #define SPDIF_ENABLE 0x01000000 139 #define CLK_DIV_SELECT 0x06000000 140 #define CLK_DIV_BY_48 0x00000000 141 #define CLK_DIV_BY_49 0x02000000 142 #define CLK_DIV_BY_50 0x04000000 143 #define CLK_DIV_RESERVED 0x06000000 144 #define PM_CTRL_ENABLE 0x08000000 145 #define CLK_MULT_MODE_SELECT 0x30000000 146 #define CLK_MULT_MODE_SHIFT 28 147 #define CLK_MULT_MODE_0 0x00000000 148 #define CLK_MULT_MODE_1 0x10000000 149 #define CLK_MULT_MODE_2 0x20000000 150 #define CLK_MULT_MODE_3 0x30000000 151 #define INT_CLK_SELECT 0x40000000 152 #define INT_CLK_MULT_RESET 0x80000000 153 154 /* M3 */ 155 #define INT_CLK_SRC_NOT_PCI 0x00100000 156 #define INT_CLK_MULT_ENABLE 0x80000000 157 158 #define PCI_ACPI_CONTROL 0x54 159 #define PCI_ACPI_D0 0x00000000 160 #define PCI_ACPI_D1 0xB4F70000 161 #define PCI_ACPI_D2 0xB4F7B4F7 162 163 #define PCI_USER_CONFIG 0x58 164 #define EXT_PCI_MASTER_ENABLE 0x00000001 165 #define SPDIF_OUT_SELECT 0x00000002 166 #define TEST_PIN_DIR_CTRL 0x00000004 167 #define AC97_CODEC_TEST 0x00000020 168 #define TRI_STATE_BUFFER 0x00000080 169 #define IN_CLK_12MHZ_SELECT 0x00000100 170 #define MULTI_FUNC_DISABLE 0x00000200 171 #define EXT_MASTER_PAIR_SEL 0x00000400 172 #define PCI_MASTER_SUPPORT 0x00000800 173 #define STOP_CLOCK_ENABLE 0x00001000 174 #define EAPD_DRIVE_ENABLE 0x00002000 175 #define REQ_TRI_STATE_ENABLE 0x00004000 176 #define REQ_LOW_ENABLE 0x00008000 177 #define MIDI_1_ENABLE 0x00010000 178 #define MIDI_2_ENABLE 0x00020000 179 #define SB_AUDIO_SYNC 0x00040000 180 #define HV_CTRL_TEST 0x00100000 181 #define SOUNDBLASTER_TEST 0x00400000 182 183 #define PCI_USER_CONFIG_C 0x5C 184 185 #define PCI_DDMA_CTRL 0x60 186 #define DDMA_ENABLE 0x00000001 187 188 189 /* Allegro registers */ 190 #define HOST_INT_CTRL 0x18 191 #define SB_INT_ENABLE 0x0001 192 #define MPU401_INT_ENABLE 0x0002 193 #define ASSP_INT_ENABLE 0x0010 194 #define RING_INT_ENABLE 0x0020 195 #define HV_INT_ENABLE 0x0040 196 #define CLKRUN_GEN_ENABLE 0x0100 197 #define HV_CTRL_TO_PME 0x0400 198 #define SOFTWARE_RESET_ENABLE 0x8000 199 200 /* 201 * should be using the above defines, probably. 202 */ 203 #define REGB_ENABLE_RESET 0x01 204 #define REGB_STOP_CLOCK 0x10 205 206 #define HOST_INT_STATUS 0x1A 207 #define SB_INT_PENDING 0x01 208 #define MPU401_INT_PENDING 0x02 209 #define ASSP_INT_PENDING 0x10 210 #define RING_INT_PENDING 0x20 211 #define HV_INT_PENDING 0x40 212 213 #define HARDWARE_VOL_CTRL 0x1B 214 #define SHADOW_MIX_REG_VOICE 0x1C 215 #define HW_VOL_COUNTER_VOICE 0x1D 216 #define SHADOW_MIX_REG_MASTER 0x1E 217 #define HW_VOL_COUNTER_MASTER 0x1F 218 219 #define CODEC_COMMAND 0x30 220 #define CODEC_READ_B 0x80 221 222 #define CODEC_STATUS 0x30 223 #define CODEC_BUSY_B 0x01 224 225 #define CODEC_DATA 0x32 226 227 #define RING_BUS_CTRL_A 0x36 228 #define RAC_PME_ENABLE 0x0100 229 #define RAC_SDFS_ENABLE 0x0200 230 #define LAC_PME_ENABLE 0x0400 231 #define LAC_SDFS_ENABLE 0x0800 232 #define SERIAL_AC_LINK_ENABLE 0x1000 233 #define IO_SRAM_ENABLE 0x2000 234 #define IIS_INPUT_ENABLE 0x8000 235 236 #define RING_BUS_CTRL_B 0x38 237 #define SECOND_CODEC_ID_MASK 0x0003 238 #define SPDIF_FUNC_ENABLE 0x0010 239 #define SECOND_AC_ENABLE 0x0020 240 #define SB_MODULE_INTF_ENABLE 0x0040 241 #define SSPE_ENABLE 0x0040 242 #define M3I_DOCK_ENABLE 0x0080 243 244 #define SDO_OUT_DEST_CTRL 0x3A 245 #define COMMAND_ADDR_OUT 0x0003 246 #define PCM_LR_OUT_LOCAL 0x0000 247 #define PCM_LR_OUT_REMOTE 0x0004 248 #define PCM_LR_OUT_MUTE 0x0008 249 #define PCM_LR_OUT_BOTH 0x000C 250 #define LINE1_DAC_OUT_LOCAL 0x0000 251 #define LINE1_DAC_OUT_REMOTE 0x0010 252 #define LINE1_DAC_OUT_MUTE 0x0020 253 #define LINE1_DAC_OUT_BOTH 0x0030 254 #define PCM_CLS_OUT_LOCAL 0x0000 255 #define PCM_CLS_OUT_REMOTE 0x0040 256 #define PCM_CLS_OUT_MUTE 0x0080 257 #define PCM_CLS_OUT_BOTH 0x00C0 258 #define PCM_RLF_OUT_LOCAL 0x0000 259 #define PCM_RLF_OUT_REMOTE 0x0100 260 #define PCM_RLF_OUT_MUTE 0x0200 261 #define PCM_RLF_OUT_BOTH 0x0300 262 #define LINE2_DAC_OUT_LOCAL 0x0000 263 #define LINE2_DAC_OUT_REMOTE 0x0400 264 #define LINE2_DAC_OUT_MUTE 0x0800 265 #define LINE2_DAC_OUT_BOTH 0x0C00 266 #define HANDSET_OUT_LOCAL 0x0000 267 #define HANDSET_OUT_REMOTE 0x1000 268 #define HANDSET_OUT_MUTE 0x2000 269 #define HANDSET_OUT_BOTH 0x3000 270 #define IO_CTRL_OUT_LOCAL 0x0000 271 #define IO_CTRL_OUT_REMOTE 0x4000 272 #define IO_CTRL_OUT_MUTE 0x8000 273 #define IO_CTRL_OUT_BOTH 0xC000 274 275 #define SDO_IN_DEST_CTRL 0x3C 276 #define STATUS_ADDR_IN 0x0003 277 #define PCM_LR_IN_LOCAL 0x0000 278 #define PCM_LR_IN_REMOTE 0x0004 279 #define PCM_LR_RESERVED 0x0008 280 #define PCM_LR_IN_BOTH 0x000C 281 #define LINE1_ADC_IN_LOCAL 0x0000 282 #define LINE1_ADC_IN_REMOTE 0x0010 283 #define LINE1_ADC_IN_MUTE 0x0020 284 #define MIC_ADC_IN_LOCAL 0x0000 285 #define MIC_ADC_IN_REMOTE 0x0040 286 #define MIC_ADC_IN_MUTE 0x0080 287 #define LINE2_DAC_IN_LOCAL 0x0000 288 #define LINE2_DAC_IN_REMOTE 0x0400 289 #define LINE2_DAC_IN_MUTE 0x0800 290 #define HANDSET_IN_LOCAL 0x0000 291 #define HANDSET_IN_REMOTE 0x1000 292 #define HANDSET_IN_MUTE 0x2000 293 #define IO_STATUS_IN_LOCAL 0x0000 294 #define IO_STATUS_IN_REMOTE 0x4000 295 296 #define SPDIF_IN_CTRL 0x3E 297 #define SPDIF_IN_ENABLE 0x0001 298 299 #define GPIO_DATA 0x60 300 #define GPIO_DATA_MASK 0x0FFF 301 #define GPIO_HV_STATUS 0x3000 302 #define GPIO_PME_STATUS 0x4000 303 304 #define GPIO_MASK 0x64 305 #define GPIO_DIRECTION 0x68 306 #define GPO_PRIMARY_AC97 0x0001 307 #define GPI_LINEOUT_SENSE 0x0004 308 #define GPO_SECONDARY_AC97 0x0008 309 #define GPI_VOL_DOWN 0x0010 310 #define GPI_VOL_UP 0x0020 311 #define GPI_IIS_CLK 0x0040 312 #define GPI_IIS_LRCLK 0x0080 313 #define GPI_IIS_DATA 0x0100 314 #define GPI_DOCKING_STATUS 0x0100 315 #define GPI_HEADPHONE_SENSE 0x0200 316 #define GPO_EXT_AMP_SHUTDOWN 0x1000 317 318 #define GPO_EXT_AMP_M3 1 /* default m3 amp */ 319 #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */ 320 321 /* M3 */ 322 #define GPO_M3_EXT_AMP_SHUTDN 0x0002 323 324 #define ASSP_INDEX_PORT 0x80 325 #define ASSP_MEMORY_PORT 0x82 326 #define ASSP_DATA_PORT 0x84 327 328 #define MPU401_DATA_PORT 0x98 329 #define MPU401_STATUS_PORT 0x99 330 331 #define CLK_MULT_DATA_PORT 0x9C 332 333 #define ASSP_CONTROL_A 0xA2 334 #define ASSP_0_WS_ENABLE 0x01 335 #define ASSP_CTRL_A_RESERVED1 0x02 336 #define ASSP_CTRL_A_RESERVED2 0x04 337 #define ASSP_CLK_49MHZ_SELECT 0x08 338 #define FAST_PLU_ENABLE 0x10 339 #define ASSP_CTRL_A_RESERVED3 0x20 340 #define DSP_CLK_36MHZ_SELECT 0x40 341 342 #define ASSP_CONTROL_B 0xA4 343 #define RESET_ASSP 0x00 344 #define RUN_ASSP 0x01 345 #define ENABLE_ASSP_CLOCK 0x00 346 #define STOP_ASSP_CLOCK 0x10 347 #define RESET_TOGGLE 0x40 348 349 #define ASSP_CONTROL_C 0xA6 350 #define ASSP_HOST_INT_ENABLE 0x01 351 #define FM_ADDR_REMAP_DISABLE 0x02 352 #define HOST_WRITE_PORT_ENABLE 0x08 353 354 #define ASSP_HOST_INT_STATUS 0xAC 355 #define DSP2HOST_REQ_PIORECORD 0x01 356 #define DSP2HOST_REQ_I2SRATE 0x02 357 #define DSP2HOST_REQ_TIMER 0x04 358 359 /* AC97 registers */ 360 /* XXX fix this crap up */ 361 /*#define AC97_RESET 0x00*/ 362 363 #define AC97_VOL_MUTE_B 0x8000 364 #define AC97_VOL_M 0x1F 365 #define AC97_LEFT_VOL_S 8 366 367 #define AC97_MASTER_VOL 0x02 368 #define AC97_LINE_LEVEL_VOL 0x04 369 #define AC97_MASTER_MONO_VOL 0x06 370 #define AC97_PC_BEEP_VOL 0x0A 371 #define AC97_PC_BEEP_VOL_M 0x0F 372 #define AC97_SROUND_MASTER_VOL 0x38 373 #define AC97_PC_BEEP_VOL_S 1 374 375 /*#define AC97_PHONE_VOL 0x0C 376 #define AC97_MIC_VOL 0x0E*/ 377 #define AC97_MIC_20DB_ENABLE 0x40 378 379 /*#define AC97_LINEIN_VOL 0x10 380 #define AC97_CD_VOL 0x12 381 #define AC97_VIDEO_VOL 0x14 382 #define AC97_AUX_VOL 0x16*/ 383 #define AC97_PCM_OUT_VOL 0x18 384 /*#define AC97_RECORD_SELECT 0x1A*/ 385 #define AC97_RECORD_MIC 0x00 386 #define AC97_RECORD_CD 0x01 387 #define AC97_RECORD_VIDEO 0x02 388 #define AC97_RECORD_AUX 0x03 389 #define AC97_RECORD_MONO_MUX 0x02 390 #define AC97_RECORD_DIGITAL 0x03 391 #define AC97_RECORD_LINE 0x04 392 #define AC97_RECORD_STEREO 0x05 393 #define AC97_RECORD_MONO 0x06 394 #define AC97_RECORD_PHONE 0x07 395 396 /*#define AC97_RECORD_GAIN 0x1C*/ 397 #define AC97_RECORD_VOL_M 0x0F 398 399 /*#define AC97_GENERAL_PURPOSE 0x20*/ 400 #define AC97_POWER_DOWN_CTRL 0x26 401 #define AC97_ADC_READY 0x0001 402 #define AC97_DAC_READY 0x0002 403 #define AC97_ANALOG_READY 0x0004 404 #define AC97_VREF_ON 0x0008 405 #define AC97_PR0 0x0100 406 #define AC97_PR1 0x0200 407 #define AC97_PR2 0x0400 408 #define AC97_PR3 0x0800 409 #define AC97_PR4 0x1000 410 411 #define AC97_RESERVED1 0x28 412 413 #define AC97_VENDOR_TEST 0x5A 414 415 #define AC97_CLOCK_DELAY 0x5C 416 #define AC97_LINEOUT_MUX_SEL 0x0001 417 #define AC97_MONO_MUX_SEL 0x0002 418 #define AC97_CLOCK_DELAY_SEL 0x1F 419 #define AC97_DAC_CDS_SHIFT 6 420 #define AC97_ADC_CDS_SHIFT 11 421 422 #define AC97_MULTI_CHANNEL_SEL 0x74 423 424 /*#define AC97_VENDOR_ID1 0x7C 425 #define AC97_VENDOR_ID2 0x7E*/ 426 427 /* 428 * ASSP control regs 429 */ 430 #define DSP_PORT_TIMER_COUNT 0x06 431 432 #define DSP_PORT_MEMORY_INDEX 0x80 433 434 #define DSP_PORT_MEMORY_TYPE 0x82 435 #define MEMTYPE_INTERNAL_CODE 0x0002 436 #define MEMTYPE_INTERNAL_DATA 0x0003 437 #define MEMTYPE_MASK 0x0003 438 439 #define DSP_PORT_MEMORY_DATA 0x84 440 441 #define DSP_PORT_CONTROL_REG_A 0xA2 442 #define DSP_PORT_CONTROL_REG_B 0xA4 443 #define DSP_PORT_CONTROL_REG_C 0xA6 444 445 #define REV_A_CODE_MEMORY_BEGIN 0x0000 446 #define REV_A_CODE_MEMORY_END 0x0FFF 447 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 448 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) 449 450 #define REV_B_CODE_MEMORY_BEGIN 0x0000 451 #define REV_B_CODE_MEMORY_END 0x0BFF 452 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 453 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) 454 455 #define REV_A_DATA_MEMORY_BEGIN 0x1000 456 #define REV_A_DATA_MEMORY_END 0x2FFF 457 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 458 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) 459 460 #define REV_B_DATA_MEMORY_BEGIN 0x1000 461 #define REV_B_DATA_MEMORY_END 0x2BFF 462 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 463 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) 464 465 466 #define NUM_UNITS_KERNEL_CODE 16 467 #define NUM_UNITS_KERNEL_DATA 2 468 469 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 470 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 471 472 /* 473 * Kernel data layout 474 */ 475 476 #define DP_SHIFT_COUNT 7 477 478 #define KDATA_BASE_ADDR 0x1000 479 #define KDATA_BASE_ADDR2 0x1080 480 481 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) 482 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) 483 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) 484 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) 485 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) 486 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) 487 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) 488 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) 489 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) 490 491 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) 492 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) 493 494 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) 495 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) 496 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) 497 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) 498 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) 499 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) 500 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) 501 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) 502 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) 503 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) 504 505 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) 506 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) 507 508 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) 509 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) 510 511 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) 512 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) 513 514 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) 515 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) 516 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) 517 518 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) 519 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) 520 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) 521 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) 522 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) 523 524 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) 525 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) 526 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) 527 528 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) 529 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) 530 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) 531 532 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) 533 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) 534 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) 535 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) 536 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) 537 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) 538 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) 539 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) 540 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) 541 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) 542 543 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) 544 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) 545 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) 546 547 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) 548 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) 549 550 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) 551 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) 552 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) 553 554 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) 555 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) 556 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) 557 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) 558 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) 559 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) 560 561 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) 562 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) 563 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) 564 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) 565 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) 566 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) 567 568 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) 569 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) 570 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) 571 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) 572 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) 573 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) 574 575 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) 576 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) 577 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) 578 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) 579 580 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) 581 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) 582 583 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) 584 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) 585 586 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) 587 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) 588 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) 589 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) 590 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) 591 592 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) 593 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) 594 595 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) 596 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) 597 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) 598 599 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) 600 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) 601 602 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) 603 604 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) 605 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) 606 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) 607 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) 608 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) 609 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) 610 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) 611 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) 612 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) 613 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) 614 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) 615 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) 616 617 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) 618 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) 619 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) 620 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) 621 622 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) 623 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) 624 625 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) 626 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) 627 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) 628 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) 629 630 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) 631 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) 632 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) 633 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) 634 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) 635 636 /* 637 * second 'segment' (?) reserved for mixer 638 * buffers.. 639 */ 640 641 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) 642 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) 643 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) 644 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) 645 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) 646 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) 647 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) 648 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) 649 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) 650 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) 651 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) 652 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) 653 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) 654 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) 655 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) 656 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) 657 658 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) 659 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) 660 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) 661 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) 662 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) 663 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) 664 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) 665 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) 666 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) 667 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) 668 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) 669 670 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) 671 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) 672 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) 673 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) 674 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) 675 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) 676 677 #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC) 678 #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0) 679 #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0) 680 #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0) 681 682 /* 683 * client data area offsets 684 */ 685 #define CDATA_INSTANCE_READY 0x00 686 687 #define CDATA_HOST_SRC_ADDRL 0x01 688 #define CDATA_HOST_SRC_ADDRH 0x02 689 #define CDATA_HOST_SRC_END_PLUS_1L 0x03 690 #define CDATA_HOST_SRC_END_PLUS_1H 0x04 691 #define CDATA_HOST_SRC_CURRENTL 0x05 692 #define CDATA_HOST_SRC_CURRENTH 0x06 693 694 #define CDATA_IN_BUF_CONNECT 0x07 695 #define CDATA_OUT_BUF_CONNECT 0x08 696 697 #define CDATA_IN_BUF_BEGIN 0x09 698 #define CDATA_IN_BUF_END_PLUS_1 0x0A 699 #define CDATA_IN_BUF_HEAD 0x0B 700 #define CDATA_IN_BUF_TAIL 0x0C 701 #define CDATA_OUT_BUF_BEGIN 0x0D 702 #define CDATA_OUT_BUF_END_PLUS_1 0x0E 703 #define CDATA_OUT_BUF_HEAD 0x0F 704 #define CDATA_OUT_BUF_TAIL 0x10 705 706 #define CDATA_DMA_CONTROL 0x11 707 #define CDATA_RESERVED 0x12 708 709 #define CDATA_FREQUENCY 0x13 710 #define CDATA_LEFT_VOLUME 0x14 711 #define CDATA_RIGHT_VOLUME 0x15 712 #define CDATA_LEFT_SUR_VOL 0x16 713 #define CDATA_RIGHT_SUR_VOL 0x17 714 715 #define CDATA_HEADER_LEN 0x18 716 717 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN 718 #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1) 719 #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2) 720 #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3) 721 #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8) 722 #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10) 723 #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16) 724 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17) 725 726 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) 727 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) 728 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) 729 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) 730 #define MINISRC_BIQUAD_STAGE 2 731 #define MINISRC_COEF_LOC 0x175 732 733 #define DMACONTROL_BLOCK_MASK 0x000F 734 #define DMAC_BLOCK0_SELECTOR 0x0000 735 #define DMAC_BLOCK1_SELECTOR 0x0001 736 #define DMAC_BLOCK2_SELECTOR 0x0002 737 #define DMAC_BLOCK3_SELECTOR 0x0003 738 #define DMAC_BLOCK4_SELECTOR 0x0004 739 #define DMAC_BLOCK5_SELECTOR 0x0005 740 #define DMAC_BLOCK6_SELECTOR 0x0006 741 #define DMAC_BLOCK7_SELECTOR 0x0007 742 #define DMAC_BLOCK8_SELECTOR 0x0008 743 #define DMAC_BLOCK9_SELECTOR 0x0009 744 #define DMAC_BLOCKA_SELECTOR 0x000A 745 #define DMAC_BLOCKB_SELECTOR 0x000B 746 #define DMAC_BLOCKC_SELECTOR 0x000C 747 #define DMAC_BLOCKD_SELECTOR 0x000D 748 #define DMAC_BLOCKE_SELECTOR 0x000E 749 #define DMAC_BLOCKF_SELECTOR 0x000F 750 #define DMACONTROL_PAGE_MASK 0x00F0 751 #define DMAC_PAGE0_SELECTOR 0x0030 752 #define DMAC_PAGE1_SELECTOR 0x0020 753 #define DMAC_PAGE2_SELECTOR 0x0010 754 #define DMAC_PAGE3_SELECTOR 0x0000 755 #define DMACONTROL_AUTOREPEAT 0x1000 756 #define DMACONTROL_STOPPED 0x2000 757 #define DMACONTROL_DIRECTION 0x0100 758 759 /* 760 * an arbitrary volume we set the internal 761 * volume settings to so that the ac97 volume 762 * range is a little less insane. 0x7fff is 763 * max. 764 */ 765 #define ARB_VOLUME ( 0x6800 ) 766 767 /* 768 */ 769 770 typedef struct snd_m3_dma m3_dma_t; 771 typedef struct snd_m3 m3_t; 772 773 /* quirk lists */ 774 struct m3_quirk { 775 const char *name; /* device name */ 776 u16 vendor, device; /* subsystem ids */ 777 int amp_gpio; /* gpio pin # for external amp, -1 = default */ 778 int irda_workaround; /* non-zero if avoid to touch 0x10 on GPIO_DIRECTION 779 (e.g. for IrDA on Dell Inspirons) */ 780 }; 781 782 struct m3_hv_quirk { 783 u16 vendor, device, subsystem_vendor, subsystem_device; 784 u32 config; /* ALLEGRO_CONFIG hardware volume bits */ 785 int is_omnibook; /* Do HP OmniBook GPIO magic? */ 786 }; 787 788 struct m3_list { 789 int curlen; 790 int mem_addr; 791 int max; 792 }; 793 794 struct snd_m3_dma { 795 796 int number; 797 m3_t *chip; 798 snd_pcm_substream_t *substream; 799 800 struct assp_instance { 801 unsigned short code, data; 802 } inst; 803 804 int running; 805 int opened; 806 807 unsigned long buffer_addr; 808 int dma_size; 809 int period_size; 810 unsigned int hwptr; 811 int count; 812 813 int index[3]; 814 struct m3_list *index_list[3]; 815 816 int in_lists; 817 818 struct list_head list; 819 820 }; 821 822 struct snd_m3 { 823 824 snd_card_t *card; 825 826 unsigned long iobase; 827 828 int irq; 829 unsigned int allegro_flag : 1; 830 831 ac97_t *ac97; 832 833 snd_pcm_t *pcm; 834 835 struct pci_dev *pci; 836 struct m3_quirk *quirk; 837 struct m3_hv_quirk *hv_quirk; 838 839 int dacs_active; 840 int timer_users; 841 842 struct m3_list msrc_list; 843 struct m3_list mixer_list; 844 struct m3_list adc1_list; 845 struct m3_list dma_list; 846 847 /* for storing reset state..*/ 848 u8 reset_state; 849 850 int external_amp; 851 int amp_gpio; 852 853 /* midi */ 854 snd_rawmidi_t *rmidi; 855 856 /* pcm streams */ 857 int num_substreams; 858 m3_dma_t *substreams; 859 860 spinlock_t reg_lock; 861 spinlock_t ac97_lock; 862 863 snd_kcontrol_t *master_switch; 864 snd_kcontrol_t *master_volume; 865 struct tasklet_struct hwvol_tq; 866 867 #ifdef CONFIG_PM 868 u16 *suspend_mem; 869 #endif 870 }; 871 872 /* 873 * pci ids 874 */ 875 876 #ifndef PCI_VENDOR_ID_ESS 877 #define PCI_VENDOR_ID_ESS 0x125D 878 #endif 879 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO_1 880 #define PCI_DEVICE_ID_ESS_ALLEGRO_1 0x1988 881 #endif 882 #ifndef PCI_DEVICE_ID_ESS_ALLEGRO 883 #define PCI_DEVICE_ID_ESS_ALLEGRO 0x1989 884 #endif 885 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2LE 886 #define PCI_DEVICE_ID_ESS_CANYON3D_2LE 0x1990 887 #endif 888 #ifndef PCI_DEVICE_ID_ESS_CANYON3D_2 889 #define PCI_DEVICE_ID_ESS_CANYON3D_2 0x1992 890 #endif 891 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3 892 #define PCI_DEVICE_ID_ESS_MAESTRO3 0x1998 893 #endif 894 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_1 895 #define PCI_DEVICE_ID_ESS_MAESTRO3_1 0x1999 896 #endif 897 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_HW 898 #define PCI_DEVICE_ID_ESS_MAESTRO3_HW 0x199a 899 #endif 900 #ifndef PCI_DEVICE_ID_ESS_MAESTRO3_2 901 #define PCI_DEVICE_ID_ESS_MAESTRO3_2 0x199b 902 #endif 903 904 static struct pci_device_id snd_m3_ids[] = { 905 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID, 906 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 907 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID, 908 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 909 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID, 910 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 911 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID, 912 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 913 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID, 914 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 915 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID, 916 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 917 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID, 918 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 919 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID, 920 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0}, 921 {0,}, 922 }; 923 924 MODULE_DEVICE_TABLE(pci, snd_m3_ids); 925 926 static struct m3_quirk m3_quirk_list[] = { 927 /* panasonic CF-28 "toughbook" */ 928 { 929 .name = "Panasonic CF-28", 930 .vendor = 0x10f7, 931 .device = 0x833e, 932 .amp_gpio = 0x0d, 933 }, 934 /* panasonic CF-72 "toughbook" */ 935 { 936 .name = "Panasonic CF-72", 937 .vendor = 0x10f7, 938 .device = 0x833d, 939 .amp_gpio = 0x0d, 940 }, 941 /* Dell Inspiron 4000 */ 942 { 943 .name = "Dell Inspiron 4000", 944 .vendor = 0x1028, 945 .device = 0x00b0, 946 .amp_gpio = -1, 947 .irda_workaround = 1, 948 }, 949 /* Dell Inspiron 8000 */ 950 { 951 .name = "Dell Inspiron 8000", 952 .vendor = 0x1028, 953 .device = 0x00a4, 954 .amp_gpio = -1, 955 .irda_workaround = 1, 956 }, 957 /* Dell Inspiron 8100 */ 958 { 959 .name = "Dell Inspiron 8100", 960 .vendor = 0x1028, 961 .device = 0x00e6, 962 .amp_gpio = -1, 963 .irda_workaround = 1, 964 }, 965 /* NEC LM800J/7 */ 966 { 967 .name = "NEC LM800J/7", 968 .vendor = 0x1033, 969 .device = 0x80f1, 970 .amp_gpio = 0x03, 971 }, 972 /* LEGEND ZhaoYang 3100CF */ 973 { 974 .name = "LEGEND ZhaoYang 3100CF", 975 .vendor = 0x1509, 976 .device = 0x1740, 977 .amp_gpio = 0x03, 978 }, 979 /* END */ 980 { NULL } 981 }; 982 983 /* These values came from the Windows driver. */ 984 static struct m3_hv_quirk m3_hv_quirk_list[] = { 985 /* Allegro chips */ 986 { 0x125D, 0x1988, 0x0E11, 0x002E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 987 { 0x125D, 0x1988, 0x0E11, 0x0094, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 988 { 0x125D, 0x1988, 0x0E11, 0xB112, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 989 { 0x125D, 0x1988, 0x0E11, 0xB114, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 990 { 0x125D, 0x1988, 0x103C, 0x0012, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 991 { 0x125D, 0x1988, 0x103C, 0x0018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 992 { 0x125D, 0x1988, 0x103C, 0x001C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 993 { 0x125D, 0x1988, 0x103C, 0x001D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 994 { 0x125D, 0x1988, 0x103C, 0x001E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 995 { 0x125D, 0x1988, 0x107B, 0x3350, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 996 { 0x125D, 0x1988, 0x10F7, 0x8338, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 997 { 0x125D, 0x1988, 0x10F7, 0x833C, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 998 { 0x125D, 0x1988, 0x10F7, 0x833D, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 999 { 0x125D, 0x1988, 0x10F7, 0x833E, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1000 { 0x125D, 0x1988, 0x10F7, 0x833F, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1001 { 0x125D, 0x1988, 0x13BD, 0x1018, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1002 { 0x125D, 0x1988, 0x13BD, 0x1019, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1003 { 0x125D, 0x1988, 0x13BD, 0x101A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1004 { 0x125D, 0x1988, 0x14FF, 0x0F03, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1005 { 0x125D, 0x1988, 0x14FF, 0x0F04, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1006 { 0x125D, 0x1988, 0x14FF, 0x0F05, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1007 { 0x125D, 0x1988, 0x156D, 0xB400, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1008 { 0x125D, 0x1988, 0x156D, 0xB795, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1009 { 0x125D, 0x1988, 0x156D, 0xB797, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1010 { 0x125D, 0x1988, 0x156D, 0xC700, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD, 0 }, 1011 { 0x125D, 0x1988, 0x1033, 0x80F1, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, 1012 { 0x125D, 0x1988, 0x103C, 0x001A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, /* HP OmniBook 6100 */ 1013 { 0x125D, 0x1988, 0x107B, 0x340A, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, 1014 { 0x125D, 0x1988, 0x107B, 0x3450, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, 1015 { 0x125D, 0x1988, 0x109F, 0x3134, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, 1016 { 0x125D, 0x1988, 0x109F, 0x3161, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, 1017 { 0x125D, 0x1988, 0x144D, 0x3280, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, 1018 { 0x125D, 0x1988, 0x144D, 0x3281, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, 1019 { 0x125D, 0x1988, 0x144D, 0xC002, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, 1020 { 0x125D, 0x1988, 0x144D, 0xC003, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, 1021 { 0x125D, 0x1988, 0x1509, 0x1740, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, 1022 { 0x125D, 0x1988, 0x1610, 0x0010, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE, 0 }, 1023 { 0x125D, 0x1988, 0x1042, 0x1042, HV_CTRL_ENABLE, 0 }, 1024 { 0x125D, 0x1988, 0x107B, 0x9500, HV_CTRL_ENABLE, 0 }, 1025 { 0x125D, 0x1988, 0x14FF, 0x0F06, HV_CTRL_ENABLE, 0 }, 1026 { 0x125D, 0x1988, 0x1558, 0x8586, HV_CTRL_ENABLE, 0 }, 1027 { 0x125D, 0x1988, 0x161F, 0x2011, HV_CTRL_ENABLE, 0 }, 1028 /* Maestro3 chips */ 1029 { 0x125D, 0x1998, 0x103C, 0x000E, HV_CTRL_ENABLE, 0 }, 1030 { 0x125D, 0x1998, 0x103C, 0x0010, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 6000 */ 1031 { 0x125D, 0x1998, 0x103C, 0x0011, HV_CTRL_ENABLE, 1 }, /* HP OmniBook 500 */ 1032 { 0x125D, 0x1998, 0x103C, 0x001B, HV_CTRL_ENABLE, 0 }, 1033 { 0x125D, 0x1998, 0x104D, 0x80A6, HV_CTRL_ENABLE, 0 }, 1034 { 0x125D, 0x1998, 0x104D, 0x80AA, HV_CTRL_ENABLE, 0 }, 1035 { 0x125D, 0x1998, 0x107B, 0x5300, HV_CTRL_ENABLE, 0 }, 1036 { 0x125D, 0x1998, 0x110A, 0x1998, HV_CTRL_ENABLE, 0 }, 1037 { 0x125D, 0x1998, 0x13BD, 0x1015, HV_CTRL_ENABLE, 0 }, 1038 { 0x125D, 0x1998, 0x13BD, 0x101C, HV_CTRL_ENABLE, 0 }, 1039 { 0x125D, 0x1998, 0x13BD, 0x1802, HV_CTRL_ENABLE, 0 }, 1040 { 0x125D, 0x1998, 0x1599, 0x0715, HV_CTRL_ENABLE, 0 }, 1041 { 0x125D, 0x1998, 0x5643, 0x5643, HV_CTRL_ENABLE, 0 }, 1042 { 0x125D, 0x199A, 0x144D, 0x3260, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 }, 1043 { 0x125D, 0x199A, 0x144D, 0x3261, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 }, 1044 { 0x125D, 0x199A, 0x144D, 0xC000, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 }, 1045 { 0x125D, 0x199A, 0x144D, 0xC001, HV_CTRL_ENABLE | REDUCED_DEBOUNCE, 0 }, 1046 { 0 } 1047 }; 1048 1049 /* 1050 * lowlevel functions 1051 */ 1052 1053 #define big_mdelay(msec) do {\ 1054 set_current_state(TASK_UNINTERRUPTIBLE);\ 1055 schedule_timeout(((msec) * HZ) / 1000);\ 1056 } while (0) 1057 1058 inline static void snd_m3_outw(m3_t *chip, u16 value, unsigned long reg) 1059 { 1060 outw(value, chip->iobase + reg); 1061 } 1062 1063 inline static u16 snd_m3_inw(m3_t *chip, unsigned long reg) 1064 { 1065 return inw(chip->iobase + reg); 1066 } 1067 1068 inline static void snd_m3_outb(m3_t *chip, u8 value, unsigned long reg) 1069 { 1070 outb(value, chip->iobase + reg); 1071 } 1072 1073 inline static u8 snd_m3_inb(m3_t *chip, unsigned long reg) 1074 { 1075 return inb(chip->iobase + reg); 1076 } 1077 1078 /* 1079 * access 16bit words to the code or data regions of the dsp's memory. 1080 * index addresses 16bit words. 1081 */ 1082 static u16 snd_m3_assp_read(m3_t *chip, u16 region, u16 index) 1083 { 1084 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); 1085 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); 1086 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA); 1087 } 1088 1089 static void snd_m3_assp_write(m3_t *chip, u16 region, u16 index, u16 data) 1090 { 1091 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE); 1092 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX); 1093 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA); 1094 } 1095 1096 static void snd_m3_assp_halt(m3_t *chip) 1097 { 1098 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK; 1099 big_mdelay(10); 1100 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); 1101 } 1102 1103 static void snd_m3_assp_continue(m3_t *chip) 1104 { 1105 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B); 1106 } 1107 1108 1109 /* 1110 * This makes me sad. the maestro3 has lists 1111 * internally that must be packed.. 0 terminates, 1112 * apparently, or maybe all unused entries have 1113 * to be 0, the lists have static lengths set 1114 * by the binary code images. 1115 */ 1116 1117 static int snd_m3_add_list(m3_t *chip, struct m3_list *list, u16 val) 1118 { 1119 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1120 list->mem_addr + list->curlen, 1121 val); 1122 return list->curlen++; 1123 } 1124 1125 static void snd_m3_remove_list(m3_t *chip, struct m3_list *list, int index) 1126 { 1127 u16 val; 1128 int lastindex = list->curlen - 1; 1129 1130 if (index != lastindex) { 1131 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 1132 list->mem_addr + lastindex); 1133 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1134 list->mem_addr + index, 1135 val); 1136 } 1137 1138 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1139 list->mem_addr + lastindex, 1140 0); 1141 1142 list->curlen--; 1143 } 1144 1145 static void snd_m3_inc_timer_users(m3_t *chip) 1146 { 1147 chip->timer_users++; 1148 if (chip->timer_users != 1) 1149 return; 1150 1151 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1152 KDATA_TIMER_COUNT_RELOAD, 1153 240); 1154 1155 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1156 KDATA_TIMER_COUNT_CURRENT, 1157 240); 1158 1159 snd_m3_outw(chip, 1160 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE, 1161 HOST_INT_CTRL); 1162 } 1163 1164 static void snd_m3_dec_timer_users(m3_t *chip) 1165 { 1166 chip->timer_users--; 1167 if (chip->timer_users > 0) 1168 return; 1169 1170 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1171 KDATA_TIMER_COUNT_RELOAD, 1172 0); 1173 1174 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1175 KDATA_TIMER_COUNT_CURRENT, 1176 0); 1177 1178 snd_m3_outw(chip, 1179 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE, 1180 HOST_INT_CTRL); 1181 } 1182 1183 /* 1184 * start/stop 1185 */ 1186 1187 /* spinlock held! */ 1188 static int snd_m3_pcm_start(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) 1189 { 1190 if (! s || ! subs) 1191 return -EINVAL; 1192 1193 snd_m3_inc_timer_users(chip); 1194 switch (subs->stream) { 1195 case SNDRV_PCM_STREAM_PLAYBACK: 1196 chip->dacs_active++; 1197 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1198 s->inst.data + CDATA_INSTANCE_READY, 1); 1199 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1200 KDATA_MIXER_TASK_NUMBER, 1201 chip->dacs_active); 1202 break; 1203 case SNDRV_PCM_STREAM_CAPTURE: 1204 snd_m3_assp_write(s->chip, MEMTYPE_INTERNAL_DATA, 1205 KDATA_ADC1_REQUEST, 1); 1206 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1207 s->inst.data + CDATA_INSTANCE_READY, 1); 1208 break; 1209 } 1210 return 0; 1211 } 1212 1213 /* spinlock held! */ 1214 static int snd_m3_pcm_stop(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) 1215 { 1216 if (! s || ! subs) 1217 return -EINVAL; 1218 1219 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1220 s->inst.data + CDATA_INSTANCE_READY, 0); 1221 snd_m3_dec_timer_users(chip); 1222 switch (subs->stream) { 1223 case SNDRV_PCM_STREAM_PLAYBACK: 1224 chip->dacs_active--; 1225 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1226 KDATA_MIXER_TASK_NUMBER, 1227 chip->dacs_active); 1228 break; 1229 case SNDRV_PCM_STREAM_CAPTURE: 1230 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1231 KDATA_ADC1_REQUEST, 0); 1232 break; 1233 } 1234 return 0; 1235 } 1236 1237 static int 1238 snd_m3_pcm_trigger(snd_pcm_substream_t *subs, int cmd) 1239 { 1240 m3_t *chip = snd_pcm_substream_chip(subs); 1241 m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data; 1242 int err = -EINVAL; 1243 1244 snd_assert(s != NULL, return -ENXIO); 1245 1246 spin_lock(&chip->reg_lock); 1247 switch (cmd) { 1248 case SNDRV_PCM_TRIGGER_START: 1249 case SNDRV_PCM_TRIGGER_RESUME: 1250 if (s->running) 1251 err = -EBUSY; 1252 else { 1253 s->running = 1; 1254 err = snd_m3_pcm_start(chip, s, subs); 1255 } 1256 break; 1257 case SNDRV_PCM_TRIGGER_STOP: 1258 case SNDRV_PCM_TRIGGER_SUSPEND: 1259 if (! s->running) 1260 err = 0; /* should return error? */ 1261 else { 1262 s->running = 0; 1263 err = snd_m3_pcm_stop(chip, s, subs); 1264 } 1265 break; 1266 } 1267 spin_unlock(&chip->reg_lock); 1268 return err; 1269 } 1270 1271 /* 1272 * setup 1273 */ 1274 static void 1275 snd_m3_pcm_setup1(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) 1276 { 1277 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer; 1278 snd_pcm_runtime_t *runtime = subs->runtime; 1279 1280 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1281 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2); 1282 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2); 1283 } else { 1284 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2); 1285 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2); 1286 } 1287 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2); 1288 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1; 1289 1290 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size); 1291 s->period_size = frames_to_bytes(runtime, runtime->period_size); 1292 s->hwptr = 0; 1293 s->count = 0; 1294 1295 #define LO(x) ((x) & 0xffff) 1296 #define HI(x) LO((x) >> 16) 1297 1298 /* host dma buffer pointers */ 1299 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1300 s->inst.data + CDATA_HOST_SRC_ADDRL, 1301 LO(s->buffer_addr)); 1302 1303 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1304 s->inst.data + CDATA_HOST_SRC_ADDRH, 1305 HI(s->buffer_addr)); 1306 1307 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1308 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L, 1309 LO(s->buffer_addr + s->dma_size)); 1310 1311 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1312 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H, 1313 HI(s->buffer_addr + s->dma_size)); 1314 1315 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1316 s->inst.data + CDATA_HOST_SRC_CURRENTL, 1317 LO(s->buffer_addr)); 1318 1319 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1320 s->inst.data + CDATA_HOST_SRC_CURRENTH, 1321 HI(s->buffer_addr)); 1322 #undef LO 1323 #undef HI 1324 1325 /* dsp buffers */ 1326 1327 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1328 s->inst.data + CDATA_IN_BUF_BEGIN, 1329 dsp_in_buffer); 1330 1331 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1332 s->inst.data + CDATA_IN_BUF_END_PLUS_1, 1333 dsp_in_buffer + (dsp_in_size / 2)); 1334 1335 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1336 s->inst.data + CDATA_IN_BUF_HEAD, 1337 dsp_in_buffer); 1338 1339 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1340 s->inst.data + CDATA_IN_BUF_TAIL, 1341 dsp_in_buffer); 1342 1343 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1344 s->inst.data + CDATA_OUT_BUF_BEGIN, 1345 dsp_out_buffer); 1346 1347 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1348 s->inst.data + CDATA_OUT_BUF_END_PLUS_1, 1349 dsp_out_buffer + (dsp_out_size / 2)); 1350 1351 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1352 s->inst.data + CDATA_OUT_BUF_HEAD, 1353 dsp_out_buffer); 1354 1355 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1356 s->inst.data + CDATA_OUT_BUF_TAIL, 1357 dsp_out_buffer); 1358 } 1359 1360 static void snd_m3_pcm_setup2(m3_t *chip, m3_dma_t *s, snd_pcm_runtime_t *runtime) 1361 { 1362 u32 freq; 1363 1364 /* 1365 * put us in the lists if we're not already there 1366 */ 1367 if (! s->in_lists) { 1368 s->index[0] = snd_m3_add_list(chip, s->index_list[0], 1369 s->inst.data >> DP_SHIFT_COUNT); 1370 s->index[1] = snd_m3_add_list(chip, s->index_list[1], 1371 s->inst.data >> DP_SHIFT_COUNT); 1372 s->index[2] = snd_m3_add_list(chip, s->index_list[2], 1373 s->inst.data >> DP_SHIFT_COUNT); 1374 s->in_lists = 1; 1375 } 1376 1377 /* write to 'mono' word */ 1378 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1379 s->inst.data + SRC3_DIRECTION_OFFSET + 1, 1380 runtime->channels == 2 ? 0 : 1); 1381 /* write to '8bit' word */ 1382 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1383 s->inst.data + SRC3_DIRECTION_OFFSET + 2, 1384 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1); 1385 1386 /* set up dac/adc rate */ 1387 freq = ((runtime->rate << 15) + 24000 ) / 48000; 1388 if (freq) 1389 freq--; 1390 1391 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1392 s->inst.data + CDATA_FREQUENCY, 1393 freq); 1394 } 1395 1396 1397 static struct play_vals { 1398 u16 addr, val; 1399 } pv[] = { 1400 {CDATA_LEFT_VOLUME, ARB_VOLUME}, 1401 {CDATA_RIGHT_VOLUME, ARB_VOLUME}, 1402 {SRC3_DIRECTION_OFFSET, 0} , 1403 /* +1, +2 are stereo/16 bit */ 1404 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ 1405 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ 1406 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ 1407 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ 1408 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ 1409 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ 1410 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ 1411 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ 1412 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ 1413 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ 1414 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ 1415 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ 1416 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */ 1417 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */ 1418 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */ 1419 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ 1420 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */ 1421 }; 1422 1423 1424 /* the mode passed should be already shifted and masked */ 1425 static void 1426 snd_m3_playback_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) 1427 { 1428 unsigned int i; 1429 1430 /* 1431 * some per client initializers 1432 */ 1433 1434 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1435 s->inst.data + SRC3_DIRECTION_OFFSET + 12, 1436 s->inst.data + 40 + 8); 1437 1438 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1439 s->inst.data + SRC3_DIRECTION_OFFSET + 19, 1440 s->inst.code + MINISRC_COEF_LOC); 1441 1442 /* enable or disable low pass filter? */ 1443 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1444 s->inst.data + SRC3_DIRECTION_OFFSET + 22, 1445 subs->runtime->rate > 45000 ? 0xff : 0); 1446 1447 /* tell it which way dma is going? */ 1448 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1449 s->inst.data + CDATA_DMA_CONTROL, 1450 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); 1451 1452 /* 1453 * set an armload of static initializers 1454 */ 1455 for (i = 0; i < ARRAY_SIZE(pv); i++) 1456 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1457 s->inst.data + pv[i].addr, pv[i].val); 1458 } 1459 1460 /* 1461 * Native record driver 1462 */ 1463 static struct rec_vals { 1464 u16 addr, val; 1465 } rv[] = { 1466 {CDATA_LEFT_VOLUME, ARB_VOLUME}, 1467 {CDATA_RIGHT_VOLUME, ARB_VOLUME}, 1468 {SRC3_DIRECTION_OFFSET, 1} , 1469 /* +1, +2 are stereo/16 bit */ 1470 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */ 1471 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */ 1472 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */ 1473 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */ 1474 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */ 1475 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */ 1476 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */ 1477 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */ 1478 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */ 1479 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */ 1480 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */ 1481 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */ 1482 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */ 1483 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */ 1484 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */ 1485 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */ 1486 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */ 1487 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */ 1488 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */ 1489 }; 1490 1491 static void 1492 snd_m3_capture_setup(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) 1493 { 1494 unsigned int i; 1495 1496 /* 1497 * some per client initializers 1498 */ 1499 1500 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1501 s->inst.data + SRC3_DIRECTION_OFFSET + 12, 1502 s->inst.data + 40 + 8); 1503 1504 /* tell it which way dma is going? */ 1505 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1506 s->inst.data + CDATA_DMA_CONTROL, 1507 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT + 1508 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR); 1509 1510 /* 1511 * set an armload of static initializers 1512 */ 1513 for (i = 0; i < ARRAY_SIZE(rv); i++) 1514 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 1515 s->inst.data + rv[i].addr, rv[i].val); 1516 } 1517 1518 static int snd_m3_pcm_hw_params(snd_pcm_substream_t * substream, 1519 snd_pcm_hw_params_t * hw_params) 1520 { 1521 m3_dma_t *s = (m3_dma_t*) substream->runtime->private_data; 1522 int err; 1523 1524 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) 1525 return err; 1526 /* set buffer address */ 1527 s->buffer_addr = substream->runtime->dma_addr; 1528 if (s->buffer_addr & 0x3) { 1529 snd_printk("oh my, not aligned\n"); 1530 s->buffer_addr = s->buffer_addr & ~0x3; 1531 } 1532 return 0; 1533 } 1534 1535 static int snd_m3_pcm_hw_free(snd_pcm_substream_t * substream) 1536 { 1537 m3_dma_t *s; 1538 1539 if (substream->runtime->private_data == NULL) 1540 return 0; 1541 s = (m3_dma_t*) substream->runtime->private_data; 1542 snd_pcm_lib_free_pages(substream); 1543 s->buffer_addr = 0; 1544 return 0; 1545 } 1546 1547 static int 1548 snd_m3_pcm_prepare(snd_pcm_substream_t *subs) 1549 { 1550 m3_t *chip = snd_pcm_substream_chip(subs); 1551 snd_pcm_runtime_t *runtime = subs->runtime; 1552 m3_dma_t *s = (m3_dma_t*)runtime->private_data; 1553 1554 snd_assert(s != NULL, return -ENXIO); 1555 1556 if (runtime->format != SNDRV_PCM_FORMAT_U8 && 1557 runtime->format != SNDRV_PCM_FORMAT_S16_LE) 1558 return -EINVAL; 1559 if (runtime->rate > 48000 || 1560 runtime->rate < 8000) 1561 return -EINVAL; 1562 1563 spin_lock_irq(&chip->reg_lock); 1564 1565 snd_m3_pcm_setup1(chip, s, subs); 1566 1567 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) 1568 snd_m3_playback_setup(chip, s, subs); 1569 else 1570 snd_m3_capture_setup(chip, s, subs); 1571 1572 snd_m3_pcm_setup2(chip, s, runtime); 1573 1574 spin_unlock_irq(&chip->reg_lock); 1575 1576 return 0; 1577 } 1578 1579 /* 1580 * get current pointer 1581 */ 1582 static unsigned int 1583 snd_m3_get_pointer(m3_t *chip, m3_dma_t *s, snd_pcm_substream_t *subs) 1584 { 1585 u16 hi = 0, lo = 0; 1586 int retry = 10; 1587 u32 addr; 1588 1589 /* 1590 * try and get a valid answer 1591 */ 1592 while (retry--) { 1593 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 1594 s->inst.data + CDATA_HOST_SRC_CURRENTH); 1595 1596 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 1597 s->inst.data + CDATA_HOST_SRC_CURRENTL); 1598 1599 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, 1600 s->inst.data + CDATA_HOST_SRC_CURRENTH)) 1601 break; 1602 } 1603 addr = lo | ((u32)hi<<16); 1604 return (unsigned int)(addr - s->buffer_addr); 1605 } 1606 1607 static snd_pcm_uframes_t 1608 snd_m3_pcm_pointer(snd_pcm_substream_t * subs) 1609 { 1610 m3_t *chip = snd_pcm_substream_chip(subs); 1611 unsigned int ptr; 1612 m3_dma_t *s = (m3_dma_t*)subs->runtime->private_data; 1613 snd_assert(s != NULL, return 0); 1614 1615 spin_lock(&chip->reg_lock); 1616 ptr = snd_m3_get_pointer(chip, s, subs); 1617 spin_unlock(&chip->reg_lock); 1618 return bytes_to_frames(subs->runtime, ptr); 1619 } 1620 1621 1622 /* update pointer */ 1623 /* spinlock held! */ 1624 static void snd_m3_update_ptr(m3_t *chip, m3_dma_t *s) 1625 { 1626 snd_pcm_substream_t *subs = s->substream; 1627 unsigned int hwptr; 1628 int diff; 1629 1630 if (! s->running) 1631 return; 1632 1633 hwptr = snd_m3_get_pointer(chip, s, subs) % s->dma_size; 1634 diff = (s->dma_size + hwptr - s->hwptr) % s->dma_size; 1635 s->hwptr = hwptr; 1636 s->count += diff; 1637 if (s->count >= (signed)s->period_size) { 1638 s->count %= s->period_size; 1639 spin_unlock(&chip->reg_lock); 1640 snd_pcm_period_elapsed(subs); 1641 spin_lock(&chip->reg_lock); 1642 } 1643 } 1644 1645 static void snd_m3_update_hw_volume(unsigned long private_data) 1646 { 1647 m3_t *chip = (m3_t *) private_data; 1648 int x, val; 1649 unsigned long flags; 1650 1651 /* Figure out which volume control button was pushed, 1652 based on differences from the default register 1653 values. */ 1654 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee; 1655 1656 /* Reset the volume control registers. */ 1657 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE); 1658 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE); 1659 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER); 1660 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER); 1661 1662 if (!chip->master_switch || !chip->master_volume) 1663 return; 1664 1665 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */ 1666 spin_lock_irqsave(&chip->ac97_lock, flags); 1667 1668 val = chip->ac97->regs[AC97_MASTER_VOL]; 1669 switch (x) { 1670 case 0x88: 1671 /* mute */ 1672 val ^= 0x8000; 1673 chip->ac97->regs[AC97_MASTER_VOL] = val; 1674 outw(val, chip->iobase + CODEC_DATA); 1675 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND); 1676 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1677 &chip->master_switch->id); 1678 break; 1679 case 0xaa: 1680 /* volume up */ 1681 if ((val & 0x7f) > 0) 1682 val--; 1683 if ((val & 0x7f00) > 0) 1684 val -= 0x0100; 1685 chip->ac97->regs[AC97_MASTER_VOL] = val; 1686 outw(val, chip->iobase + CODEC_DATA); 1687 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND); 1688 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1689 &chip->master_volume->id); 1690 break; 1691 case 0x66: 1692 /* volume down */ 1693 if ((val & 0x7f) < 0x1f) 1694 val++; 1695 if ((val & 0x7f00) < 0x1f00) 1696 val += 0x0100; 1697 chip->ac97->regs[AC97_MASTER_VOL] = val; 1698 outw(val, chip->iobase + CODEC_DATA); 1699 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND); 1700 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1701 &chip->master_volume->id); 1702 break; 1703 } 1704 spin_unlock_irqrestore(&chip->ac97_lock, flags); 1705 } 1706 1707 static irqreturn_t 1708 snd_m3_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1709 { 1710 m3_t *chip = dev_id; 1711 u8 status; 1712 int i; 1713 1714 status = inb(chip->iobase + HOST_INT_STATUS); 1715 1716 if (status == 0xff) 1717 return IRQ_NONE; 1718 1719 if (status & HV_INT_PENDING) 1720 tasklet_hi_schedule(&chip->hwvol_tq); 1721 1722 /* 1723 * ack an assp int if its running 1724 * and has an int pending 1725 */ 1726 if (status & ASSP_INT_PENDING) { 1727 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B); 1728 if (!(ctl & STOP_ASSP_CLOCK)) { 1729 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS); 1730 if (ctl & DSP2HOST_REQ_TIMER) { 1731 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS); 1732 /* update adc/dac info if it was a timer int */ 1733 spin_lock(&chip->reg_lock); 1734 for (i = 0; i < chip->num_substreams; i++) { 1735 m3_dma_t *s = &chip->substreams[i]; 1736 if (s->running) 1737 snd_m3_update_ptr(chip, s); 1738 } 1739 spin_unlock(&chip->reg_lock); 1740 } 1741 } 1742 } 1743 1744 #if 0 /* TODO: not supported yet */ 1745 if ((status & MPU401_INT_PENDING) && chip->rmidi) 1746 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs); 1747 #endif 1748 1749 /* ack ints */ 1750 outb(status, chip->iobase + HOST_INT_STATUS); 1751 1752 return IRQ_HANDLED; 1753 } 1754 1755 1756 /* 1757 */ 1758 1759 static snd_pcm_hardware_t snd_m3_playback = 1760 { 1761 .info = (SNDRV_PCM_INFO_MMAP | 1762 SNDRV_PCM_INFO_INTERLEAVED | 1763 SNDRV_PCM_INFO_MMAP_VALID | 1764 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1765 /*SNDRV_PCM_INFO_PAUSE |*/ 1766 SNDRV_PCM_INFO_RESUME), 1767 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1768 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1769 .rate_min = 8000, 1770 .rate_max = 48000, 1771 .channels_min = 1, 1772 .channels_max = 2, 1773 .buffer_bytes_max = (512*1024), 1774 .period_bytes_min = 64, 1775 .period_bytes_max = (512*1024), 1776 .periods_min = 1, 1777 .periods_max = 1024, 1778 }; 1779 1780 static snd_pcm_hardware_t snd_m3_capture = 1781 { 1782 .info = (SNDRV_PCM_INFO_MMAP | 1783 SNDRV_PCM_INFO_INTERLEAVED | 1784 SNDRV_PCM_INFO_MMAP_VALID | 1785 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1786 /*SNDRV_PCM_INFO_PAUSE |*/ 1787 SNDRV_PCM_INFO_RESUME), 1788 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1789 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1790 .rate_min = 8000, 1791 .rate_max = 48000, 1792 .channels_min = 1, 1793 .channels_max = 2, 1794 .buffer_bytes_max = (512*1024), 1795 .period_bytes_min = 64, 1796 .period_bytes_max = (512*1024), 1797 .periods_min = 1, 1798 .periods_max = 1024, 1799 }; 1800 1801 1802 /* 1803 */ 1804 1805 static int 1806 snd_m3_substream_open(m3_t *chip, snd_pcm_substream_t *subs) 1807 { 1808 int i; 1809 m3_dma_t *s; 1810 1811 spin_lock_irq(&chip->reg_lock); 1812 for (i = 0; i < chip->num_substreams; i++) { 1813 s = &chip->substreams[i]; 1814 if (! s->opened) 1815 goto __found; 1816 } 1817 spin_unlock_irq(&chip->reg_lock); 1818 return -ENOMEM; 1819 __found: 1820 s->opened = 1; 1821 s->running = 0; 1822 spin_unlock_irq(&chip->reg_lock); 1823 1824 subs->runtime->private_data = s; 1825 s->substream = subs; 1826 1827 /* set list owners */ 1828 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1829 s->index_list[0] = &chip->mixer_list; 1830 } else 1831 s->index_list[0] = &chip->adc1_list; 1832 s->index_list[1] = &chip->msrc_list; 1833 s->index_list[2] = &chip->dma_list; 1834 1835 return 0; 1836 } 1837 1838 static void 1839 snd_m3_substream_close(m3_t *chip, snd_pcm_substream_t *subs) 1840 { 1841 m3_dma_t *s = (m3_dma_t*) subs->runtime->private_data; 1842 1843 if (s == NULL) 1844 return; /* not opened properly */ 1845 1846 spin_lock_irq(&chip->reg_lock); 1847 if (s->substream && s->running) 1848 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */ 1849 if (s->in_lists) { 1850 snd_m3_remove_list(chip, s->index_list[0], s->index[0]); 1851 snd_m3_remove_list(chip, s->index_list[1], s->index[1]); 1852 snd_m3_remove_list(chip, s->index_list[2], s->index[2]); 1853 s->in_lists = 0; 1854 } 1855 s->running = 0; 1856 s->opened = 0; 1857 spin_unlock_irq(&chip->reg_lock); 1858 } 1859 1860 static int 1861 snd_m3_playback_open(snd_pcm_substream_t *subs) 1862 { 1863 m3_t *chip = snd_pcm_substream_chip(subs); 1864 snd_pcm_runtime_t *runtime = subs->runtime; 1865 int err; 1866 1867 if ((err = snd_m3_substream_open(chip, subs)) < 0) 1868 return err; 1869 1870 runtime->hw = snd_m3_playback; 1871 snd_pcm_set_sync(subs); 1872 1873 return 0; 1874 } 1875 1876 static int 1877 snd_m3_playback_close(snd_pcm_substream_t *subs) 1878 { 1879 m3_t *chip = snd_pcm_substream_chip(subs); 1880 1881 snd_m3_substream_close(chip, subs); 1882 return 0; 1883 } 1884 1885 static int 1886 snd_m3_capture_open(snd_pcm_substream_t *subs) 1887 { 1888 m3_t *chip = snd_pcm_substream_chip(subs); 1889 snd_pcm_runtime_t *runtime = subs->runtime; 1890 int err; 1891 1892 if ((err = snd_m3_substream_open(chip, subs)) < 0) 1893 return err; 1894 1895 runtime->hw = snd_m3_capture; 1896 snd_pcm_set_sync(subs); 1897 1898 return 0; 1899 } 1900 1901 static int 1902 snd_m3_capture_close(snd_pcm_substream_t *subs) 1903 { 1904 m3_t *chip = snd_pcm_substream_chip(subs); 1905 1906 snd_m3_substream_close(chip, subs); 1907 return 0; 1908 } 1909 1910 /* 1911 * create pcm instance 1912 */ 1913 1914 static snd_pcm_ops_t snd_m3_playback_ops = { 1915 .open = snd_m3_playback_open, 1916 .close = snd_m3_playback_close, 1917 .ioctl = snd_pcm_lib_ioctl, 1918 .hw_params = snd_m3_pcm_hw_params, 1919 .hw_free = snd_m3_pcm_hw_free, 1920 .prepare = snd_m3_pcm_prepare, 1921 .trigger = snd_m3_pcm_trigger, 1922 .pointer = snd_m3_pcm_pointer, 1923 }; 1924 1925 static snd_pcm_ops_t snd_m3_capture_ops = { 1926 .open = snd_m3_capture_open, 1927 .close = snd_m3_capture_close, 1928 .ioctl = snd_pcm_lib_ioctl, 1929 .hw_params = snd_m3_pcm_hw_params, 1930 .hw_free = snd_m3_pcm_hw_free, 1931 .prepare = snd_m3_pcm_prepare, 1932 .trigger = snd_m3_pcm_trigger, 1933 .pointer = snd_m3_pcm_pointer, 1934 }; 1935 1936 static int __devinit 1937 snd_m3_pcm(m3_t * chip, int device) 1938 { 1939 snd_pcm_t *pcm; 1940 int err; 1941 1942 err = snd_pcm_new(chip->card, chip->card->driver, device, 1943 MAX_PLAYBACKS, MAX_CAPTURES, &pcm); 1944 if (err < 0) 1945 return err; 1946 1947 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops); 1948 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops); 1949 1950 pcm->private_data = chip; 1951 pcm->info_flags = 0; 1952 strcpy(pcm->name, chip->card->driver); 1953 chip->pcm = pcm; 1954 1955 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1956 snd_dma_pci_data(chip->pci), 64*1024, 64*1024); 1957 1958 return 0; 1959 } 1960 1961 1962 /* 1963 * ac97 interface 1964 */ 1965 1966 /* 1967 * Wait for the ac97 serial bus to be free. 1968 * return nonzero if the bus is still busy. 1969 */ 1970 static int snd_m3_ac97_wait(m3_t *chip) 1971 { 1972 int i = 10000; 1973 1974 do { 1975 if (! (snd_m3_inb(chip, 0x30) & 1)) 1976 return 0; 1977 } while (i-- > 0); 1978 1979 snd_printk("ac97 serial bus busy\n"); 1980 return 1; 1981 } 1982 1983 static unsigned short 1984 snd_m3_ac97_read(ac97_t *ac97, unsigned short reg) 1985 { 1986 m3_t *chip = ac97->private_data; 1987 unsigned long flags; 1988 unsigned short data; 1989 1990 if (snd_m3_ac97_wait(chip)) 1991 return 0xffff; 1992 spin_lock_irqsave(&chip->ac97_lock, flags); 1993 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND); 1994 if (snd_m3_ac97_wait(chip)) 1995 return 0xffff; 1996 data = snd_m3_inw(chip, CODEC_DATA); 1997 spin_unlock_irqrestore(&chip->ac97_lock, flags); 1998 return data; 1999 } 2000 2001 static void 2002 snd_m3_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val) 2003 { 2004 m3_t *chip = ac97->private_data; 2005 unsigned long flags; 2006 2007 if (snd_m3_ac97_wait(chip)) 2008 return; 2009 spin_lock_irqsave(&chip->ac97_lock, flags); 2010 snd_m3_outw(chip, val, CODEC_DATA); 2011 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND); 2012 spin_unlock_irqrestore(&chip->ac97_lock, flags); 2013 } 2014 2015 2016 static void snd_m3_remote_codec_config(int io, int isremote) 2017 { 2018 isremote = isremote ? 1 : 0; 2019 2020 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote, 2021 io + RING_BUS_CTRL_B); 2022 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote, 2023 io + SDO_OUT_DEST_CTRL); 2024 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote, 2025 io + SDO_IN_DEST_CTRL); 2026 } 2027 2028 /* 2029 * hack, returns non zero on err 2030 */ 2031 static int snd_m3_try_read_vendor(m3_t *chip) 2032 { 2033 u16 ret; 2034 2035 if (snd_m3_ac97_wait(chip)) 2036 return 1; 2037 2038 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30); 2039 2040 if (snd_m3_ac97_wait(chip)) 2041 return 1; 2042 2043 ret = snd_m3_inw(chip, 0x32); 2044 2045 return (ret == 0) || (ret == 0xffff); 2046 } 2047 2048 static void snd_m3_ac97_reset(m3_t *chip) 2049 { 2050 u16 dir; 2051 int delay1 = 0, delay2 = 0, i; 2052 int io = chip->iobase; 2053 2054 if (chip->allegro_flag) { 2055 /* 2056 * the onboard codec on the allegro seems 2057 * to want to wait a very long time before 2058 * coming back to life 2059 */ 2060 delay1 = 50; 2061 delay2 = 800; 2062 } else { 2063 /* maestro3 */ 2064 delay1 = 20; 2065 delay2 = 500; 2066 } 2067 2068 for (i = 0; i < 5; i++) { 2069 dir = inw(io + GPIO_DIRECTION); 2070 if (! chip->quirk || ! chip->quirk->irda_workaround) 2071 dir |= 0x10; /* assuming pci bus master? */ 2072 2073 snd_m3_remote_codec_config(io, 0); 2074 2075 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A); 2076 udelay(20); 2077 2078 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION); 2079 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK); 2080 outw(0, io + GPIO_DATA); 2081 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION); 2082 2083 set_current_state(TASK_UNINTERRUPTIBLE); 2084 schedule_timeout((delay1 * HZ) / 1000); 2085 2086 outw(GPO_PRIMARY_AC97, io + GPIO_DATA); 2087 udelay(5); 2088 /* ok, bring back the ac-link */ 2089 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A); 2090 outw(~0, io + GPIO_MASK); 2091 2092 set_current_state(TASK_UNINTERRUPTIBLE); 2093 schedule_timeout((delay2 * HZ) / 1000); 2094 2095 if (! snd_m3_try_read_vendor(chip)) 2096 break; 2097 2098 delay1 += 10; 2099 delay2 += 100; 2100 2101 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n", 2102 delay1, delay2); 2103 } 2104 2105 #if 0 2106 /* more gung-ho reset that doesn't 2107 * seem to work anywhere :) 2108 */ 2109 tmp = inw(io + RING_BUS_CTRL_A); 2110 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A); 2111 big_mdelay(20); 2112 outw(tmp, io + RING_BUS_CTRL_A); 2113 big_mdelay(50); 2114 #endif 2115 } 2116 2117 static int __devinit snd_m3_mixer(m3_t *chip) 2118 { 2119 ac97_bus_t *pbus; 2120 ac97_template_t ac97; 2121 snd_ctl_elem_id_t id; 2122 int err; 2123 static ac97_bus_ops_t ops = { 2124 .write = snd_m3_ac97_write, 2125 .read = snd_m3_ac97_read, 2126 }; 2127 2128 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0) 2129 return err; 2130 2131 memset(&ac97, 0, sizeof(ac97)); 2132 ac97.private_data = chip; 2133 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0) 2134 return err; 2135 2136 /* seems ac97 PCM needs initialization.. hack hack.. */ 2137 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15); 2138 set_current_state(TASK_UNINTERRUPTIBLE); 2139 schedule_timeout(HZ / 10); 2140 snd_ac97_write(chip->ac97, AC97_PCM, 0); 2141 2142 memset(&id, 0, sizeof(id)); 2143 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2144 strcpy(id.name, "Master Playback Switch"); 2145 chip->master_switch = snd_ctl_find_id(chip->card, &id); 2146 memset(&id, 0, sizeof(id)); 2147 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2148 strcpy(id.name, "Master Playback Volume"); 2149 chip->master_volume = snd_ctl_find_id(chip->card, &id); 2150 2151 return 0; 2152 } 2153 2154 2155 /* 2156 * DSP Code images 2157 */ 2158 2159 static u16 assp_kernel_image[] __devinitdata = { 2160 0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4, 2161 0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 2162 0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 2163 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4, 2164 0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08, 2165 0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909, 2166 0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41, 2167 0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308, 2168 0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910, 2169 0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00, 2170 0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026, 2171 0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0, 2172 0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012, 2173 0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A, 2174 0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000, 2175 0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05, 2176 0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26, 2177 0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300, 2178 0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88, 2179 0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008, 2180 0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80, 2181 0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71, 2182 0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A, 2183 0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100, 2184 0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900, 2185 0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903, 2186 0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309, 2187 0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B, 2188 0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540, 2189 0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C, 2190 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380, 2191 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340, 2192 0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041, 2193 0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18, 2194 0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 2195 0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9, 2196 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8, 2197 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A, 2198 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80, 2199 0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 2200 0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80, 2201 0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A, 2202 0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F, 2203 0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1, 2204 0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034, 2205 0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 2206 0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977, 2207 0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B, 2208 0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388, 2209 0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 2210 0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473, 2211 0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473, 2212 0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880, 2213 0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80, 2214 0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6, 2215 0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909, 2216 0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED, 2217 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005, 2218 0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 2219 0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4, 2220 0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 2221 0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10, 2222 0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070, 2223 0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71, 2224 0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A, 2225 0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061, 2226 0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A, 2227 0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6, 2228 0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A, 2229 0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6, 2230 0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358, 2231 0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6, 2232 0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9, 2233 0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379, 2234 0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6, 2235 0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C, 2236 0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166, 2237 0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B, 2238 0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A, 2239 0xBE3A, 2240 }; 2241 2242 /* 2243 * Mini sample rate converter code image 2244 * that is to be loaded at 0x400 on the DSP. 2245 */ 2246 static u16 assp_minisrc_image[] __devinitdata = { 2247 2248 0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412, 2249 0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41, 2250 0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907, 2251 0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01, 2252 0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904, 2253 0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D, 2254 0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD, 2255 0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22, 2256 0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0, 2257 0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9, 2258 0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89, 2259 0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0, 2260 0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484, 2261 0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80, 2262 0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624, 2263 0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4, 2264 0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027, 2265 0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903, 2266 0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809, 2267 0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46, 2268 0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47, 2269 0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0, 2270 0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516, 2271 0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E, 2272 0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C, 2273 0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180, 2274 0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E, 2275 0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0, 2276 0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0, 2277 0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0, 2278 0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F, 2279 0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 2280 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 2281 }; 2282 2283 2284 /* 2285 * initialize ASSP 2286 */ 2287 2288 #define MINISRC_LPF_LEN 10 2289 static u16 minisrc_lpf[MINISRC_LPF_LEN] __devinitdata = { 2290 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C, 2291 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F 2292 }; 2293 2294 static void __devinit snd_m3_assp_init(m3_t *chip) 2295 { 2296 unsigned int i; 2297 2298 /* zero kernel data */ 2299 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) 2300 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2301 KDATA_BASE_ADDR + i, 0); 2302 2303 /* zero mixer data? */ 2304 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++) 2305 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2306 KDATA_BASE_ADDR2 + i, 0); 2307 2308 /* init dma pointer */ 2309 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2310 KDATA_CURRENT_DMA, 2311 KDATA_DMA_XFER0); 2312 2313 /* write kernel into code memory.. */ 2314 for (i = 0 ; i < ARRAY_SIZE(assp_kernel_image); i++) { 2315 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2316 REV_B_CODE_MEMORY_BEGIN + i, 2317 assp_kernel_image[i]); 2318 } 2319 2320 /* 2321 * We only have this one client and we know that 0x400 2322 * is free in our kernel's mem map, so lets just 2323 * drop it there. It seems that the minisrc doesn't 2324 * need vectors, so we won't bother with them.. 2325 */ 2326 for (i = 0; i < ARRAY_SIZE(assp_minisrc_image); i++) { 2327 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2328 0x400 + i, 2329 assp_minisrc_image[i]); 2330 } 2331 2332 /* 2333 * write the coefficients for the low pass filter? 2334 */ 2335 for (i = 0; i < MINISRC_LPF_LEN ; i++) { 2336 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2337 0x400 + MINISRC_COEF_LOC + i, 2338 minisrc_lpf[i]); 2339 } 2340 2341 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, 2342 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN, 2343 0x8000); 2344 2345 /* 2346 * the minisrc is the only thing on 2347 * our task list.. 2348 */ 2349 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2350 KDATA_TASK0, 2351 0x400); 2352 2353 /* 2354 * init the mixer number.. 2355 */ 2356 2357 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2358 KDATA_MIXER_TASK_NUMBER,0); 2359 2360 /* 2361 * EXTREME KERNEL MASTER VOLUME 2362 */ 2363 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2364 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME); 2365 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2366 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME); 2367 2368 chip->mixer_list.curlen = 0; 2369 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0; 2370 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS; 2371 chip->adc1_list.curlen = 0; 2372 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0; 2373 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS; 2374 chip->dma_list.curlen = 0; 2375 chip->dma_list.mem_addr = KDATA_DMA_XFER0; 2376 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS; 2377 chip->msrc_list.curlen = 0; 2378 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC; 2379 chip->msrc_list.max = MAX_INSTANCE_MINISRC; 2380 } 2381 2382 2383 static int __devinit snd_m3_assp_client_init(m3_t *chip, m3_dma_t *s, int index) 2384 { 2385 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 + 2386 MINISRC_IN_BUFFER_SIZE / 2 + 2387 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 ); 2388 int address, i; 2389 2390 /* 2391 * the revb memory map has 0x1100 through 0x1c00 2392 * free. 2393 */ 2394 2395 /* 2396 * align instance address to 256 bytes so that it's 2397 * shifted list address is aligned. 2398 * list address = (mem address >> 1) >> 7; 2399 */ 2400 data_bytes = (data_bytes + 255) & ~255; 2401 address = 0x1100 + ((data_bytes/2) * index); 2402 2403 if ((address + (data_bytes/2)) >= 0x1c00) { 2404 snd_printk("no memory for %d bytes at ind %d (addr 0x%x)\n", 2405 data_bytes, index, address); 2406 return -ENOMEM; 2407 } 2408 2409 s->number = index; 2410 s->inst.code = 0x400; 2411 s->inst.data = address; 2412 2413 for (i = data_bytes / 2; i > 0; address++, i--) { 2414 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2415 address, 0); 2416 } 2417 2418 return 0; 2419 } 2420 2421 2422 /* 2423 * this works for the reference board, have to find 2424 * out about others 2425 * 2426 * this needs more magic for 4 speaker, but.. 2427 */ 2428 static void 2429 snd_m3_amp_enable(m3_t *chip, int enable) 2430 { 2431 int io = chip->iobase; 2432 u16 gpo, polarity; 2433 2434 if (! chip->external_amp) 2435 return; 2436 2437 polarity = enable ? 0 : 1; 2438 polarity = polarity << chip->amp_gpio; 2439 gpo = 1 << chip->amp_gpio; 2440 2441 outw(~gpo, io + GPIO_MASK); 2442 2443 outw(inw(io + GPIO_DIRECTION) | gpo, 2444 io + GPIO_DIRECTION); 2445 2446 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity), 2447 io + GPIO_DATA); 2448 2449 outw(0xffff, io + GPIO_MASK); 2450 } 2451 2452 static int 2453 snd_m3_chip_init(m3_t *chip) 2454 { 2455 struct pci_dev *pcidev = chip->pci; 2456 unsigned long io = chip->iobase; 2457 u32 n; 2458 u16 w; 2459 u8 t; /* makes as much sense as 'n', no? */ 2460 2461 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w); 2462 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE| 2463 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO| 2464 DISABLE_LEGACY); 2465 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w); 2466 2467 if (chip->hv_quirk && chip->hv_quirk->is_omnibook) { 2468 /* 2469 * Volume buttons on some HP OmniBook laptops don't work 2470 * correctly. This makes them work for the most part. 2471 * 2472 * Volume up and down buttons on the laptop side work. 2473 * Fn+cursor_up (volme up) works. 2474 * Fn+cursor_down (volume down) doesn't work. 2475 * Fn+F7 (mute) works acts as volume up. 2476 */ 2477 outw(~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_MASK); 2478 outw(inw(io + GPIO_DIRECTION) & ~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DIRECTION); 2479 outw((GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DATA); 2480 outw(0xffff, io + GPIO_MASK); 2481 } 2482 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); 2483 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD); 2484 if (chip->hv_quirk) 2485 n |= chip->hv_quirk->config; 2486 /* For some reason we must always use reduced debounce. */ 2487 n |= REDUCED_DEBOUNCE; 2488 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING; 2489 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); 2490 2491 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B); 2492 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n); 2493 n &= ~INT_CLK_SELECT; 2494 if (!chip->allegro_flag) { 2495 n &= ~INT_CLK_MULT_ENABLE; 2496 n |= INT_CLK_SRC_NOT_PCI; 2497 } 2498 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 ); 2499 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n); 2500 2501 if (chip->allegro_flag) { 2502 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n); 2503 n |= IN_CLK_12MHZ_SELECT; 2504 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n); 2505 } 2506 2507 t = inb(chip->iobase + ASSP_CONTROL_A); 2508 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT); 2509 t |= ASSP_CLK_49MHZ_SELECT; 2510 t |= ASSP_0_WS_ENABLE; 2511 outb(t, chip->iobase + ASSP_CONTROL_A); 2512 2513 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B); 2514 2515 outb(0x00, io + HARDWARE_VOL_CTRL); 2516 outb(0x88, io + SHADOW_MIX_REG_VOICE); 2517 outb(0x88, io + HW_VOL_COUNTER_VOICE); 2518 outb(0x88, io + SHADOW_MIX_REG_MASTER); 2519 outb(0x88, io + HW_VOL_COUNTER_MASTER); 2520 2521 return 0; 2522 } 2523 2524 static void 2525 snd_m3_enable_ints(m3_t *chip) 2526 { 2527 unsigned long io = chip->iobase; 2528 2529 /* TODO: MPU401 not supported yet */ 2530 outw(ASSP_INT_ENABLE | HV_INT_ENABLE /*| MPU401_INT_ENABLE*/, io + HOST_INT_CTRL); 2531 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE, 2532 io + ASSP_CONTROL_C); 2533 } 2534 2535 2536 /* 2537 */ 2538 2539 static int snd_m3_free(m3_t *chip) 2540 { 2541 m3_dma_t *s; 2542 int i; 2543 2544 if (chip->substreams) { 2545 spin_lock_irq(&chip->reg_lock); 2546 for (i = 0; i < chip->num_substreams; i++) { 2547 s = &chip->substreams[i]; 2548 /* check surviving pcms; this should not happen though.. */ 2549 if (s->substream && s->running) 2550 snd_m3_pcm_stop(chip, s, s->substream); 2551 } 2552 spin_unlock_irq(&chip->reg_lock); 2553 kfree(chip->substreams); 2554 } 2555 if (chip->iobase) { 2556 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */ 2557 } 2558 2559 #ifdef CONFIG_PM 2560 vfree(chip->suspend_mem); 2561 #endif 2562 2563 if (chip->irq >= 0) { 2564 synchronize_irq(chip->irq); 2565 free_irq(chip->irq, (void *)chip); 2566 } 2567 2568 if (chip->iobase) 2569 pci_release_regions(chip->pci); 2570 2571 pci_disable_device(chip->pci); 2572 kfree(chip); 2573 return 0; 2574 } 2575 2576 2577 /* 2578 * APM support 2579 */ 2580 #ifdef CONFIG_PM 2581 static int m3_suspend(snd_card_t *card, pm_message_t state) 2582 { 2583 m3_t *chip = card->pm_private_data; 2584 int i, index; 2585 2586 if (chip->suspend_mem == NULL) 2587 return 0; 2588 2589 snd_pcm_suspend_all(chip->pcm); 2590 snd_ac97_suspend(chip->ac97); 2591 2592 big_mdelay(10); /* give the assp a chance to idle.. */ 2593 2594 snd_m3_assp_halt(chip); 2595 2596 /* save dsp image */ 2597 index = 0; 2598 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 2599 chip->suspend_mem[index++] = 2600 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i); 2601 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) 2602 chip->suspend_mem[index++] = 2603 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i); 2604 2605 /* power down apci registers */ 2606 snd_m3_outw(chip, 0xffff, 0x54); 2607 snd_m3_outw(chip, 0xffff, 0x56); 2608 2609 pci_disable_device(chip->pci); 2610 return 0; 2611 } 2612 2613 static int m3_resume(snd_card_t *card) 2614 { 2615 m3_t *chip = card->pm_private_data; 2616 int i, index; 2617 2618 if (chip->suspend_mem == NULL) 2619 return 0; 2620 2621 pci_enable_device(chip->pci); 2622 pci_set_master(chip->pci); 2623 2624 /* first lets just bring everything back. .*/ 2625 snd_m3_outw(chip, 0, 0x54); 2626 snd_m3_outw(chip, 0, 0x56); 2627 2628 snd_m3_chip_init(chip); 2629 snd_m3_assp_halt(chip); 2630 snd_m3_ac97_reset(chip); 2631 2632 /* restore dsp image */ 2633 index = 0; 2634 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++) 2635 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i, 2636 chip->suspend_mem[index++]); 2637 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++) 2638 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i, 2639 chip->suspend_mem[index++]); 2640 2641 /* tell the dma engine to restart itself */ 2642 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, 2643 KDATA_DMA_ACTIVE, 0); 2644 2645 /* restore ac97 registers */ 2646 snd_ac97_resume(chip->ac97); 2647 2648 snd_m3_assp_continue(chip); 2649 snd_m3_enable_ints(chip); 2650 snd_m3_amp_enable(chip, 1); 2651 2652 return 0; 2653 } 2654 #endif /* CONFIG_PM */ 2655 2656 2657 /* 2658 */ 2659 2660 static int snd_m3_dev_free(snd_device_t *device) 2661 { 2662 m3_t *chip = device->device_data; 2663 return snd_m3_free(chip); 2664 } 2665 2666 static int __devinit 2667 snd_m3_create(snd_card_t *card, struct pci_dev *pci, 2668 int enable_amp, 2669 int amp_gpio, 2670 m3_t **chip_ret) 2671 { 2672 m3_t *chip; 2673 int i, err; 2674 struct m3_quirk *quirk; 2675 struct m3_hv_quirk *hv_quirk; 2676 static snd_device_ops_t ops = { 2677 .dev_free = snd_m3_dev_free, 2678 }; 2679 2680 *chip_ret = NULL; 2681 2682 if (pci_enable_device(pci)) 2683 return -EIO; 2684 2685 /* check, if we can restrict PCI DMA transfers to 28 bits */ 2686 if (pci_set_dma_mask(pci, 0x0fffffff) < 0 || 2687 pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) { 2688 snd_printk("architecture does not support 28bit PCI busmaster DMA\n"); 2689 pci_disable_device(pci); 2690 return -ENXIO; 2691 } 2692 2693 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL); 2694 if (chip == NULL) { 2695 pci_disable_device(pci); 2696 return -ENOMEM; 2697 } 2698 2699 spin_lock_init(&chip->reg_lock); 2700 switch (pci->device) { 2701 case PCI_DEVICE_ID_ESS_ALLEGRO: 2702 case PCI_DEVICE_ID_ESS_ALLEGRO_1: 2703 case PCI_DEVICE_ID_ESS_CANYON3D_2LE: 2704 case PCI_DEVICE_ID_ESS_CANYON3D_2: 2705 chip->allegro_flag = 1; 2706 break; 2707 } 2708 2709 chip->card = card; 2710 chip->pci = pci; 2711 chip->irq = -1; 2712 2713 for (quirk = m3_quirk_list; quirk->vendor; quirk++) { 2714 if (pci->subsystem_vendor == quirk->vendor && 2715 pci->subsystem_device == quirk->device) { 2716 printk(KERN_INFO "maestro3: enabled hack for '%s'\n", quirk->name); 2717 chip->quirk = quirk; 2718 break; 2719 } 2720 } 2721 2722 for (hv_quirk = m3_hv_quirk_list; hv_quirk->vendor; hv_quirk++) { 2723 if (pci->vendor == hv_quirk->vendor && 2724 pci->device == hv_quirk->device && 2725 pci->subsystem_vendor == hv_quirk->subsystem_vendor && 2726 pci->subsystem_device == hv_quirk->subsystem_device) { 2727 chip->hv_quirk = hv_quirk; 2728 break; 2729 } 2730 } 2731 2732 chip->external_amp = enable_amp; 2733 if (amp_gpio >= 0 && amp_gpio <= 0x0f) 2734 chip->amp_gpio = amp_gpio; 2735 else if (chip->quirk && chip->quirk->amp_gpio >= 0) 2736 chip->amp_gpio = chip->quirk->amp_gpio; 2737 else if (chip->allegro_flag) 2738 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO; 2739 else /* presumably this is for all 'maestro3's.. */ 2740 chip->amp_gpio = GPO_EXT_AMP_M3; 2741 2742 chip->num_substreams = NR_DSPS; 2743 chip->substreams = kmalloc(sizeof(m3_dma_t) * chip->num_substreams, GFP_KERNEL); 2744 if (chip->substreams == NULL) { 2745 kfree(chip); 2746 pci_disable_device(pci); 2747 return -ENOMEM; 2748 } 2749 memset(chip->substreams, 0, sizeof(m3_dma_t) * chip->num_substreams); 2750 2751 if ((err = pci_request_regions(pci, card->driver)) < 0) { 2752 snd_m3_free(chip); 2753 return err; 2754 } 2755 chip->iobase = pci_resource_start(pci, 0); 2756 2757 /* just to be sure */ 2758 pci_set_master(pci); 2759 2760 snd_m3_chip_init(chip); 2761 snd_m3_assp_halt(chip); 2762 2763 snd_m3_ac97_reset(chip); 2764 2765 snd_m3_assp_init(chip); 2766 snd_m3_amp_enable(chip, 1); 2767 2768 if (request_irq(pci->irq, snd_m3_interrupt, SA_INTERRUPT|SA_SHIRQ, 2769 card->driver, (void *)chip)) { 2770 snd_printk("unable to grab IRQ %d\n", pci->irq); 2771 snd_m3_free(chip); 2772 return -ENOMEM; 2773 } 2774 chip->irq = pci->irq; 2775 2776 #ifdef CONFIG_PM 2777 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH)); 2778 if (chip->suspend_mem == NULL) 2779 snd_printk(KERN_WARNING "can't allocate apm buffer\n"); 2780 else 2781 snd_card_set_pm_callback(card, m3_suspend, m3_resume, chip); 2782 #endif 2783 2784 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 2785 snd_m3_free(chip); 2786 return err; 2787 } 2788 2789 spin_lock_init(&chip->ac97_lock); 2790 tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip); 2791 2792 if ((err = snd_m3_mixer(chip)) < 0) 2793 return err; 2794 2795 for (i = 0; i < chip->num_substreams; i++) { 2796 m3_dma_t *s = &chip->substreams[i]; 2797 s->chip = chip; 2798 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0) 2799 return err; 2800 } 2801 2802 if ((err = snd_m3_pcm(chip, 0)) < 0) 2803 return err; 2804 2805 snd_m3_enable_ints(chip); 2806 snd_m3_assp_continue(chip); 2807 2808 snd_card_set_dev(card, &pci->dev); 2809 2810 *chip_ret = chip; 2811 2812 return 0; 2813 } 2814 2815 /* 2816 */ 2817 static int __devinit 2818 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2819 { 2820 static int dev; 2821 snd_card_t *card; 2822 m3_t *chip; 2823 int err; 2824 2825 /* don't pick up modems */ 2826 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO) 2827 return -ENODEV; 2828 2829 if (dev >= SNDRV_CARDS) 2830 return -ENODEV; 2831 if (!enable[dev]) { 2832 dev++; 2833 return -ENOENT; 2834 } 2835 2836 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2837 if (card == NULL) 2838 return -ENOMEM; 2839 2840 switch (pci->device) { 2841 case PCI_DEVICE_ID_ESS_ALLEGRO: 2842 case PCI_DEVICE_ID_ESS_ALLEGRO_1: 2843 strcpy(card->driver, "Allegro"); 2844 break; 2845 case PCI_DEVICE_ID_ESS_CANYON3D_2LE: 2846 case PCI_DEVICE_ID_ESS_CANYON3D_2: 2847 strcpy(card->driver, "Canyon3D-2"); 2848 break; 2849 default: 2850 strcpy(card->driver, "Maestro3"); 2851 break; 2852 } 2853 2854 if ((err = snd_m3_create(card, pci, 2855 external_amp[dev], 2856 amp_gpio[dev], 2857 &chip)) < 0) { 2858 snd_card_free(card); 2859 return err; 2860 } 2861 2862 sprintf(card->shortname, "ESS %s PCI", card->driver); 2863 sprintf(card->longname, "%s at 0x%lx, irq %d", 2864 card->shortname, chip->iobase, chip->irq); 2865 2866 if ((err = snd_card_register(card)) < 0) { 2867 snd_card_free(card); 2868 return err; 2869 } 2870 2871 #if 0 /* TODO: not supported yet */ 2872 /* TODO enable midi irq and i/o */ 2873 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401, 2874 chip->iobase + MPU401_DATA_PORT, 1, 2875 chip->irq, 0, &chip->rmidi); 2876 if (err < 0) 2877 printk(KERN_WARNING "maestro3: no midi support.\n"); 2878 #endif 2879 2880 pci_set_drvdata(pci, card); 2881 dev++; 2882 return 0; 2883 } 2884 2885 static void __devexit snd_m3_remove(struct pci_dev *pci) 2886 { 2887 snd_card_free(pci_get_drvdata(pci)); 2888 pci_set_drvdata(pci, NULL); 2889 } 2890 2891 static struct pci_driver driver = { 2892 .name = "Maestro3", 2893 .id_table = snd_m3_ids, 2894 .probe = snd_m3_probe, 2895 .remove = __devexit_p(snd_m3_remove), 2896 SND_PCI_PM_CALLBACKS 2897 }; 2898 2899 static int __init alsa_card_m3_init(void) 2900 { 2901 return pci_register_driver(&driver); 2902 } 2903 2904 static void __exit alsa_card_m3_exit(void) 2905 { 2906 pci_unregister_driver(&driver); 2907 } 2908 2909 module_init(alsa_card_m3_init) 2910 module_exit(alsa_card_m3_exit) 2911