1 /* 2 * ALSA driver for Intel ICH (i8x0) chipsets 3 * 4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz> 5 * 6 * 7 * This code also contains alpha support for SiS 735 chipsets provided 8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet 9 * for SiS735, so the code is not fully functional. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 26 * 27 */ 28 29 #include <sound/driver.h> 30 #include <asm/io.h> 31 #include <linux/delay.h> 32 #include <linux/interrupt.h> 33 #include <linux/init.h> 34 #include <linux/pci.h> 35 #include <linux/slab.h> 36 #include <linux/moduleparam.h> 37 #include <sound/core.h> 38 #include <sound/pcm.h> 39 #include <sound/ac97_codec.h> 40 #include <sound/info.h> 41 #include <sound/initval.h> 42 /* for 440MX workaround */ 43 #include <asm/pgtable.h> 44 #include <asm/cacheflush.h> 45 46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); 47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455"); 48 MODULE_LICENSE("GPL"); 49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 50 "{Intel,82901AB-ICH0}," 51 "{Intel,82801BA-ICH2}," 52 "{Intel,82801CA-ICH3}," 53 "{Intel,82801DB-ICH4}," 54 "{Intel,ICH5}," 55 "{Intel,ICH6}," 56 "{Intel,ICH7}," 57 "{Intel,6300ESB}," 58 "{Intel,ESB2}," 59 "{Intel,MX440}," 60 "{SiS,SI7012}," 61 "{NVidia,nForce Audio}," 62 "{NVidia,nForce2 Audio}," 63 "{AMD,AMD768}," 64 "{AMD,AMD8111}," 65 "{ALI,M5455}}"); 66 67 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ 68 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 69 static int ac97_clock; 70 static char *ac97_quirk; 71 static int buggy_semaphore; 72 static int buggy_irq = -1; /* auto-check */ 73 static int xbox; 74 static int spdif_aclink = -1; 75 76 module_param(index, int, 0444); 77 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard."); 78 module_param(id, charp, 0444); 79 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard."); 80 module_param(ac97_clock, int, 0444); 81 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); 82 module_param(ac97_quirk, charp, 0444); 83 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 84 module_param(buggy_semaphore, bool, 0444); 85 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores."); 86 module_param(buggy_irq, bool, 0444); 87 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards."); 88 module_param(xbox, bool, 0444); 89 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection."); 90 module_param(spdif_aclink, int, 0444); 91 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); 92 93 /* just for backward compatibility */ 94 static int enable; 95 module_param(enable, bool, 0444); 96 static int joystick; 97 module_param(joystick, int, 0444); 98 99 /* 100 * Direct registers 101 */ 102 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 103 104 #define ICHREG(x) ICH_REG_##x 105 106 #define DEFINE_REGSET(name,base) \ 107 enum { \ 108 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 109 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 110 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 111 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 112 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 113 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 114 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 115 }; 116 117 /* busmaster blocks */ 118 DEFINE_REGSET(OFF, 0); /* offset */ 119 DEFINE_REGSET(PI, 0x00); /* PCM in */ 120 DEFINE_REGSET(PO, 0x10); /* PCM out */ 121 DEFINE_REGSET(MC, 0x20); /* Mic in */ 122 123 /* ICH4 busmaster blocks */ 124 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */ 125 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */ 126 DEFINE_REGSET(SP, 0x60); /* SPDIF out */ 127 128 /* values for each busmaster block */ 129 130 /* LVI */ 131 #define ICH_REG_LVI_MASK 0x1f 132 133 /* SR */ 134 #define ICH_FIFOE 0x10 /* FIFO error */ 135 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 136 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 137 #define ICH_CELV 0x02 /* current equals last valid */ 138 #define ICH_DCH 0x01 /* DMA controller halted */ 139 140 /* PIV */ 141 #define ICH_REG_PIV_MASK 0x1f /* mask */ 142 143 /* CR */ 144 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 145 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 146 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 147 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 148 #define ICH_STARTBM 0x01 /* start busmaster operation */ 149 150 151 /* global block */ 152 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */ 153 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ 154 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ 155 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ 156 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ 157 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ 158 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ 159 #define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */ 160 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ 161 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ 162 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ 163 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ 164 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ 165 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ 166 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ 167 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 168 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 169 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 170 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 171 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 172 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 173 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 174 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */ 175 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 176 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 177 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 178 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 179 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 180 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 181 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 182 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ 183 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 184 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */ 185 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */ 186 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 187 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 188 #define ICH_RCS 0x00008000 /* read completion status */ 189 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 190 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 191 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 192 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 193 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 194 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 195 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 196 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 197 #define ICH_POINT 0x00000040 /* playback interrupt */ 198 #define ICH_PIINT 0x00000020 /* capture interrupt */ 199 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 200 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 201 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 202 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 203 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ 204 #define ICH_CAS 0x01 /* codec access semaphore */ 205 #define ICH_REG_SDM 0x80 206 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ 207 #define ICH_DI2L_SHIFT 6 208 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ 209 #define ICH_DI1L_SHIFT 4 210 #define ICH_SE 0x00000008 /* steer enable */ 211 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */ 212 213 #define ICH_MAX_FRAGS 32 /* max hw frags */ 214 215 216 /* 217 * registers for Ali5455 218 */ 219 220 /* ALi 5455 busmaster blocks */ 221 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */ 222 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */ 223 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */ 224 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */ 225 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */ 226 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */ 227 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */ 228 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */ 229 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */ 230 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */ 231 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */ 232 233 enum { 234 ICH_REG_ALI_SCR = 0x00, /* System Control Register */ 235 ICH_REG_ALI_SSR = 0x04, /* System Status Register */ 236 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */ 237 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */ 238 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */ 239 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */ 240 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */ 241 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */ 242 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */ 243 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */ 244 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */ 245 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */ 246 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */ 247 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */ 248 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */ 249 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */ 250 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */ 251 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */ 252 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */ 253 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */ 254 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */ 255 }; 256 257 #define ALI_CAS_SEM_BUSY 0x80000000 258 #define ALI_CPR_ADDR_SECONDARY 0x100 259 #define ALI_CPR_ADDR_READ 0x80 260 #define ALI_CSPSR_CODEC_READY 0x08 261 #define ALI_CSPSR_READ_OK 0x02 262 #define ALI_CSPSR_WRITE_OK 0x01 263 264 /* interrupts for the whole chip by interrupt status register finish */ 265 266 #define ALI_INT_MICIN2 (1<<26) 267 #define ALI_INT_PCMIN2 (1<<25) 268 #define ALI_INT_I2SIN (1<<24) 269 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ 270 #define ALI_INT_SPDIFIN (1<<22) 271 #define ALI_INT_LFEOUT (1<<21) 272 #define ALI_INT_CENTEROUT (1<<20) 273 #define ALI_INT_CODECSPDIFOUT (1<<19) 274 #define ALI_INT_MICIN (1<<18) 275 #define ALI_INT_PCMOUT (1<<17) 276 #define ALI_INT_PCMIN (1<<16) 277 #define ALI_INT_CPRAIS (1<<7) /* command port available */ 278 #define ALI_INT_SPRAIS (1<<5) /* status port available */ 279 #define ALI_INT_GPIO (1<<1) 280 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\ 281 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN) 282 283 #define ICH_ALI_SC_RESET (1<<31) /* master reset */ 284 #define ICH_ALI_SC_AC97_DBL (1<<30) 285 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ 286 #define ICH_ALI_SC_IN_BITS (3<<18) 287 #define ICH_ALI_SC_OUT_BITS (3<<16) 288 #define ICH_ALI_SC_6CH_CFG (3<<14) 289 #define ICH_ALI_SC_PCM_4 (1<<8) 290 #define ICH_ALI_SC_PCM_6 (2<<8) 291 #define ICH_ALI_SC_PCM_246_MASK (3<<8) 292 293 #define ICH_ALI_SS_SEC_ID (3<<5) 294 #define ICH_ALI_SS_PRI_ID (3<<3) 295 296 #define ICH_ALI_IF_AC97SP (1<<21) 297 #define ICH_ALI_IF_MC (1<<20) 298 #define ICH_ALI_IF_PI (1<<19) 299 #define ICH_ALI_IF_MC2 (1<<18) 300 #define ICH_ALI_IF_PI2 (1<<17) 301 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ 302 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ 303 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ 304 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ 305 #define ICH_ALI_IF_PO_SPDF (1<<3) 306 #define ICH_ALI_IF_PO (1<<1) 307 308 /* 309 * 310 */ 311 312 enum { 313 ICHD_PCMIN, 314 ICHD_PCMOUT, 315 ICHD_MIC, 316 ICHD_MIC2, 317 ICHD_PCM2IN, 318 ICHD_SPBAR, 319 ICHD_LAST = ICHD_SPBAR 320 }; 321 enum { 322 NVD_PCMIN, 323 NVD_PCMOUT, 324 NVD_MIC, 325 NVD_SPBAR, 326 NVD_LAST = NVD_SPBAR 327 }; 328 enum { 329 ALID_PCMIN, 330 ALID_PCMOUT, 331 ALID_MIC, 332 ALID_AC97SPDIFOUT, 333 ALID_SPDIFIN, 334 ALID_SPDIFOUT, 335 ALID_LAST = ALID_SPDIFOUT 336 }; 337 338 #define get_ichdev(substream) (substream->runtime->private_data) 339 340 struct ichdev { 341 unsigned int ichd; /* ich device number */ 342 unsigned long reg_offset; /* offset to bmaddr */ 343 u32 *bdbar; /* CPU address (32bit) */ 344 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 345 struct snd_pcm_substream *substream; 346 unsigned int physbuf; /* physical address (32bit) */ 347 unsigned int size; 348 unsigned int fragsize; 349 unsigned int fragsize1; 350 unsigned int position; 351 unsigned int pos_shift; 352 int frags; 353 int lvi; 354 int lvi_frag; 355 int civ; 356 int ack; 357 int ack_reload; 358 unsigned int ack_bit; 359 unsigned int roff_sr; 360 unsigned int roff_picb; 361 unsigned int int_sta_mask; /* interrupt status mask */ 362 unsigned int ali_slot; /* ALI DMA slot */ 363 struct ac97_pcm *pcm; 364 int pcm_open_flag; 365 unsigned int page_attr_changed: 1; 366 unsigned int suspended: 1; 367 }; 368 369 struct intel8x0 { 370 unsigned int device_type; 371 372 int irq; 373 374 void __iomem *addr; 375 void __iomem *bmaddr; 376 377 struct pci_dev *pci; 378 struct snd_card *card; 379 380 int pcm_devs; 381 struct snd_pcm *pcm[6]; 382 struct ichdev ichd[6]; 383 384 unsigned multi4: 1, 385 multi6: 1, 386 dra: 1, 387 smp20bit: 1; 388 unsigned in_ac97_init: 1, 389 in_sdin_init: 1; 390 unsigned in_measurement: 1; /* during ac97 clock measurement */ 391 unsigned fix_nocache: 1; /* workaround for 440MX */ 392 unsigned buggy_irq: 1; /* workaround for buggy mobos */ 393 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */ 394 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */ 395 396 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */ 397 unsigned int sdm_saved; /* SDM reg value */ 398 399 struct snd_ac97_bus *ac97_bus; 400 struct snd_ac97 *ac97[3]; 401 unsigned int ac97_sdin[3]; 402 unsigned int max_codecs, ncodecs; 403 unsigned int *codec_bit; 404 unsigned int codec_isr_bits; 405 unsigned int codec_ready_bits; 406 407 spinlock_t reg_lock; 408 409 u32 bdbars_count; 410 struct snd_dma_buffer bdbars; 411 u32 int_sta_reg; /* interrupt status register */ 412 u32 int_sta_mask; /* interrupt status mask */ 413 }; 414 415 static struct pci_device_id snd_intel8x0_ids[] = { 416 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */ 417 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */ 418 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */ 419 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */ 420 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */ 421 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */ 422 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */ 423 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */ 424 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */ 425 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */ 426 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */ 427 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */ 428 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */ 429 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */ 430 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */ 431 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */ 432 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */ 433 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */ 434 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */ 435 { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP51 */ 436 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */ 437 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */ 438 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */ 439 { 0, } 440 }; 441 442 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids); 443 444 /* 445 * Lowlevel I/O - busmaster 446 */ 447 448 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset) 449 { 450 return ioread8(chip->bmaddr + offset); 451 } 452 453 static inline u16 igetword(struct intel8x0 *chip, u32 offset) 454 { 455 return ioread16(chip->bmaddr + offset); 456 } 457 458 static inline u32 igetdword(struct intel8x0 *chip, u32 offset) 459 { 460 return ioread32(chip->bmaddr + offset); 461 } 462 463 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val) 464 { 465 iowrite8(val, chip->bmaddr + offset); 466 } 467 468 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val) 469 { 470 iowrite16(val, chip->bmaddr + offset); 471 } 472 473 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val) 474 { 475 iowrite32(val, chip->bmaddr + offset); 476 } 477 478 /* 479 * Lowlevel I/O - AC'97 registers 480 */ 481 482 static inline u16 iagetword(struct intel8x0 *chip, u32 offset) 483 { 484 return ioread16(chip->addr + offset); 485 } 486 487 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val) 488 { 489 iowrite16(val, chip->addr + offset); 490 } 491 492 /* 493 * Basic I/O 494 */ 495 496 /* 497 * access to AC97 codec via normal i/o (for ICH and SIS7012) 498 */ 499 500 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec) 501 { 502 int time; 503 504 if (codec > 2) 505 return -EIO; 506 if (chip->in_sdin_init) { 507 /* we don't know the ready bit assignment at the moment */ 508 /* so we check any */ 509 codec = chip->codec_isr_bits; 510 } else { 511 codec = chip->codec_bit[chip->ac97_sdin[codec]]; 512 } 513 514 /* codec ready ? */ 515 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 516 return -EIO; 517 518 if (chip->buggy_semaphore) 519 return 0; /* just ignore ... */ 520 521 /* Anyone holding a semaphore for 1 msec should be shot... */ 522 time = 100; 523 do { 524 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 525 return 0; 526 udelay(10); 527 } while (time--); 528 529 /* access to some forbidden (non existant) ac97 registers will not 530 * reset the semaphore. So even if you don't get the semaphore, still 531 * continue the access. We don't need the semaphore anyway. */ 532 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 533 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 534 iagetword(chip, 0); /* clear semaphore flag */ 535 /* I don't care about the semaphore */ 536 return -EBUSY; 537 } 538 539 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97, 540 unsigned short reg, 541 unsigned short val) 542 { 543 struct intel8x0 *chip = ac97->private_data; 544 545 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 546 if (! chip->in_ac97_init) 547 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 548 } 549 iaputword(chip, reg + ac97->num * 0x80, val); 550 } 551 552 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97, 553 unsigned short reg) 554 { 555 struct intel8x0 *chip = ac97->private_data; 556 unsigned short res; 557 unsigned int tmp; 558 559 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 560 if (! chip->in_ac97_init) 561 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 562 res = 0xffff; 563 } else { 564 res = iagetword(chip, reg + ac97->num * 0x80); 565 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 566 /* reset RCS and preserve other R/WC bits */ 567 iputdword(chip, ICHREG(GLOB_STA), tmp & 568 ~(chip->codec_ready_bits | ICH_GSCI)); 569 if (! chip->in_ac97_init) 570 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); 571 res = 0xffff; 572 } 573 } 574 return res; 575 } 576 577 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip, 578 unsigned int codec) 579 { 580 unsigned int tmp; 581 582 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) { 583 iagetword(chip, codec * 0x80); 584 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 585 /* reset RCS and preserve other R/WC bits */ 586 iputdword(chip, ICHREG(GLOB_STA), tmp & 587 ~(chip->codec_ready_bits | ICH_GSCI)); 588 } 589 } 590 } 591 592 /* 593 * access to AC97 for Ali5455 594 */ 595 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask) 596 { 597 int count = 0; 598 for (count = 0; count < 0x7f; count++) { 599 int val = igetbyte(chip, ICHREG(ALI_CSPSR)); 600 if (val & mask) 601 return 0; 602 } 603 if (! chip->in_ac97_init) 604 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n"); 605 return -EBUSY; 606 } 607 608 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip) 609 { 610 int time = 100; 611 if (chip->buggy_semaphore) 612 return 0; /* just ignore ... */ 613 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY)) 614 udelay(1); 615 if (! time && ! chip->in_ac97_init) 616 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n"); 617 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY); 618 } 619 620 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg) 621 { 622 struct intel8x0 *chip = ac97->private_data; 623 unsigned short data = 0xffff; 624 625 if (snd_intel8x0_ali_codec_semaphore(chip)) 626 goto __err; 627 reg |= ALI_CPR_ADDR_READ; 628 if (ac97->num) 629 reg |= ALI_CPR_ADDR_SECONDARY; 630 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 631 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK)) 632 goto __err; 633 data = igetword(chip, ICHREG(ALI_SPR)); 634 __err: 635 return data; 636 } 637 638 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg, 639 unsigned short val) 640 { 641 struct intel8x0 *chip = ac97->private_data; 642 643 if (snd_intel8x0_ali_codec_semaphore(chip)) 644 return; 645 iputword(chip, ICHREG(ALI_CPR), val); 646 if (ac97->num) 647 reg |= ALI_CPR_ADDR_SECONDARY; 648 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 649 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK); 650 } 651 652 653 /* 654 * DMA I/O 655 */ 656 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 657 { 658 int idx; 659 u32 *bdbar = ichdev->bdbar; 660 unsigned long port = ichdev->reg_offset; 661 662 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 663 if (ichdev->size == ichdev->fragsize) { 664 ichdev->ack_reload = ichdev->ack = 2; 665 ichdev->fragsize1 = ichdev->fragsize >> 1; 666 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 667 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 668 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 669 ichdev->fragsize1 >> ichdev->pos_shift); 670 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 671 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 672 ichdev->fragsize1 >> ichdev->pos_shift); 673 } 674 ichdev->frags = 2; 675 } else { 676 ichdev->ack_reload = ichdev->ack = 1; 677 ichdev->fragsize1 = ichdev->fragsize; 678 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 679 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + 680 (((idx >> 1) * ichdev->fragsize) % 681 ichdev->size)); 682 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 683 ichdev->fragsize >> ichdev->pos_shift); 684 #if 0 685 printk("bdbar[%i] = 0x%x [0x%x]\n", 686 idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 687 #endif 688 } 689 ichdev->frags = ichdev->size / ichdev->fragsize; 690 } 691 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 692 ichdev->civ = 0; 693 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 694 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 695 ichdev->position = 0; 696 #if 0 697 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 698 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1); 699 #endif 700 /* clear interrupts */ 701 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 702 } 703 704 #ifdef __i386__ 705 /* 706 * Intel 82443MX running a 100MHz processor system bus has a hardware bug, 707 * which aborts PCI busmaster for audio transfer. A workaround is to set 708 * the pages as non-cached. For details, see the errata in 709 * http://www.intel.com/design/chipsets/specupdt/245051.htm 710 */ 711 static void fill_nocache(void *buf, int size, int nocache) 712 { 713 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; 714 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL); 715 global_flush_tlb(); 716 } 717 #else 718 #define fill_nocache(buf,size,nocache) 719 #endif 720 721 /* 722 * Interrupt handler 723 */ 724 725 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev) 726 { 727 unsigned long port = ichdev->reg_offset; 728 unsigned long flags; 729 int status, civ, i, step; 730 int ack = 0; 731 732 spin_lock_irqsave(&chip->reg_lock, flags); 733 status = igetbyte(chip, port + ichdev->roff_sr); 734 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 735 if (!(status & ICH_BCIS)) { 736 step = 0; 737 } else if (civ == ichdev->civ) { 738 // snd_printd("civ same %d\n", civ); 739 step = 1; 740 ichdev->civ++; 741 ichdev->civ &= ICH_REG_LVI_MASK; 742 } else { 743 step = civ - ichdev->civ; 744 if (step < 0) 745 step += ICH_REG_LVI_MASK + 1; 746 // if (step != 1) 747 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 748 ichdev->civ = civ; 749 } 750 751 ichdev->position += step * ichdev->fragsize1; 752 if (! chip->in_measurement) 753 ichdev->position %= ichdev->size; 754 ichdev->lvi += step; 755 ichdev->lvi &= ICH_REG_LVI_MASK; 756 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 757 for (i = 0; i < step; i++) { 758 ichdev->lvi_frag++; 759 ichdev->lvi_frag %= ichdev->frags; 760 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); 761 #if 0 762 printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", 763 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], 764 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), 765 inl(port + 4), inb(port + ICH_REG_OFF_CR)); 766 #endif 767 if (--ichdev->ack == 0) { 768 ichdev->ack = ichdev->ack_reload; 769 ack = 1; 770 } 771 } 772 spin_unlock_irqrestore(&chip->reg_lock, flags); 773 if (ack && ichdev->substream) { 774 snd_pcm_period_elapsed(ichdev->substream); 775 } 776 iputbyte(chip, port + ichdev->roff_sr, 777 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI)); 778 } 779 780 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id) 781 { 782 struct intel8x0 *chip = dev_id; 783 struct ichdev *ichdev; 784 unsigned int status; 785 unsigned int i; 786 787 status = igetdword(chip, chip->int_sta_reg); 788 if (status == 0xffffffff) /* we are not yet resumed */ 789 return IRQ_NONE; 790 791 if ((status & chip->int_sta_mask) == 0) { 792 if (status) { 793 /* ack */ 794 iputdword(chip, chip->int_sta_reg, status); 795 if (! chip->buggy_irq) 796 status = 0; 797 } 798 return IRQ_RETVAL(status); 799 } 800 801 for (i = 0; i < chip->bdbars_count; i++) { 802 ichdev = &chip->ichd[i]; 803 if (status & ichdev->int_sta_mask) 804 snd_intel8x0_update(chip, ichdev); 805 } 806 807 /* ack them */ 808 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 809 810 return IRQ_HANDLED; 811 } 812 813 /* 814 * PCM part 815 */ 816 817 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 818 { 819 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 820 struct ichdev *ichdev = get_ichdev(substream); 821 unsigned char val = 0; 822 unsigned long port = ichdev->reg_offset; 823 824 switch (cmd) { 825 case SNDRV_PCM_TRIGGER_RESUME: 826 ichdev->suspended = 0; 827 /* fallthru */ 828 case SNDRV_PCM_TRIGGER_START: 829 val = ICH_IOCE | ICH_STARTBM; 830 break; 831 case SNDRV_PCM_TRIGGER_SUSPEND: 832 ichdev->suspended = 1; 833 /* fallthru */ 834 case SNDRV_PCM_TRIGGER_STOP: 835 val = 0; 836 break; 837 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 838 val = ICH_IOCE; 839 break; 840 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 841 val = ICH_IOCE | ICH_STARTBM; 842 break; 843 default: 844 return -EINVAL; 845 } 846 iputbyte(chip, port + ICH_REG_OFF_CR, val); 847 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 848 /* wait until DMA stopped */ 849 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 850 /* reset whole DMA things */ 851 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 852 } 853 return 0; 854 } 855 856 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd) 857 { 858 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 859 struct ichdev *ichdev = get_ichdev(substream); 860 unsigned long port = ichdev->reg_offset; 861 static int fiforeg[] = { 862 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) 863 }; 864 unsigned int val, fifo; 865 866 val = igetdword(chip, ICHREG(ALI_DMACR)); 867 switch (cmd) { 868 case SNDRV_PCM_TRIGGER_RESUME: 869 ichdev->suspended = 0; 870 /* fallthru */ 871 case SNDRV_PCM_TRIGGER_START: 872 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 873 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 874 /* clear FIFO for synchronization of channels */ 875 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]); 876 fifo &= ~(0xff << (ichdev->ali_slot % 4)); 877 fifo |= 0x83 << (ichdev->ali_slot % 4); 878 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo); 879 } 880 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 881 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */ 882 /* start DMA */ 883 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); 884 break; 885 case SNDRV_PCM_TRIGGER_SUSPEND: 886 ichdev->suspended = 1; 887 /* fallthru */ 888 case SNDRV_PCM_TRIGGER_STOP: 889 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 890 /* pause */ 891 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); 892 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 893 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 894 ; 895 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 896 break; 897 /* reset whole DMA things */ 898 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 899 /* clear interrupts */ 900 iputbyte(chip, port + ICH_REG_OFF_SR, 901 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e); 902 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 903 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask); 904 break; 905 default: 906 return -EINVAL; 907 } 908 return 0; 909 } 910 911 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream, 912 struct snd_pcm_hw_params *hw_params) 913 { 914 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 915 struct ichdev *ichdev = get_ichdev(substream); 916 struct snd_pcm_runtime *runtime = substream->runtime; 917 int dbl = params_rate(hw_params) > 48000; 918 int err; 919 920 if (chip->fix_nocache && ichdev->page_attr_changed) { 921 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */ 922 ichdev->page_attr_changed = 0; 923 } 924 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 925 if (err < 0) 926 return err; 927 if (chip->fix_nocache) { 928 if (runtime->dma_area && ! ichdev->page_attr_changed) { 929 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 930 ichdev->page_attr_changed = 1; 931 } 932 } 933 if (ichdev->pcm_open_flag) { 934 snd_ac97_pcm_close(ichdev->pcm); 935 ichdev->pcm_open_flag = 0; 936 } 937 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params), 938 params_channels(hw_params), 939 ichdev->pcm->r[dbl].slots); 940 if (err >= 0) { 941 ichdev->pcm_open_flag = 1; 942 /* Force SPDIF setting */ 943 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0) 944 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, 945 params_rate(hw_params)); 946 } 947 return err; 948 } 949 950 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream) 951 { 952 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 953 struct ichdev *ichdev = get_ichdev(substream); 954 955 if (ichdev->pcm_open_flag) { 956 snd_ac97_pcm_close(ichdev->pcm); 957 ichdev->pcm_open_flag = 0; 958 } 959 if (chip->fix_nocache && ichdev->page_attr_changed) { 960 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0); 961 ichdev->page_attr_changed = 0; 962 } 963 return snd_pcm_lib_free_pages(substream); 964 } 965 966 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip, 967 struct snd_pcm_runtime *runtime) 968 { 969 unsigned int cnt; 970 int dbl = runtime->rate > 48000; 971 972 spin_lock_irq(&chip->reg_lock); 973 switch (chip->device_type) { 974 case DEVICE_ALI: 975 cnt = igetdword(chip, ICHREG(ALI_SCR)); 976 cnt &= ~ICH_ALI_SC_PCM_246_MASK; 977 if (runtime->channels == 4 || dbl) 978 cnt |= ICH_ALI_SC_PCM_4; 979 else if (runtime->channels == 6) 980 cnt |= ICH_ALI_SC_PCM_6; 981 iputdword(chip, ICHREG(ALI_SCR), cnt); 982 break; 983 case DEVICE_SIS: 984 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 985 cnt &= ~ICH_SIS_PCM_246_MASK; 986 if (runtime->channels == 4 || dbl) 987 cnt |= ICH_SIS_PCM_4; 988 else if (runtime->channels == 6) 989 cnt |= ICH_SIS_PCM_6; 990 iputdword(chip, ICHREG(GLOB_CNT), cnt); 991 break; 992 default: 993 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 994 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT); 995 if (runtime->channels == 4 || dbl) 996 cnt |= ICH_PCM_4; 997 else if (runtime->channels == 6) 998 cnt |= ICH_PCM_6; 999 if (chip->device_type == DEVICE_NFORCE) { 1000 /* reset to 2ch once to keep the 6 channel data in alignment, 1001 * to start from Front Left always 1002 */ 1003 if (cnt & ICH_PCM_246_MASK) { 1004 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK); 1005 spin_unlock_irq(&chip->reg_lock); 1006 msleep(50); /* grrr... */ 1007 spin_lock_irq(&chip->reg_lock); 1008 } 1009 } else if (chip->device_type == DEVICE_INTEL_ICH4) { 1010 if (runtime->sample_bits > 16) 1011 cnt |= ICH_PCM_20BIT; 1012 } 1013 iputdword(chip, ICHREG(GLOB_CNT), cnt); 1014 break; 1015 } 1016 spin_unlock_irq(&chip->reg_lock); 1017 } 1018 1019 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream) 1020 { 1021 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1022 struct snd_pcm_runtime *runtime = substream->runtime; 1023 struct ichdev *ichdev = get_ichdev(substream); 1024 1025 ichdev->physbuf = runtime->dma_addr; 1026 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 1027 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 1028 if (ichdev->ichd == ICHD_PCMOUT) { 1029 snd_intel8x0_setup_pcm_out(chip, runtime); 1030 if (chip->device_type == DEVICE_INTEL_ICH4) 1031 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1; 1032 } 1033 snd_intel8x0_setup_periods(chip, ichdev); 1034 return 0; 1035 } 1036 1037 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream) 1038 { 1039 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1040 struct ichdev *ichdev = get_ichdev(substream); 1041 size_t ptr1, ptr; 1042 int civ, timeout = 100; 1043 unsigned int position; 1044 1045 spin_lock(&chip->reg_lock); 1046 do { 1047 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 1048 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 1049 position = ichdev->position; 1050 if (ptr1 == 0) { 1051 udelay(10); 1052 continue; 1053 } 1054 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && 1055 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 1056 break; 1057 } while (timeout--); 1058 ptr1 <<= ichdev->pos_shift; 1059 ptr = ichdev->fragsize1 - ptr1; 1060 ptr += position; 1061 spin_unlock(&chip->reg_lock); 1062 if (ptr >= ichdev->size) 1063 return 0; 1064 return bytes_to_frames(substream->runtime, ptr); 1065 } 1066 1067 static struct snd_pcm_hardware snd_intel8x0_stream = 1068 { 1069 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1070 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1071 SNDRV_PCM_INFO_MMAP_VALID | 1072 SNDRV_PCM_INFO_PAUSE | 1073 SNDRV_PCM_INFO_RESUME), 1074 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1075 .rates = SNDRV_PCM_RATE_48000, 1076 .rate_min = 48000, 1077 .rate_max = 48000, 1078 .channels_min = 2, 1079 .channels_max = 2, 1080 .buffer_bytes_max = 128 * 1024, 1081 .period_bytes_min = 32, 1082 .period_bytes_max = 128 * 1024, 1083 .periods_min = 1, 1084 .periods_max = 1024, 1085 .fifo_size = 0, 1086 }; 1087 1088 static unsigned int channels4[] = { 1089 2, 4, 1090 }; 1091 1092 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = { 1093 .count = ARRAY_SIZE(channels4), 1094 .list = channels4, 1095 .mask = 0, 1096 }; 1097 1098 static unsigned int channels6[] = { 1099 2, 4, 6, 1100 }; 1101 1102 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = { 1103 .count = ARRAY_SIZE(channels6), 1104 .list = channels6, 1105 .mask = 0, 1106 }; 1107 1108 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) 1109 { 1110 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1111 struct snd_pcm_runtime *runtime = substream->runtime; 1112 int err; 1113 1114 ichdev->substream = substream; 1115 runtime->hw = snd_intel8x0_stream; 1116 runtime->hw.rates = ichdev->pcm->rates; 1117 snd_pcm_limit_hw_rates(runtime); 1118 if (chip->device_type == DEVICE_SIS) { 1119 runtime->hw.buffer_bytes_max = 64*1024; 1120 runtime->hw.period_bytes_max = 64*1024; 1121 } 1122 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) 1123 return err; 1124 runtime->private_data = ichdev; 1125 return 0; 1126 } 1127 1128 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream) 1129 { 1130 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1131 struct snd_pcm_runtime *runtime = substream->runtime; 1132 int err; 1133 1134 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]); 1135 if (err < 0) 1136 return err; 1137 1138 if (chip->multi6) { 1139 runtime->hw.channels_max = 6; 1140 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1141 &hw_constraints_channels6); 1142 } else if (chip->multi4) { 1143 runtime->hw.channels_max = 4; 1144 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1145 &hw_constraints_channels4); 1146 } 1147 if (chip->dra) { 1148 snd_ac97_pcm_double_rate_rules(runtime); 1149 } 1150 if (chip->smp20bit) { 1151 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1152 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 1153 } 1154 return 0; 1155 } 1156 1157 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream) 1158 { 1159 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1160 1161 chip->ichd[ICHD_PCMOUT].substream = NULL; 1162 return 0; 1163 } 1164 1165 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream) 1166 { 1167 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1168 1169 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]); 1170 } 1171 1172 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream) 1173 { 1174 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1175 1176 chip->ichd[ICHD_PCMIN].substream = NULL; 1177 return 0; 1178 } 1179 1180 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream) 1181 { 1182 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1183 1184 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]); 1185 } 1186 1187 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream) 1188 { 1189 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1190 1191 chip->ichd[ICHD_MIC].substream = NULL; 1192 return 0; 1193 } 1194 1195 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream) 1196 { 1197 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1198 1199 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]); 1200 } 1201 1202 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream) 1203 { 1204 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1205 1206 chip->ichd[ICHD_MIC2].substream = NULL; 1207 return 0; 1208 } 1209 1210 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream) 1211 { 1212 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1213 1214 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]); 1215 } 1216 1217 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream) 1218 { 1219 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1220 1221 chip->ichd[ICHD_PCM2IN].substream = NULL; 1222 return 0; 1223 } 1224 1225 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream) 1226 { 1227 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1228 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1229 1230 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]); 1231 } 1232 1233 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream) 1234 { 1235 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1236 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1237 1238 chip->ichd[idx].substream = NULL; 1239 return 0; 1240 } 1241 1242 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream) 1243 { 1244 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1245 unsigned int val; 1246 1247 spin_lock_irq(&chip->reg_lock); 1248 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1249 val |= ICH_ALI_IF_AC97SP; 1250 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1251 /* also needs to set ALI_SC_CODEC_SPDF correctly */ 1252 spin_unlock_irq(&chip->reg_lock); 1253 1254 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]); 1255 } 1256 1257 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream) 1258 { 1259 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1260 unsigned int val; 1261 1262 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL; 1263 spin_lock_irq(&chip->reg_lock); 1264 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1265 val &= ~ICH_ALI_IF_AC97SP; 1266 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1267 spin_unlock_irq(&chip->reg_lock); 1268 1269 return 0; 1270 } 1271 1272 #if 0 // NYI 1273 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream) 1274 { 1275 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1276 1277 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]); 1278 } 1279 1280 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream) 1281 { 1282 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1283 1284 chip->ichd[ALID_SPDIFIN].substream = NULL; 1285 return 0; 1286 } 1287 1288 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream) 1289 { 1290 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1291 1292 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]); 1293 } 1294 1295 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream) 1296 { 1297 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1298 1299 chip->ichd[ALID_SPDIFOUT].substream = NULL; 1300 return 0; 1301 } 1302 #endif 1303 1304 static struct snd_pcm_ops snd_intel8x0_playback_ops = { 1305 .open = snd_intel8x0_playback_open, 1306 .close = snd_intel8x0_playback_close, 1307 .ioctl = snd_pcm_lib_ioctl, 1308 .hw_params = snd_intel8x0_hw_params, 1309 .hw_free = snd_intel8x0_hw_free, 1310 .prepare = snd_intel8x0_pcm_prepare, 1311 .trigger = snd_intel8x0_pcm_trigger, 1312 .pointer = snd_intel8x0_pcm_pointer, 1313 }; 1314 1315 static struct snd_pcm_ops snd_intel8x0_capture_ops = { 1316 .open = snd_intel8x0_capture_open, 1317 .close = snd_intel8x0_capture_close, 1318 .ioctl = snd_pcm_lib_ioctl, 1319 .hw_params = snd_intel8x0_hw_params, 1320 .hw_free = snd_intel8x0_hw_free, 1321 .prepare = snd_intel8x0_pcm_prepare, 1322 .trigger = snd_intel8x0_pcm_trigger, 1323 .pointer = snd_intel8x0_pcm_pointer, 1324 }; 1325 1326 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = { 1327 .open = snd_intel8x0_mic_open, 1328 .close = snd_intel8x0_mic_close, 1329 .ioctl = snd_pcm_lib_ioctl, 1330 .hw_params = snd_intel8x0_hw_params, 1331 .hw_free = snd_intel8x0_hw_free, 1332 .prepare = snd_intel8x0_pcm_prepare, 1333 .trigger = snd_intel8x0_pcm_trigger, 1334 .pointer = snd_intel8x0_pcm_pointer, 1335 }; 1336 1337 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = { 1338 .open = snd_intel8x0_mic2_open, 1339 .close = snd_intel8x0_mic2_close, 1340 .ioctl = snd_pcm_lib_ioctl, 1341 .hw_params = snd_intel8x0_hw_params, 1342 .hw_free = snd_intel8x0_hw_free, 1343 .prepare = snd_intel8x0_pcm_prepare, 1344 .trigger = snd_intel8x0_pcm_trigger, 1345 .pointer = snd_intel8x0_pcm_pointer, 1346 }; 1347 1348 static struct snd_pcm_ops snd_intel8x0_capture2_ops = { 1349 .open = snd_intel8x0_capture2_open, 1350 .close = snd_intel8x0_capture2_close, 1351 .ioctl = snd_pcm_lib_ioctl, 1352 .hw_params = snd_intel8x0_hw_params, 1353 .hw_free = snd_intel8x0_hw_free, 1354 .prepare = snd_intel8x0_pcm_prepare, 1355 .trigger = snd_intel8x0_pcm_trigger, 1356 .pointer = snd_intel8x0_pcm_pointer, 1357 }; 1358 1359 static struct snd_pcm_ops snd_intel8x0_spdif_ops = { 1360 .open = snd_intel8x0_spdif_open, 1361 .close = snd_intel8x0_spdif_close, 1362 .ioctl = snd_pcm_lib_ioctl, 1363 .hw_params = snd_intel8x0_hw_params, 1364 .hw_free = snd_intel8x0_hw_free, 1365 .prepare = snd_intel8x0_pcm_prepare, 1366 .trigger = snd_intel8x0_pcm_trigger, 1367 .pointer = snd_intel8x0_pcm_pointer, 1368 }; 1369 1370 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = { 1371 .open = snd_intel8x0_playback_open, 1372 .close = snd_intel8x0_playback_close, 1373 .ioctl = snd_pcm_lib_ioctl, 1374 .hw_params = snd_intel8x0_hw_params, 1375 .hw_free = snd_intel8x0_hw_free, 1376 .prepare = snd_intel8x0_pcm_prepare, 1377 .trigger = snd_intel8x0_ali_trigger, 1378 .pointer = snd_intel8x0_pcm_pointer, 1379 }; 1380 1381 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = { 1382 .open = snd_intel8x0_capture_open, 1383 .close = snd_intel8x0_capture_close, 1384 .ioctl = snd_pcm_lib_ioctl, 1385 .hw_params = snd_intel8x0_hw_params, 1386 .hw_free = snd_intel8x0_hw_free, 1387 .prepare = snd_intel8x0_pcm_prepare, 1388 .trigger = snd_intel8x0_ali_trigger, 1389 .pointer = snd_intel8x0_pcm_pointer, 1390 }; 1391 1392 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = { 1393 .open = snd_intel8x0_mic_open, 1394 .close = snd_intel8x0_mic_close, 1395 .ioctl = snd_pcm_lib_ioctl, 1396 .hw_params = snd_intel8x0_hw_params, 1397 .hw_free = snd_intel8x0_hw_free, 1398 .prepare = snd_intel8x0_pcm_prepare, 1399 .trigger = snd_intel8x0_ali_trigger, 1400 .pointer = snd_intel8x0_pcm_pointer, 1401 }; 1402 1403 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = { 1404 .open = snd_intel8x0_ali_ac97spdifout_open, 1405 .close = snd_intel8x0_ali_ac97spdifout_close, 1406 .ioctl = snd_pcm_lib_ioctl, 1407 .hw_params = snd_intel8x0_hw_params, 1408 .hw_free = snd_intel8x0_hw_free, 1409 .prepare = snd_intel8x0_pcm_prepare, 1410 .trigger = snd_intel8x0_ali_trigger, 1411 .pointer = snd_intel8x0_pcm_pointer, 1412 }; 1413 1414 #if 0 // NYI 1415 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = { 1416 .open = snd_intel8x0_ali_spdifin_open, 1417 .close = snd_intel8x0_ali_spdifin_close, 1418 .ioctl = snd_pcm_lib_ioctl, 1419 .hw_params = snd_intel8x0_hw_params, 1420 .hw_free = snd_intel8x0_hw_free, 1421 .prepare = snd_intel8x0_pcm_prepare, 1422 .trigger = snd_intel8x0_pcm_trigger, 1423 .pointer = snd_intel8x0_pcm_pointer, 1424 }; 1425 1426 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = { 1427 .open = snd_intel8x0_ali_spdifout_open, 1428 .close = snd_intel8x0_ali_spdifout_close, 1429 .ioctl = snd_pcm_lib_ioctl, 1430 .hw_params = snd_intel8x0_hw_params, 1431 .hw_free = snd_intel8x0_hw_free, 1432 .prepare = snd_intel8x0_pcm_prepare, 1433 .trigger = snd_intel8x0_pcm_trigger, 1434 .pointer = snd_intel8x0_pcm_pointer, 1435 }; 1436 #endif // NYI 1437 1438 struct ich_pcm_table { 1439 char *suffix; 1440 struct snd_pcm_ops *playback_ops; 1441 struct snd_pcm_ops *capture_ops; 1442 size_t prealloc_size; 1443 size_t prealloc_max_size; 1444 int ac97_idx; 1445 }; 1446 1447 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device, 1448 struct ich_pcm_table *rec) 1449 { 1450 struct snd_pcm *pcm; 1451 int err; 1452 char name[32]; 1453 1454 if (rec->suffix) 1455 sprintf(name, "Intel ICH - %s", rec->suffix); 1456 else 1457 strcpy(name, "Intel ICH"); 1458 err = snd_pcm_new(chip->card, name, device, 1459 rec->playback_ops ? 1 : 0, 1460 rec->capture_ops ? 1 : 0, &pcm); 1461 if (err < 0) 1462 return err; 1463 1464 if (rec->playback_ops) 1465 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 1466 if (rec->capture_ops) 1467 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 1468 1469 pcm->private_data = chip; 1470 pcm->info_flags = 0; 1471 if (rec->suffix) 1472 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 1473 else 1474 strcpy(pcm->name, chip->card->shortname); 1475 chip->pcm[device] = pcm; 1476 1477 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1478 snd_dma_pci_data(chip->pci), 1479 rec->prealloc_size, rec->prealloc_max_size); 1480 1481 return 0; 1482 } 1483 1484 static struct ich_pcm_table intel_pcms[] __devinitdata = { 1485 { 1486 .playback_ops = &snd_intel8x0_playback_ops, 1487 .capture_ops = &snd_intel8x0_capture_ops, 1488 .prealloc_size = 64 * 1024, 1489 .prealloc_max_size = 128 * 1024, 1490 }, 1491 { 1492 .suffix = "MIC ADC", 1493 .capture_ops = &snd_intel8x0_capture_mic_ops, 1494 .prealloc_size = 0, 1495 .prealloc_max_size = 128 * 1024, 1496 .ac97_idx = ICHD_MIC, 1497 }, 1498 { 1499 .suffix = "MIC2 ADC", 1500 .capture_ops = &snd_intel8x0_capture_mic2_ops, 1501 .prealloc_size = 0, 1502 .prealloc_max_size = 128 * 1024, 1503 .ac97_idx = ICHD_MIC2, 1504 }, 1505 { 1506 .suffix = "ADC2", 1507 .capture_ops = &snd_intel8x0_capture2_ops, 1508 .prealloc_size = 0, 1509 .prealloc_max_size = 128 * 1024, 1510 .ac97_idx = ICHD_PCM2IN, 1511 }, 1512 { 1513 .suffix = "IEC958", 1514 .playback_ops = &snd_intel8x0_spdif_ops, 1515 .prealloc_size = 64 * 1024, 1516 .prealloc_max_size = 128 * 1024, 1517 .ac97_idx = ICHD_SPBAR, 1518 }, 1519 }; 1520 1521 static struct ich_pcm_table nforce_pcms[] __devinitdata = { 1522 { 1523 .playback_ops = &snd_intel8x0_playback_ops, 1524 .capture_ops = &snd_intel8x0_capture_ops, 1525 .prealloc_size = 64 * 1024, 1526 .prealloc_max_size = 128 * 1024, 1527 }, 1528 { 1529 .suffix = "MIC ADC", 1530 .capture_ops = &snd_intel8x0_capture_mic_ops, 1531 .prealloc_size = 0, 1532 .prealloc_max_size = 128 * 1024, 1533 .ac97_idx = NVD_MIC, 1534 }, 1535 { 1536 .suffix = "IEC958", 1537 .playback_ops = &snd_intel8x0_spdif_ops, 1538 .prealloc_size = 64 * 1024, 1539 .prealloc_max_size = 128 * 1024, 1540 .ac97_idx = NVD_SPBAR, 1541 }, 1542 }; 1543 1544 static struct ich_pcm_table ali_pcms[] __devinitdata = { 1545 { 1546 .playback_ops = &snd_intel8x0_ali_playback_ops, 1547 .capture_ops = &snd_intel8x0_ali_capture_ops, 1548 .prealloc_size = 64 * 1024, 1549 .prealloc_max_size = 128 * 1024, 1550 }, 1551 { 1552 .suffix = "MIC ADC", 1553 .capture_ops = &snd_intel8x0_ali_capture_mic_ops, 1554 .prealloc_size = 0, 1555 .prealloc_max_size = 128 * 1024, 1556 .ac97_idx = ALID_MIC, 1557 }, 1558 { 1559 .suffix = "IEC958", 1560 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops, 1561 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */ 1562 .prealloc_size = 64 * 1024, 1563 .prealloc_max_size = 128 * 1024, 1564 .ac97_idx = ALID_AC97SPDIFOUT, 1565 }, 1566 #if 0 // NYI 1567 { 1568 .suffix = "HW IEC958", 1569 .playback_ops = &snd_intel8x0_ali_spdifout_ops, 1570 .prealloc_size = 64 * 1024, 1571 .prealloc_max_size = 128 * 1024, 1572 }, 1573 #endif 1574 }; 1575 1576 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip) 1577 { 1578 int i, tblsize, device, err; 1579 struct ich_pcm_table *tbl, *rec; 1580 1581 switch (chip->device_type) { 1582 case DEVICE_INTEL_ICH4: 1583 tbl = intel_pcms; 1584 tblsize = ARRAY_SIZE(intel_pcms); 1585 if (spdif_aclink) 1586 tblsize--; 1587 break; 1588 case DEVICE_NFORCE: 1589 tbl = nforce_pcms; 1590 tblsize = ARRAY_SIZE(nforce_pcms); 1591 if (spdif_aclink) 1592 tblsize--; 1593 break; 1594 case DEVICE_ALI: 1595 tbl = ali_pcms; 1596 tblsize = ARRAY_SIZE(ali_pcms); 1597 break; 1598 default: 1599 tbl = intel_pcms; 1600 tblsize = 2; 1601 break; 1602 } 1603 1604 device = 0; 1605 for (i = 0; i < tblsize; i++) { 1606 rec = tbl + i; 1607 if (i > 0 && rec->ac97_idx) { 1608 /* activate PCM only when associated AC'97 codec */ 1609 if (! chip->ichd[rec->ac97_idx].pcm) 1610 continue; 1611 } 1612 err = snd_intel8x0_pcm1(chip, device, rec); 1613 if (err < 0) 1614 return err; 1615 device++; 1616 } 1617 1618 chip->pcm_devs = device; 1619 return 0; 1620 } 1621 1622 1623 /* 1624 * Mixer part 1625 */ 1626 1627 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1628 { 1629 struct intel8x0 *chip = bus->private_data; 1630 chip->ac97_bus = NULL; 1631 } 1632 1633 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97) 1634 { 1635 struct intel8x0 *chip = ac97->private_data; 1636 chip->ac97[ac97->num] = NULL; 1637 } 1638 1639 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = { 1640 /* front PCM */ 1641 { 1642 .exclusive = 1, 1643 .r = { { 1644 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1645 (1 << AC97_SLOT_PCM_RIGHT) | 1646 (1 << AC97_SLOT_PCM_CENTER) | 1647 (1 << AC97_SLOT_PCM_SLEFT) | 1648 (1 << AC97_SLOT_PCM_SRIGHT) | 1649 (1 << AC97_SLOT_LFE) 1650 }, 1651 { 1652 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1653 (1 << AC97_SLOT_PCM_RIGHT) | 1654 (1 << AC97_SLOT_PCM_LEFT_0) | 1655 (1 << AC97_SLOT_PCM_RIGHT_0) 1656 } 1657 } 1658 }, 1659 /* PCM IN #1 */ 1660 { 1661 .stream = 1, 1662 .exclusive = 1, 1663 .r = { { 1664 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1665 (1 << AC97_SLOT_PCM_RIGHT) 1666 } 1667 } 1668 }, 1669 /* MIC IN #1 */ 1670 { 1671 .stream = 1, 1672 .exclusive = 1, 1673 .r = { { 1674 .slots = (1 << AC97_SLOT_MIC) 1675 } 1676 } 1677 }, 1678 /* S/PDIF PCM */ 1679 { 1680 .exclusive = 1, 1681 .spdif = 1, 1682 .r = { { 1683 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1684 (1 << AC97_SLOT_SPDIF_RIGHT2) 1685 } 1686 } 1687 }, 1688 /* PCM IN #2 */ 1689 { 1690 .stream = 1, 1691 .exclusive = 1, 1692 .r = { { 1693 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1694 (1 << AC97_SLOT_PCM_RIGHT) 1695 } 1696 } 1697 }, 1698 /* MIC IN #2 */ 1699 { 1700 .stream = 1, 1701 .exclusive = 1, 1702 .r = { { 1703 .slots = (1 << AC97_SLOT_MIC) 1704 } 1705 } 1706 }, 1707 }; 1708 1709 static struct ac97_quirk ac97_quirks[] __devinitdata = { 1710 { 1711 .subvendor = 0x0e11, 1712 .subdevice = 0x008a, 1713 .name = "Compaq Evo W4000", /* AD1885 */ 1714 .type = AC97_TUNE_HP_ONLY 1715 }, 1716 { 1717 .subvendor = 0x0e11, 1718 .subdevice = 0x00b8, 1719 .name = "Compaq Evo D510C", 1720 .type = AC97_TUNE_HP_ONLY 1721 }, 1722 { 1723 .subvendor = 0x0e11, 1724 .subdevice = 0x0860, 1725 .name = "HP/Compaq nx7010", 1726 .type = AC97_TUNE_MUTE_LED 1727 }, 1728 { 1729 .subvendor = 0x1014, 1730 .subdevice = 0x1f00, 1731 .name = "MS-9128", 1732 .type = AC97_TUNE_ALC_JACK 1733 }, 1734 { 1735 .subvendor = 0x1014, 1736 .subdevice = 0x0267, 1737 .name = "IBM NetVista A30p", /* AD1981B */ 1738 .type = AC97_TUNE_HP_ONLY 1739 }, 1740 { 1741 .subvendor = 0x1025, 1742 .subdevice = 0x0083, 1743 .name = "Acer Aspire 3003LCi", 1744 .type = AC97_TUNE_HP_ONLY 1745 }, 1746 { 1747 .subvendor = 0x1028, 1748 .subdevice = 0x00d8, 1749 .name = "Dell Precision 530", /* AD1885 */ 1750 .type = AC97_TUNE_HP_ONLY 1751 }, 1752 { 1753 .subvendor = 0x1028, 1754 .subdevice = 0x010d, 1755 .name = "Dell", /* which model? AD1885 */ 1756 .type = AC97_TUNE_HP_ONLY 1757 }, 1758 { 1759 .subvendor = 0x1028, 1760 .subdevice = 0x0126, 1761 .name = "Dell Optiplex GX260", /* AD1981A */ 1762 .type = AC97_TUNE_HP_ONLY 1763 }, 1764 { 1765 .subvendor = 0x1028, 1766 .subdevice = 0x012c, 1767 .name = "Dell Precision 650", /* AD1981A */ 1768 .type = AC97_TUNE_HP_ONLY 1769 }, 1770 { 1771 .subvendor = 0x1028, 1772 .subdevice = 0x012d, 1773 .name = "Dell Precision 450", /* AD1981B*/ 1774 .type = AC97_TUNE_HP_ONLY 1775 }, 1776 { 1777 .subvendor = 0x1028, 1778 .subdevice = 0x0147, 1779 .name = "Dell", /* which model? AD1981B*/ 1780 .type = AC97_TUNE_HP_ONLY 1781 }, 1782 { 1783 .subvendor = 0x1028, 1784 .subdevice = 0x0151, 1785 .name = "Dell Optiplex GX270", /* AD1981B */ 1786 .type = AC97_TUNE_HP_ONLY 1787 }, 1788 { 1789 .subvendor = 0x1028, 1790 .subdevice = 0x014e, 1791 .name = "Dell D800", /* STAC9750/51 */ 1792 .type = AC97_TUNE_HP_ONLY 1793 }, 1794 { 1795 .subvendor = 0x1028, 1796 .subdevice = 0x0163, 1797 .name = "Dell Unknown", /* STAC9750/51 */ 1798 .type = AC97_TUNE_HP_ONLY 1799 }, 1800 { 1801 .subvendor = 0x1028, 1802 .subdevice = 0x0191, 1803 .name = "Dell Inspiron 8600", 1804 .type = AC97_TUNE_HP_ONLY 1805 }, 1806 { 1807 .subvendor = 0x103c, 1808 .subdevice = 0x006d, 1809 .name = "HP zv5000", 1810 .type = AC97_TUNE_MUTE_LED /*AD1981B*/ 1811 }, 1812 { /* FIXME: which codec? */ 1813 .subvendor = 0x103c, 1814 .subdevice = 0x00c3, 1815 .name = "HP xw6000", 1816 .type = AC97_TUNE_HP_ONLY 1817 }, 1818 { 1819 .subvendor = 0x103c, 1820 .subdevice = 0x088c, 1821 .name = "HP nc8000", 1822 .type = AC97_TUNE_MUTE_LED 1823 }, 1824 { 1825 .subvendor = 0x103c, 1826 .subdevice = 0x0890, 1827 .name = "HP nc6000", 1828 .type = AC97_TUNE_MUTE_LED 1829 }, 1830 { 1831 .subvendor = 0x103c, 1832 .subdevice = 0x0934, 1833 .name = "HP nx8220", 1834 .type = AC97_TUNE_MUTE_LED 1835 }, 1836 { 1837 .subvendor = 0x103c, 1838 .subdevice = 0x129d, 1839 .name = "HP xw8000", 1840 .type = AC97_TUNE_HP_ONLY 1841 }, 1842 { 1843 .subvendor = 0x103c, 1844 .subdevice = 0x0938, 1845 .name = "HP nc4200", 1846 .type = AC97_TUNE_HP_MUTE_LED 1847 }, 1848 { 1849 .subvendor = 0x103c, 1850 .subdevice = 0x099c, 1851 .name = "HP nx6110/nc6120", 1852 .type = AC97_TUNE_HP_MUTE_LED 1853 }, 1854 { 1855 .subvendor = 0x103c, 1856 .subdevice = 0x0944, 1857 .name = "HP nc6220", 1858 .type = AC97_TUNE_HP_MUTE_LED 1859 }, 1860 { 1861 .subvendor = 0x103c, 1862 .subdevice = 0x0934, 1863 .name = "HP nc8220", 1864 .type = AC97_TUNE_HP_MUTE_LED 1865 }, 1866 { 1867 .subvendor = 0x103c, 1868 .subdevice = 0x12f1, 1869 .name = "HP xw8200", /* AD1981B*/ 1870 .type = AC97_TUNE_HP_ONLY 1871 }, 1872 { 1873 .subvendor = 0x103c, 1874 .subdevice = 0x12f2, 1875 .name = "HP xw6200", 1876 .type = AC97_TUNE_HP_ONLY 1877 }, 1878 { 1879 .subvendor = 0x103c, 1880 .subdevice = 0x3008, 1881 .name = "HP xw4200", /* AD1981B*/ 1882 .type = AC97_TUNE_HP_ONLY 1883 }, 1884 { 1885 .subvendor = 0x104d, 1886 .subdevice = 0x8197, 1887 .name = "Sony S1XP", 1888 .type = AC97_TUNE_INV_EAPD 1889 }, 1890 { 1891 .subvendor = 0x1043, 1892 .subdevice = 0x80f3, 1893 .name = "ASUS ICH5/AD1985", 1894 .type = AC97_TUNE_AD_SHARING 1895 }, 1896 { 1897 .subvendor = 0x10cf, 1898 .subdevice = 0x11c3, 1899 .name = "Fujitsu-Siemens E4010", 1900 .type = AC97_TUNE_HP_ONLY 1901 }, 1902 { 1903 .subvendor = 0x10cf, 1904 .subdevice = 0x1225, 1905 .name = "Fujitsu-Siemens T3010", 1906 .type = AC97_TUNE_HP_ONLY 1907 }, 1908 { 1909 .subvendor = 0x10cf, 1910 .subdevice = 0x1253, 1911 .name = "Fujitsu S6210", /* STAC9750/51 */ 1912 .type = AC97_TUNE_HP_ONLY 1913 }, 1914 { 1915 .subvendor = 0x10cf, 1916 .subdevice = 0x12ec, 1917 .name = "Fujitsu-Siemens 4010", 1918 .type = AC97_TUNE_HP_ONLY 1919 }, 1920 { 1921 .subvendor = 0x10cf, 1922 .subdevice = 0x12f2, 1923 .name = "Fujitsu-Siemens Celsius H320", 1924 .type = AC97_TUNE_SWAP_HP 1925 }, 1926 { 1927 .subvendor = 0x10f1, 1928 .subdevice = 0x2665, 1929 .name = "Fujitsu-Siemens Celsius", /* AD1981? */ 1930 .type = AC97_TUNE_HP_ONLY 1931 }, 1932 { 1933 .subvendor = 0x10f1, 1934 .subdevice = 0x2885, 1935 .name = "AMD64 Mobo", /* ALC650 */ 1936 .type = AC97_TUNE_HP_ONLY 1937 }, 1938 { 1939 .subvendor = 0x10f1, 1940 .subdevice = 0x2895, 1941 .name = "Tyan Thunder K8WE", 1942 .type = AC97_TUNE_HP_ONLY 1943 }, 1944 { 1945 .subvendor = 0x10f7, 1946 .subdevice = 0x834c, 1947 .name = "Panasonic CF-R4", 1948 .type = AC97_TUNE_HP_ONLY, 1949 }, 1950 { 1951 .subvendor = 0x110a, 1952 .subdevice = 0x0056, 1953 .name = "Fujitsu-Siemens Scenic", /* AD1981? */ 1954 .type = AC97_TUNE_HP_ONLY 1955 }, 1956 { 1957 .subvendor = 0x11d4, 1958 .subdevice = 0x5375, 1959 .name = "ADI AD1985 (discrete)", 1960 .type = AC97_TUNE_HP_ONLY 1961 }, 1962 { 1963 .subvendor = 0x1462, 1964 .subdevice = 0x5470, 1965 .name = "MSI P4 ATX 645 Ultra", 1966 .type = AC97_TUNE_HP_ONLY 1967 }, 1968 { 1969 .subvendor = 0x1734, 1970 .subdevice = 0x0088, 1971 .name = "Fujitsu-Siemens D1522", /* AD1981 */ 1972 .type = AC97_TUNE_HP_ONLY 1973 }, 1974 { 1975 .subvendor = 0x8086, 1976 .subdevice = 0x2000, 1977 .mask = 0xfff0, 1978 .name = "Intel ICH5/AD1985", 1979 .type = AC97_TUNE_AD_SHARING 1980 }, 1981 { 1982 .subvendor = 0x8086, 1983 .subdevice = 0x4000, 1984 .mask = 0xfff0, 1985 .name = "Intel ICH5/AD1985", 1986 .type = AC97_TUNE_AD_SHARING 1987 }, 1988 { 1989 .subvendor = 0x8086, 1990 .subdevice = 0x4856, 1991 .name = "Intel D845WN (82801BA)", 1992 .type = AC97_TUNE_SWAP_HP 1993 }, 1994 { 1995 .subvendor = 0x8086, 1996 .subdevice = 0x4d44, 1997 .name = "Intel D850EMV2", /* AD1885 */ 1998 .type = AC97_TUNE_HP_ONLY 1999 }, 2000 { 2001 .subvendor = 0x8086, 2002 .subdevice = 0x4d56, 2003 .name = "Intel ICH/AD1885", 2004 .type = AC97_TUNE_HP_ONLY 2005 }, 2006 { 2007 .subvendor = 0x8086, 2008 .subdevice = 0x6000, 2009 .mask = 0xfff0, 2010 .name = "Intel ICH5/AD1985", 2011 .type = AC97_TUNE_AD_SHARING 2012 }, 2013 { 2014 .subvendor = 0x8086, 2015 .subdevice = 0xe000, 2016 .mask = 0xfff0, 2017 .name = "Intel ICH5/AD1985", 2018 .type = AC97_TUNE_AD_SHARING 2019 }, 2020 #if 0 /* FIXME: this seems wrong on most boards */ 2021 { 2022 .subvendor = 0x8086, 2023 .subdevice = 0xa000, 2024 .mask = 0xfff0, 2025 .name = "Intel ICH5/AD1985", 2026 .type = AC97_TUNE_HP_ONLY 2027 }, 2028 #endif 2029 { } /* terminator */ 2030 }; 2031 2032 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock, 2033 const char *quirk_override) 2034 { 2035 struct snd_ac97_bus *pbus; 2036 struct snd_ac97_template ac97; 2037 int err; 2038 unsigned int i, codecs; 2039 unsigned int glob_sta = 0; 2040 struct snd_ac97_bus_ops *ops; 2041 static struct snd_ac97_bus_ops standard_bus_ops = { 2042 .write = snd_intel8x0_codec_write, 2043 .read = snd_intel8x0_codec_read, 2044 }; 2045 static struct snd_ac97_bus_ops ali_bus_ops = { 2046 .write = snd_intel8x0_ali_codec_write, 2047 .read = snd_intel8x0_ali_codec_read, 2048 }; 2049 2050 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */ 2051 if (!spdif_aclink) { 2052 switch (chip->device_type) { 2053 case DEVICE_NFORCE: 2054 chip->spdif_idx = NVD_SPBAR; 2055 break; 2056 case DEVICE_ALI: 2057 chip->spdif_idx = ALID_AC97SPDIFOUT; 2058 break; 2059 case DEVICE_INTEL_ICH4: 2060 chip->spdif_idx = ICHD_SPBAR; 2061 break; 2062 }; 2063 } 2064 2065 chip->in_ac97_init = 1; 2066 2067 memset(&ac97, 0, sizeof(ac97)); 2068 ac97.private_data = chip; 2069 ac97.private_free = snd_intel8x0_mixer_free_ac97; 2070 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; 2071 if (chip->xbox) 2072 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR; 2073 if (chip->device_type != DEVICE_ALI) { 2074 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 2075 ops = &standard_bus_ops; 2076 chip->in_sdin_init = 1; 2077 codecs = 0; 2078 for (i = 0; i < chip->max_codecs; i++) { 2079 if (! (glob_sta & chip->codec_bit[i])) 2080 continue; 2081 if (chip->device_type == DEVICE_INTEL_ICH4) { 2082 snd_intel8x0_codec_read_test(chip, codecs); 2083 chip->ac97_sdin[codecs] = 2084 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; 2085 snd_assert(chip->ac97_sdin[codecs] < 3, 2086 chip->ac97_sdin[codecs] = 0); 2087 } else 2088 chip->ac97_sdin[codecs] = i; 2089 codecs++; 2090 } 2091 chip->in_sdin_init = 0; 2092 if (! codecs) 2093 codecs = 1; 2094 } else { 2095 ops = &ali_bus_ops; 2096 codecs = 1; 2097 /* detect the secondary codec */ 2098 for (i = 0; i < 100; i++) { 2099 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR)); 2100 if (reg & 0x40) { 2101 codecs = 2; 2102 break; 2103 } 2104 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40); 2105 udelay(1); 2106 } 2107 } 2108 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0) 2109 goto __err; 2110 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 2111 if (ac97_clock >= 8000 && ac97_clock <= 48000) 2112 pbus->clock = ac97_clock; 2113 /* FIXME: my test board doesn't work well with VRA... */ 2114 if (chip->device_type == DEVICE_ALI) 2115 pbus->no_vra = 1; 2116 else 2117 pbus->dra = 1; 2118 chip->ac97_bus = pbus; 2119 chip->ncodecs = codecs; 2120 2121 ac97.pci = chip->pci; 2122 for (i = 0; i < codecs; i++) { 2123 ac97.num = i; 2124 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { 2125 if (err != -EACCES) 2126 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i); 2127 if (i == 0) 2128 goto __err; 2129 continue; 2130 } 2131 } 2132 /* tune up the primary codec */ 2133 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 2134 /* enable separate SDINs for ICH4 */ 2135 if (chip->device_type == DEVICE_INTEL_ICH4) 2136 pbus->isdin = 1; 2137 /* find the available PCM streams */ 2138 i = ARRAY_SIZE(ac97_pcm_defs); 2139 if (chip->device_type != DEVICE_INTEL_ICH4) 2140 i -= 2; /* do not allocate PCM2IN and MIC2 */ 2141 if (chip->spdif_idx < 0) 2142 i--; /* do not allocate S/PDIF */ 2143 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs); 2144 if (err < 0) 2145 goto __err; 2146 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0]; 2147 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1]; 2148 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2]; 2149 if (chip->spdif_idx >= 0) 2150 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3]; 2151 if (chip->device_type == DEVICE_INTEL_ICH4) { 2152 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4]; 2153 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5]; 2154 } 2155 /* enable separate SDINs for ICH4 */ 2156 if (chip->device_type == DEVICE_INTEL_ICH4) { 2157 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm; 2158 u8 tmp = igetbyte(chip, ICHREG(SDM)); 2159 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK); 2160 if (pcm) { 2161 tmp |= ICH_SE; /* steer enable for multiple SDINs */ 2162 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT; 2163 for (i = 1; i < 4; i++) { 2164 if (pcm->r[0].codec[i]) { 2165 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT; 2166 break; 2167 } 2168 } 2169 } else { 2170 tmp &= ~ICH_SE; /* steer disable */ 2171 } 2172 iputbyte(chip, ICHREG(SDM), tmp); 2173 } 2174 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 2175 chip->multi4 = 1; 2176 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) 2177 chip->multi6 = 1; 2178 } 2179 if (pbus->pcms[0].r[1].rslots[0]) { 2180 chip->dra = 1; 2181 } 2182 if (chip->device_type == DEVICE_INTEL_ICH4) { 2183 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20) 2184 chip->smp20bit = 1; 2185 } 2186 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2187 /* 48kHz only */ 2188 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000; 2189 } 2190 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2191 /* use slot 10/11 for SPDIF */ 2192 u32 val; 2193 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK; 2194 val |= ICH_PCM_SPDIF_1011; 2195 iputdword(chip, ICHREG(GLOB_CNT), val); 2196 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); 2197 } 2198 chip->in_ac97_init = 0; 2199 return 0; 2200 2201 __err: 2202 /* clear the cold-reset bit for the next chance */ 2203 if (chip->device_type != DEVICE_ALI) 2204 iputdword(chip, ICHREG(GLOB_CNT), 2205 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 2206 return err; 2207 } 2208 2209 2210 /* 2211 * 2212 */ 2213 2214 static void do_ali_reset(struct intel8x0 *chip) 2215 { 2216 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET); 2217 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383); 2218 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383); 2219 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383); 2220 iputdword(chip, ICHREG(ALI_INTERFACECR), 2221 ICH_ALI_IF_PI|ICH_ALI_IF_PO); 2222 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000); 2223 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000); 2224 } 2225 2226 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing) 2227 { 2228 unsigned long end_time; 2229 unsigned int cnt, status, nstatus; 2230 2231 /* put logic to right state */ 2232 /* first clear status bits */ 2233 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT; 2234 if (chip->device_type == DEVICE_NFORCE) 2235 status |= ICH_NVSPINT; 2236 cnt = igetdword(chip, ICHREG(GLOB_STA)); 2237 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 2238 2239 /* ACLink on, 2 channels */ 2240 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2241 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2242 #ifdef CONFIG_SND_AC97_POWER_SAVE 2243 /* do cold reset - the full ac97 powerdown may leave the controller 2244 * in a warm state but actually it cannot communicate with the codec. 2245 */ 2246 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD); 2247 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2248 udelay(10); 2249 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD); 2250 msleep(1); 2251 #else 2252 /* finish cold or do warm reset */ 2253 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 2254 iputdword(chip, ICHREG(GLOB_CNT), cnt); 2255 end_time = (jiffies + (HZ / 4)) + 1; 2256 do { 2257 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 2258 goto __ok; 2259 schedule_timeout_uninterruptible(1); 2260 } while (time_after_eq(end_time, jiffies)); 2261 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n", 2262 igetdword(chip, ICHREG(GLOB_CNT))); 2263 return -EIO; 2264 2265 __ok: 2266 #endif 2267 if (probing) { 2268 /* wait for any codec ready status. 2269 * Once it becomes ready it should remain ready 2270 * as long as we do not disable the ac97 link. 2271 */ 2272 end_time = jiffies + HZ; 2273 do { 2274 status = igetdword(chip, ICHREG(GLOB_STA)) & 2275 chip->codec_isr_bits; 2276 if (status) 2277 break; 2278 schedule_timeout_uninterruptible(1); 2279 } while (time_after_eq(end_time, jiffies)); 2280 if (! status) { 2281 /* no codec is found */ 2282 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", 2283 igetdword(chip, ICHREG(GLOB_STA))); 2284 return -EIO; 2285 } 2286 2287 /* wait for other codecs ready status. */ 2288 end_time = jiffies + HZ / 4; 2289 while (status != chip->codec_isr_bits && 2290 time_after_eq(end_time, jiffies)) { 2291 schedule_timeout_uninterruptible(1); 2292 status |= igetdword(chip, ICHREG(GLOB_STA)) & 2293 chip->codec_isr_bits; 2294 } 2295 2296 } else { 2297 /* resume phase */ 2298 int i; 2299 status = 0; 2300 for (i = 0; i < chip->ncodecs; i++) 2301 if (chip->ac97[i]) 2302 status |= chip->codec_bit[chip->ac97_sdin[i]]; 2303 /* wait until all the probed codecs are ready */ 2304 end_time = jiffies + HZ; 2305 do { 2306 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & 2307 chip->codec_isr_bits; 2308 if (status == nstatus) 2309 break; 2310 schedule_timeout_uninterruptible(1); 2311 } while (time_after_eq(end_time, jiffies)); 2312 } 2313 2314 if (chip->device_type == DEVICE_SIS) { 2315 /* unmute the output on SIS7012 */ 2316 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 2317 } 2318 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2319 /* enable SPDIF interrupt */ 2320 unsigned int val; 2321 pci_read_config_dword(chip->pci, 0x4c, &val); 2322 val |= 0x1000000; 2323 pci_write_config_dword(chip->pci, 0x4c, val); 2324 } 2325 return 0; 2326 } 2327 2328 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing) 2329 { 2330 u32 reg; 2331 int i = 0; 2332 2333 reg = igetdword(chip, ICHREG(ALI_SCR)); 2334 if ((reg & 2) == 0) /* Cold required */ 2335 reg |= 2; 2336 else 2337 reg |= 1; /* Warm */ 2338 reg &= ~0x80000000; /* ACLink on */ 2339 iputdword(chip, ICHREG(ALI_SCR), reg); 2340 2341 for (i = 0; i < HZ / 2; i++) { 2342 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO)) 2343 goto __ok; 2344 schedule_timeout_uninterruptible(1); 2345 } 2346 snd_printk(KERN_ERR "AC'97 reset failed.\n"); 2347 if (probing) 2348 return -EIO; 2349 2350 __ok: 2351 for (i = 0; i < HZ / 2; i++) { 2352 reg = igetdword(chip, ICHREG(ALI_RTSR)); 2353 if (reg & 0x80) /* primary codec */ 2354 break; 2355 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80); 2356 schedule_timeout_uninterruptible(1); 2357 } 2358 2359 do_ali_reset(chip); 2360 return 0; 2361 } 2362 2363 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing) 2364 { 2365 unsigned int i, timeout; 2366 int err; 2367 2368 if (chip->device_type != DEVICE_ALI) { 2369 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0) 2370 return err; 2371 iagetword(chip, 0); /* clear semaphore flag */ 2372 } else { 2373 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0) 2374 return err; 2375 } 2376 2377 /* disable interrupts */ 2378 for (i = 0; i < chip->bdbars_count; i++) 2379 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2380 /* reset channels */ 2381 for (i = 0; i < chip->bdbars_count; i++) 2382 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2383 for (i = 0; i < chip->bdbars_count; i++) { 2384 timeout = 100000; 2385 while (--timeout != 0) { 2386 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0) 2387 break; 2388 } 2389 if (timeout == 0) 2390 printk(KERN_ERR "intel8x0: reset of registers failed?\n"); 2391 } 2392 /* initialize Buffer Descriptor Lists */ 2393 for (i = 0; i < chip->bdbars_count; i++) 2394 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, 2395 chip->ichd[i].bdbar_addr); 2396 return 0; 2397 } 2398 2399 static int snd_intel8x0_free(struct intel8x0 *chip) 2400 { 2401 unsigned int i; 2402 2403 if (chip->irq < 0) 2404 goto __hw_end; 2405 /* disable interrupts */ 2406 for (i = 0; i < chip->bdbars_count; i++) 2407 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2408 /* reset channels */ 2409 for (i = 0; i < chip->bdbars_count; i++) 2410 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2411 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2412 /* stop the spdif interrupt */ 2413 unsigned int val; 2414 pci_read_config_dword(chip->pci, 0x4c, &val); 2415 val &= ~0x1000000; 2416 pci_write_config_dword(chip->pci, 0x4c, val); 2417 } 2418 /* --- */ 2419 synchronize_irq(chip->irq); 2420 __hw_end: 2421 if (chip->irq >= 0) 2422 free_irq(chip->irq, chip); 2423 if (chip->bdbars.area) { 2424 if (chip->fix_nocache) 2425 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0); 2426 snd_dma_free_pages(&chip->bdbars); 2427 } 2428 if (chip->addr) 2429 pci_iounmap(chip->pci, chip->addr); 2430 if (chip->bmaddr) 2431 pci_iounmap(chip->pci, chip->bmaddr); 2432 pci_release_regions(chip->pci); 2433 pci_disable_device(chip->pci); 2434 kfree(chip); 2435 return 0; 2436 } 2437 2438 #ifdef CONFIG_PM 2439 /* 2440 * power management 2441 */ 2442 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state) 2443 { 2444 struct snd_card *card = pci_get_drvdata(pci); 2445 struct intel8x0 *chip = card->private_data; 2446 int i; 2447 2448 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2449 for (i = 0; i < chip->pcm_devs; i++) 2450 snd_pcm_suspend_all(chip->pcm[i]); 2451 /* clear nocache */ 2452 if (chip->fix_nocache) { 2453 for (i = 0; i < chip->bdbars_count; i++) { 2454 struct ichdev *ichdev = &chip->ichd[i]; 2455 if (ichdev->substream && ichdev->page_attr_changed) { 2456 struct snd_pcm_runtime *runtime = ichdev->substream->runtime; 2457 if (runtime->dma_area) 2458 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); 2459 } 2460 } 2461 } 2462 for (i = 0; i < chip->ncodecs; i++) 2463 snd_ac97_suspend(chip->ac97[i]); 2464 if (chip->device_type == DEVICE_INTEL_ICH4) 2465 chip->sdm_saved = igetbyte(chip, ICHREG(SDM)); 2466 2467 if (chip->irq >= 0) { 2468 synchronize_irq(chip->irq); 2469 free_irq(chip->irq, chip); 2470 chip->irq = -1; 2471 } 2472 pci_disable_device(pci); 2473 pci_save_state(pci); 2474 /* The call below may disable built-in speaker on some laptops 2475 * after S2RAM. So, don't touch it. 2476 */ 2477 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */ 2478 return 0; 2479 } 2480 2481 static int intel8x0_resume(struct pci_dev *pci) 2482 { 2483 struct snd_card *card = pci_get_drvdata(pci); 2484 struct intel8x0 *chip = card->private_data; 2485 int i; 2486 2487 pci_set_power_state(pci, PCI_D0); 2488 pci_restore_state(pci); 2489 if (pci_enable_device(pci) < 0) { 2490 printk(KERN_ERR "intel8x0: pci_enable_device failed, " 2491 "disabling device\n"); 2492 snd_card_disconnect(card); 2493 return -EIO; 2494 } 2495 pci_set_master(pci); 2496 snd_intel8x0_chip_init(chip, 0); 2497 if (request_irq(pci->irq, snd_intel8x0_interrupt, 2498 IRQF_SHARED, card->shortname, chip)) { 2499 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, " 2500 "disabling device\n", pci->irq); 2501 snd_card_disconnect(card); 2502 return -EIO; 2503 } 2504 chip->irq = pci->irq; 2505 synchronize_irq(chip->irq); 2506 2507 /* re-initialize mixer stuff */ 2508 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2509 /* enable separate SDINs for ICH4 */ 2510 iputbyte(chip, ICHREG(SDM), chip->sdm_saved); 2511 /* use slot 10/11 for SPDIF */ 2512 iputdword(chip, ICHREG(GLOB_CNT), 2513 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) | 2514 ICH_PCM_SPDIF_1011); 2515 } 2516 2517 /* refill nocache */ 2518 if (chip->fix_nocache) 2519 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2520 2521 for (i = 0; i < chip->ncodecs; i++) 2522 snd_ac97_resume(chip->ac97[i]); 2523 2524 /* refill nocache */ 2525 if (chip->fix_nocache) { 2526 for (i = 0; i < chip->bdbars_count; i++) { 2527 struct ichdev *ichdev = &chip->ichd[i]; 2528 if (ichdev->substream && ichdev->page_attr_changed) { 2529 struct snd_pcm_runtime *runtime = ichdev->substream->runtime; 2530 if (runtime->dma_area) 2531 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 2532 } 2533 } 2534 } 2535 2536 /* resume status */ 2537 for (i = 0; i < chip->bdbars_count; i++) { 2538 struct ichdev *ichdev = &chip->ichd[i]; 2539 unsigned long port = ichdev->reg_offset; 2540 if (! ichdev->substream || ! ichdev->suspended) 2541 continue; 2542 if (ichdev->ichd == ICHD_PCMOUT) 2543 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime); 2544 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 2545 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 2546 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ); 2547 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 2548 } 2549 2550 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2551 return 0; 2552 } 2553 #endif /* CONFIG_PM */ 2554 2555 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */ 2556 2557 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip) 2558 { 2559 struct snd_pcm_substream *subs; 2560 struct ichdev *ichdev; 2561 unsigned long port; 2562 unsigned long pos, t; 2563 struct timeval start_time, stop_time; 2564 2565 if (chip->ac97_bus->clock != 48000) 2566 return; /* specified in module option */ 2567 2568 subs = chip->pcm[0]->streams[0].substream; 2569 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) { 2570 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n"); 2571 return; 2572 } 2573 ichdev = &chip->ichd[ICHD_PCMOUT]; 2574 ichdev->physbuf = subs->dma_buffer.addr; 2575 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE; 2576 ichdev->substream = NULL; /* don't process interrupts */ 2577 2578 /* set rate */ 2579 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) { 2580 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock); 2581 return; 2582 } 2583 snd_intel8x0_setup_periods(chip, ichdev); 2584 port = ichdev->reg_offset; 2585 spin_lock_irq(&chip->reg_lock); 2586 chip->in_measurement = 1; 2587 /* trigger */ 2588 if (chip->device_type != DEVICE_ALI) 2589 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM); 2590 else { 2591 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 2592 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot); 2593 } 2594 do_gettimeofday(&start_time); 2595 spin_unlock_irq(&chip->reg_lock); 2596 msleep(50); 2597 spin_lock_irq(&chip->reg_lock); 2598 /* check the position */ 2599 pos = ichdev->fragsize1; 2600 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift; 2601 pos += ichdev->position; 2602 chip->in_measurement = 0; 2603 do_gettimeofday(&stop_time); 2604 /* stop */ 2605 if (chip->device_type == DEVICE_ALI) { 2606 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16)); 2607 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2608 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 2609 ; 2610 } else { 2611 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2612 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) 2613 ; 2614 } 2615 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 2616 spin_unlock_irq(&chip->reg_lock); 2617 2618 t = stop_time.tv_sec - start_time.tv_sec; 2619 t *= 1000000; 2620 t += stop_time.tv_usec - start_time.tv_usec; 2621 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t); 2622 if (t == 0) { 2623 snd_printk(KERN_ERR "?? calculation error..\n"); 2624 return; 2625 } 2626 pos = (pos / 4) * 1000; 2627 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t; 2628 if (pos < 40000 || pos >= 60000) 2629 /* abnormal value. hw problem? */ 2630 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos); 2631 else if (pos < 47500 || pos > 48500) 2632 /* not 48000Hz, tuning the clock.. */ 2633 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; 2634 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock); 2635 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0); 2636 } 2637 2638 #ifdef CONFIG_PROC_FS 2639 static void snd_intel8x0_proc_read(struct snd_info_entry * entry, 2640 struct snd_info_buffer *buffer) 2641 { 2642 struct intel8x0 *chip = entry->private_data; 2643 unsigned int tmp; 2644 2645 snd_iprintf(buffer, "Intel8x0\n\n"); 2646 if (chip->device_type == DEVICE_ALI) 2647 return; 2648 tmp = igetdword(chip, ICHREG(GLOB_STA)); 2649 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); 2650 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 2651 if (chip->device_type == DEVICE_INTEL_ICH4) 2652 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM))); 2653 snd_iprintf(buffer, "AC'97 codecs ready :"); 2654 if (tmp & chip->codec_isr_bits) { 2655 int i; 2656 static const char *codecs[3] = { 2657 "primary", "secondary", "tertiary" 2658 }; 2659 for (i = 0; i < chip->max_codecs; i++) 2660 if (tmp & chip->codec_bit[i]) 2661 snd_iprintf(buffer, " %s", codecs[i]); 2662 } else 2663 snd_iprintf(buffer, " none"); 2664 snd_iprintf(buffer, "\n"); 2665 if (chip->device_type == DEVICE_INTEL_ICH4 || 2666 chip->device_type == DEVICE_SIS) 2667 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n", 2668 chip->ac97_sdin[0], 2669 chip->ac97_sdin[1], 2670 chip->ac97_sdin[2]); 2671 } 2672 2673 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip) 2674 { 2675 struct snd_info_entry *entry; 2676 2677 if (! snd_card_proc_new(chip->card, "intel8x0", &entry)) 2678 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read); 2679 } 2680 #else 2681 #define snd_intel8x0_proc_init(x) 2682 #endif 2683 2684 static int snd_intel8x0_dev_free(struct snd_device *device) 2685 { 2686 struct intel8x0 *chip = device->device_data; 2687 return snd_intel8x0_free(chip); 2688 } 2689 2690 struct ich_reg_info { 2691 unsigned int int_sta_mask; 2692 unsigned int offset; 2693 }; 2694 2695 static unsigned int ich_codec_bits[3] = { 2696 ICH_PCR, ICH_SCR, ICH_TCR 2697 }; 2698 static unsigned int sis_codec_bits[3] = { 2699 ICH_PCR, ICH_SCR, ICH_SIS_TCR 2700 }; 2701 2702 static int __devinit snd_intel8x0_create(struct snd_card *card, 2703 struct pci_dev *pci, 2704 unsigned long device_type, 2705 struct intel8x0 ** r_intel8x0) 2706 { 2707 struct intel8x0 *chip; 2708 int err; 2709 unsigned int i; 2710 unsigned int int_sta_masks; 2711 struct ichdev *ichdev; 2712 static struct snd_device_ops ops = { 2713 .dev_free = snd_intel8x0_dev_free, 2714 }; 2715 2716 static unsigned int bdbars[] = { 2717 3, /* DEVICE_INTEL */ 2718 6, /* DEVICE_INTEL_ICH4 */ 2719 3, /* DEVICE_SIS */ 2720 6, /* DEVICE_ALI */ 2721 4, /* DEVICE_NFORCE */ 2722 }; 2723 static struct ich_reg_info intel_regs[6] = { 2724 { ICH_PIINT, 0 }, 2725 { ICH_POINT, 0x10 }, 2726 { ICH_MCINT, 0x20 }, 2727 { ICH_M2INT, 0x40 }, 2728 { ICH_P2INT, 0x50 }, 2729 { ICH_SPINT, 0x60 }, 2730 }; 2731 static struct ich_reg_info nforce_regs[4] = { 2732 { ICH_PIINT, 0 }, 2733 { ICH_POINT, 0x10 }, 2734 { ICH_MCINT, 0x20 }, 2735 { ICH_NVSPINT, 0x70 }, 2736 }; 2737 static struct ich_reg_info ali_regs[6] = { 2738 { ALI_INT_PCMIN, 0x40 }, 2739 { ALI_INT_PCMOUT, 0x50 }, 2740 { ALI_INT_MICIN, 0x60 }, 2741 { ALI_INT_CODECSPDIFOUT, 0x70 }, 2742 { ALI_INT_SPDIFIN, 0xa0 }, 2743 { ALI_INT_SPDIFOUT, 0xb0 }, 2744 }; 2745 struct ich_reg_info *tbl; 2746 2747 *r_intel8x0 = NULL; 2748 2749 if ((err = pci_enable_device(pci)) < 0) 2750 return err; 2751 2752 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2753 if (chip == NULL) { 2754 pci_disable_device(pci); 2755 return -ENOMEM; 2756 } 2757 spin_lock_init(&chip->reg_lock); 2758 chip->device_type = device_type; 2759 chip->card = card; 2760 chip->pci = pci; 2761 chip->irq = -1; 2762 2763 /* module parameters */ 2764 chip->buggy_irq = buggy_irq; 2765 chip->buggy_semaphore = buggy_semaphore; 2766 if (xbox) 2767 chip->xbox = 1; 2768 2769 if (pci->vendor == PCI_VENDOR_ID_INTEL && 2770 pci->device == PCI_DEVICE_ID_INTEL_440MX) 2771 chip->fix_nocache = 1; /* enable workaround */ 2772 2773 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 2774 kfree(chip); 2775 pci_disable_device(pci); 2776 return err; 2777 } 2778 2779 if (device_type == DEVICE_ALI) { 2780 /* ALI5455 has no ac97 region */ 2781 chip->bmaddr = pci_iomap(pci, 0, 0); 2782 goto port_inited; 2783 } 2784 2785 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ 2786 chip->addr = pci_iomap(pci, 2, 0); 2787 else 2788 chip->addr = pci_iomap(pci, 0, 0); 2789 if (!chip->addr) { 2790 snd_printk(KERN_ERR "AC'97 space ioremap problem\n"); 2791 snd_intel8x0_free(chip); 2792 return -EIO; 2793 } 2794 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ 2795 chip->bmaddr = pci_iomap(pci, 3, 0); 2796 else 2797 chip->bmaddr = pci_iomap(pci, 1, 0); 2798 if (!chip->bmaddr) { 2799 snd_printk(KERN_ERR "Controller space ioremap problem\n"); 2800 snd_intel8x0_free(chip); 2801 return -EIO; 2802 } 2803 2804 port_inited: 2805 chip->bdbars_count = bdbars[device_type]; 2806 2807 /* initialize offsets */ 2808 switch (device_type) { 2809 case DEVICE_NFORCE: 2810 tbl = nforce_regs; 2811 break; 2812 case DEVICE_ALI: 2813 tbl = ali_regs; 2814 break; 2815 default: 2816 tbl = intel_regs; 2817 break; 2818 } 2819 for (i = 0; i < chip->bdbars_count; i++) { 2820 ichdev = &chip->ichd[i]; 2821 ichdev->ichd = i; 2822 ichdev->reg_offset = tbl[i].offset; 2823 ichdev->int_sta_mask = tbl[i].int_sta_mask; 2824 if (device_type == DEVICE_SIS) { 2825 /* SiS 7012 swaps the registers */ 2826 ichdev->roff_sr = ICH_REG_OFF_PICB; 2827 ichdev->roff_picb = ICH_REG_OFF_SR; 2828 } else { 2829 ichdev->roff_sr = ICH_REG_OFF_SR; 2830 ichdev->roff_picb = ICH_REG_OFF_PICB; 2831 } 2832 if (device_type == DEVICE_ALI) 2833 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 2834 /* SIS7012 handles the pcm data in bytes, others are in samples */ 2835 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 2836 } 2837 2838 /* allocate buffer descriptor lists */ 2839 /* the start of each lists must be aligned to 8 bytes */ 2840 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 2841 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 2842 &chip->bdbars) < 0) { 2843 snd_intel8x0_free(chip); 2844 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n"); 2845 return -ENOMEM; 2846 } 2847 /* tables must be aligned to 8 bytes here, but the kernel pages 2848 are much bigger, so we don't care (on i386) */ 2849 /* workaround for 440MX */ 2850 if (chip->fix_nocache) 2851 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2852 int_sta_masks = 0; 2853 for (i = 0; i < chip->bdbars_count; i++) { 2854 ichdev = &chip->ichd[i]; 2855 ichdev->bdbar = ((u32 *)chip->bdbars.area) + 2856 (i * ICH_MAX_FRAGS * 2); 2857 ichdev->bdbar_addr = chip->bdbars.addr + 2858 (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 2859 int_sta_masks |= ichdev->int_sta_mask; 2860 } 2861 chip->int_sta_reg = device_type == DEVICE_ALI ? 2862 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA; 2863 chip->int_sta_mask = int_sta_masks; 2864 2865 pci_set_master(pci); 2866 2867 switch(chip->device_type) { 2868 case DEVICE_INTEL_ICH4: 2869 /* ICH4 can have three codecs */ 2870 chip->max_codecs = 3; 2871 chip->codec_bit = ich_codec_bits; 2872 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI; 2873 break; 2874 case DEVICE_SIS: 2875 /* recent SIS7012 can have three codecs */ 2876 chip->max_codecs = 3; 2877 chip->codec_bit = sis_codec_bits; 2878 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI; 2879 break; 2880 default: 2881 /* others up to two codecs */ 2882 chip->max_codecs = 2; 2883 chip->codec_bit = ich_codec_bits; 2884 chip->codec_ready_bits = ICH_PRI | ICH_SRI; 2885 break; 2886 } 2887 for (i = 0; i < chip->max_codecs; i++) 2888 chip->codec_isr_bits |= chip->codec_bit[i]; 2889 2890 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 2891 snd_intel8x0_free(chip); 2892 return err; 2893 } 2894 2895 /* request irq after initializaing int_sta_mask, etc */ 2896 if (request_irq(pci->irq, snd_intel8x0_interrupt, 2897 IRQF_SHARED, card->shortname, chip)) { 2898 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2899 snd_intel8x0_free(chip); 2900 return -EBUSY; 2901 } 2902 chip->irq = pci->irq; 2903 2904 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 2905 snd_intel8x0_free(chip); 2906 return err; 2907 } 2908 2909 snd_card_set_dev(card, &pci->dev); 2910 2911 *r_intel8x0 = chip; 2912 return 0; 2913 } 2914 2915 static struct shortname_table { 2916 unsigned int id; 2917 const char *s; 2918 } shortnames[] __devinitdata = { 2919 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" }, 2920 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" }, 2921 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" }, 2922 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" }, 2923 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" }, 2924 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" }, 2925 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" }, 2926 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" }, 2927 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" }, 2928 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" }, 2929 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" }, 2930 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" }, 2931 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" }, 2932 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" }, 2933 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" }, 2934 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" }, 2935 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" }, 2936 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" }, 2937 { 0x003a, "NVidia MCP04" }, 2938 { 0x746d, "AMD AMD8111" }, 2939 { 0x7445, "AMD AMD768" }, 2940 { 0x5455, "ALi M5455" }, 2941 { 0, NULL }, 2942 }; 2943 2944 static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = { 2945 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1), 2946 { } /* end */ 2947 }; 2948 2949 /* look up white/black list for SPDIF over ac-link */ 2950 static int __devinit check_default_spdif_aclink(struct pci_dev *pci) 2951 { 2952 const struct snd_pci_quirk *w; 2953 2954 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults); 2955 if (w) { 2956 if (w->value) 2957 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over " 2958 "AC-Link for %s\n", w->name); 2959 else 2960 snd_printdd(KERN_INFO "intel8x0: Using integrated " 2961 "SPDIF DMA for %s\n", w->name); 2962 return w->value; 2963 } 2964 return 0; 2965 } 2966 2967 static int __devinit snd_intel8x0_probe(struct pci_dev *pci, 2968 const struct pci_device_id *pci_id) 2969 { 2970 struct snd_card *card; 2971 struct intel8x0 *chip; 2972 int err; 2973 struct shortname_table *name; 2974 2975 card = snd_card_new(index, id, THIS_MODULE, 0); 2976 if (card == NULL) 2977 return -ENOMEM; 2978 2979 if (spdif_aclink < 0) 2980 spdif_aclink = check_default_spdif_aclink(pci); 2981 2982 strcpy(card->driver, "ICH"); 2983 if (!spdif_aclink) { 2984 switch (pci_id->driver_data) { 2985 case DEVICE_NFORCE: 2986 strcpy(card->driver, "NFORCE"); 2987 break; 2988 case DEVICE_INTEL_ICH4: 2989 strcpy(card->driver, "ICH4"); 2990 } 2991 } 2992 2993 strcpy(card->shortname, "Intel ICH"); 2994 for (name = shortnames; name->id; name++) { 2995 if (pci->device == name->id) { 2996 strcpy(card->shortname, name->s); 2997 break; 2998 } 2999 } 3000 3001 if (buggy_irq < 0) { 3002 /* some Nforce[2] and ICH boards have problems with IRQ handling. 3003 * Needs to return IRQ_HANDLED for unknown irqs. 3004 */ 3005 if (pci_id->driver_data == DEVICE_NFORCE) 3006 buggy_irq = 1; 3007 else 3008 buggy_irq = 0; 3009 } 3010 3011 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, 3012 &chip)) < 0) { 3013 snd_card_free(card); 3014 return err; 3015 } 3016 card->private_data = chip; 3017 3018 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) { 3019 snd_card_free(card); 3020 return err; 3021 } 3022 if ((err = snd_intel8x0_pcm(chip)) < 0) { 3023 snd_card_free(card); 3024 return err; 3025 } 3026 3027 snd_intel8x0_proc_init(chip); 3028 3029 snprintf(card->longname, sizeof(card->longname), 3030 "%s with %s at irq %i", card->shortname, 3031 snd_ac97_get_short_name(chip->ac97[0]), chip->irq); 3032 3033 if (! ac97_clock) 3034 intel8x0_measure_ac97_clock(chip); 3035 3036 if ((err = snd_card_register(card)) < 0) { 3037 snd_card_free(card); 3038 return err; 3039 } 3040 pci_set_drvdata(pci, card); 3041 return 0; 3042 } 3043 3044 static void __devexit snd_intel8x0_remove(struct pci_dev *pci) 3045 { 3046 snd_card_free(pci_get_drvdata(pci)); 3047 pci_set_drvdata(pci, NULL); 3048 } 3049 3050 static struct pci_driver driver = { 3051 .name = "Intel ICH", 3052 .id_table = snd_intel8x0_ids, 3053 .probe = snd_intel8x0_probe, 3054 .remove = __devexit_p(snd_intel8x0_remove), 3055 #ifdef CONFIG_PM 3056 .suspend = intel8x0_suspend, 3057 .resume = intel8x0_resume, 3058 #endif 3059 }; 3060 3061 3062 static int __init alsa_card_intel8x0_init(void) 3063 { 3064 return pci_register_driver(&driver); 3065 } 3066 3067 static void __exit alsa_card_intel8x0_exit(void) 3068 { 3069 pci_unregister_driver(&driver); 3070 } 3071 3072 module_init(alsa_card_intel8x0_init) 3073 module_exit(alsa_card_intel8x0_exit) 3074