1 /* 2 * Universal Interface for Intel High Definition Audio Codec 3 * 4 * HD audio interface patch for Silicon Labs 3054/5 modem codec 5 * 6 * Copyright (c) 2005 Sasha Khapyorsky <sashak@alsa-project.org> 7 * Takashi Iwai <tiwai@suse.de> 8 * 9 * 10 * This driver is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This driver is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 */ 24 25 #include <sound/driver.h> 26 #include <linux/init.h> 27 #include <linux/delay.h> 28 #include <linux/slab.h> 29 #include <sound/core.h> 30 #include "hda_codec.h" 31 #include "hda_local.h" 32 33 34 /* si3054 verbs */ 35 #define SI3054_VERB_READ_NODE 0x900 36 #define SI3054_VERB_WRITE_NODE 0x100 37 38 /* si3054 nodes (registers) */ 39 #define SI3054_EXTENDED_MID 2 40 #define SI3054_LINE_RATE 3 41 #define SI3054_LINE_LEVEL 4 42 #define SI3054_GPIO_CFG 5 43 #define SI3054_GPIO_POLARITY 6 44 #define SI3054_GPIO_STICKY 7 45 #define SI3054_GPIO_WAKEUP 8 46 #define SI3054_GPIO_STATUS 9 47 #define SI3054_GPIO_CONTROL 10 48 #define SI3054_MISC_AFE 11 49 #define SI3054_CHIPID 12 50 #define SI3054_LINE_CFG1 13 51 #define SI3054_LINE_STATUS 14 52 #define SI3054_DC_TERMINATION 15 53 #define SI3054_LINE_CONFIG 16 54 #define SI3054_CALLPROG_ATT 17 55 #define SI3054_SQ_CONTROL 18 56 #define SI3054_MISC_CONTROL 19 57 #define SI3054_RING_CTRL1 20 58 #define SI3054_RING_CTRL2 21 59 60 /* extended MID */ 61 #define SI3054_MEI_READY 0xf 62 63 /* line level */ 64 #define SI3054_ATAG_MASK 0x00f0 65 #define SI3054_DTAG_MASK 0xf000 66 67 /* GPIO bits */ 68 #define SI3054_GPIO_OH 0x0001 69 #define SI3054_GPIO_CID 0x0002 70 71 /* chipid and revisions */ 72 #define SI3054_CHIPID_CODEC_REV_MASK 0x000f 73 #define SI3054_CHIPID_DAA_REV_MASK 0x00f0 74 #define SI3054_CHIPID_INTERNATIONAL 0x0100 75 #define SI3054_CHIPID_DAA_ID 0x0f00 76 #define SI3054_CHIPID_CODEC_ID (1<<12) 77 78 /* si3054 codec registers (nodes) access macros */ 79 #define GET_REG(codec,reg) (snd_hda_codec_read(codec,reg,0,SI3054_VERB_READ_NODE,0)) 80 #define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val)) 81 #define SET_REG_CACHE(codec,reg,val) \ 82 snd_hda_codec_write_cache(codec,reg,0,SI3054_VERB_WRITE_NODE,val) 83 84 85 struct si3054_spec { 86 unsigned international; 87 struct hda_pcm pcm; 88 }; 89 90 91 /* 92 * Modem mixer 93 */ 94 95 #define PRIVATE_VALUE(reg,mask) ((reg<<16)|(mask&0xffff)) 96 #define PRIVATE_REG(val) ((val>>16)&0xffff) 97 #define PRIVATE_MASK(val) (val&0xffff) 98 99 #define si3054_switch_info snd_ctl_boolean_mono_info 100 101 static int si3054_switch_get(struct snd_kcontrol *kcontrol, 102 struct snd_ctl_elem_value *uvalue) 103 { 104 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 105 u16 reg = PRIVATE_REG(kcontrol->private_value); 106 u16 mask = PRIVATE_MASK(kcontrol->private_value); 107 uvalue->value.integer.value[0] = (GET_REG(codec, reg)) & mask ? 1 : 0 ; 108 return 0; 109 } 110 111 static int si3054_switch_put(struct snd_kcontrol *kcontrol, 112 struct snd_ctl_elem_value *uvalue) 113 { 114 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 115 u16 reg = PRIVATE_REG(kcontrol->private_value); 116 u16 mask = PRIVATE_MASK(kcontrol->private_value); 117 if (uvalue->value.integer.value[0]) 118 SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) | mask); 119 else 120 SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) & ~mask); 121 return 0; 122 } 123 124 #define SI3054_KCONTROL(kname,reg,mask) { \ 125 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 126 .name = kname, \ 127 .info = si3054_switch_info, \ 128 .get = si3054_switch_get, \ 129 .put = si3054_switch_put, \ 130 .private_value = PRIVATE_VALUE(reg,mask), \ 131 } 132 133 134 static struct snd_kcontrol_new si3054_modem_mixer[] = { 135 SI3054_KCONTROL("Off-hook Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_OH), 136 SI3054_KCONTROL("Caller ID Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_CID), 137 {} 138 }; 139 140 static int si3054_build_controls(struct hda_codec *codec) 141 { 142 return snd_hda_add_new_ctls(codec, si3054_modem_mixer); 143 } 144 145 146 /* 147 * PCM callbacks 148 */ 149 150 static int si3054_pcm_prepare(struct hda_pcm_stream *hinfo, 151 struct hda_codec *codec, 152 unsigned int stream_tag, 153 unsigned int format, 154 struct snd_pcm_substream *substream) 155 { 156 u16 val; 157 158 SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate); 159 val = GET_REG(codec, SI3054_LINE_LEVEL); 160 val &= 0xff << (8 * (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)); 161 val |= ((stream_tag & 0xf) << 4) << (8 * (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)); 162 SET_REG(codec, SI3054_LINE_LEVEL, val); 163 164 snd_hda_codec_setup_stream(codec, hinfo->nid, 165 stream_tag, 0, format); 166 return 0; 167 } 168 169 static int si3054_pcm_open(struct hda_pcm_stream *hinfo, 170 struct hda_codec *codec, 171 struct snd_pcm_substream *substream) 172 { 173 static unsigned int rates[] = { 8000, 9600, 16000 }; 174 static struct snd_pcm_hw_constraint_list hw_constraints_rates = { 175 .count = ARRAY_SIZE(rates), 176 .list = rates, 177 .mask = 0, 178 }; 179 substream->runtime->hw.period_bytes_min = 80; 180 return snd_pcm_hw_constraint_list(substream->runtime, 0, 181 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); 182 } 183 184 185 static struct hda_pcm_stream si3054_pcm = { 186 .substreams = 1, 187 .channels_min = 1, 188 .channels_max = 1, 189 .nid = 0x1, 190 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_KNOT, 191 .formats = SNDRV_PCM_FMTBIT_S16_LE, 192 .maxbps = 16, 193 .ops = { 194 .open = si3054_pcm_open, 195 .prepare = si3054_pcm_prepare, 196 }, 197 }; 198 199 200 static int si3054_build_pcms(struct hda_codec *codec) 201 { 202 struct si3054_spec *spec = codec->spec; 203 struct hda_pcm *info = &spec->pcm; 204 si3054_pcm.nid = codec->mfg; 205 codec->num_pcms = 1; 206 codec->pcm_info = info; 207 info->name = "Si3054 Modem"; 208 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = si3054_pcm; 209 info->stream[SNDRV_PCM_STREAM_CAPTURE] = si3054_pcm; 210 info->is_modem = 1; 211 return 0; 212 } 213 214 215 /* 216 * Init part 217 */ 218 219 static int si3054_init(struct hda_codec *codec) 220 { 221 struct si3054_spec *spec = codec->spec; 222 unsigned wait_count; 223 u16 val; 224 225 snd_hda_codec_write(codec, AC_NODE_ROOT, 0, AC_VERB_SET_CODEC_RESET, 0); 226 snd_hda_codec_write(codec, codec->mfg, 0, AC_VERB_SET_STREAM_FORMAT, 0); 227 SET_REG(codec, SI3054_LINE_RATE, 9600); 228 SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK); 229 SET_REG(codec, SI3054_EXTENDED_MID, 0); 230 231 wait_count = 10; 232 do { 233 msleep(2); 234 val = GET_REG(codec, SI3054_EXTENDED_MID); 235 } while ((val & SI3054_MEI_READY) != SI3054_MEI_READY && wait_count--); 236 237 if((val&SI3054_MEI_READY) != SI3054_MEI_READY) { 238 snd_printk(KERN_ERR "si3054: cannot initialize. EXT MID = %04x\n", val); 239 /* let's pray that this is no fatal error */ 240 /* return -EACCES; */ 241 } 242 243 SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff); 244 SET_REG(codec, SI3054_GPIO_CFG, 0x0); 245 SET_REG(codec, SI3054_MISC_AFE, 0); 246 SET_REG(codec, SI3054_LINE_CFG1,0x200); 247 248 if((GET_REG(codec,SI3054_LINE_STATUS) & (1<<6)) == 0) { 249 snd_printd("Link Frame Detect(FDT) is not ready (line status: %04x)\n", 250 GET_REG(codec,SI3054_LINE_STATUS)); 251 } 252 253 spec->international = GET_REG(codec, SI3054_CHIPID) & SI3054_CHIPID_INTERNATIONAL; 254 255 return 0; 256 } 257 258 static void si3054_free(struct hda_codec *codec) 259 { 260 kfree(codec->spec); 261 } 262 263 264 /* 265 */ 266 267 static struct hda_codec_ops si3054_patch_ops = { 268 .build_controls = si3054_build_controls, 269 .build_pcms = si3054_build_pcms, 270 .init = si3054_init, 271 .free = si3054_free, 272 }; 273 274 static int patch_si3054(struct hda_codec *codec) 275 { 276 struct si3054_spec *spec = kzalloc(sizeof(*spec), GFP_KERNEL); 277 if (spec == NULL) 278 return -ENOMEM; 279 codec->spec = spec; 280 codec->patch_ops = si3054_patch_ops; 281 return 0; 282 } 283 284 /* 285 * patch entries 286 */ 287 struct hda_codec_preset snd_hda_preset_si3054[] = { 288 { .id = 0x163c3055, .name = "Si3054", .patch = patch_si3054 }, 289 { .id = 0x163c3155, .name = "Si3054", .patch = patch_si3054 }, 290 { .id = 0x11c11040, .name = "Si3054", .patch = patch_si3054 }, 291 { .id = 0x11c13026, .name = "Si3054", .patch = patch_si3054 }, 292 { .id = 0x11c13055, .name = "Si3054", .patch = patch_si3054 }, 293 { .id = 0x11c13155, .name = "Si3054", .patch = patch_si3054 }, 294 { .id = 0x10573055, .name = "Si3054", .patch = patch_si3054 }, 295 { .id = 0x10573057, .name = "Si3054", .patch = patch_si3054 }, 296 { .id = 0x10573155, .name = "Si3054", .patch = patch_si3054 }, 297 /* VIA HDA on Clevo m540 */ 298 { .id = 0x11063288, .name = "Si3054", .patch = patch_si3054 }, 299 /* Asus A8J Modem (SM56) */ 300 { .id = 0x15433155, .name = "Si3054", .patch = patch_si3054 }, 301 /* LG LW20 modem */ 302 { .id = 0x18540018, .name = "Si3054", .patch = patch_si3054 }, 303 {} 304 }; 305 306