1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 static bool enable_silent_stream = 46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); 47 module_param(enable_silent_stream, bool, 0644); 48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); 49 50 struct hdmi_spec_per_cvt { 51 hda_nid_t cvt_nid; 52 int assigned; 53 unsigned int channels_min; 54 unsigned int channels_max; 55 u32 rates; 56 u64 formats; 57 unsigned int maxbps; 58 }; 59 60 /* max. connections to a widget */ 61 #define HDA_MAX_CONNECTIONS 32 62 63 struct hdmi_spec_per_pin { 64 hda_nid_t pin_nid; 65 int dev_id; 66 /* pin idx, different device entries on the same pin use the same idx */ 67 int pin_nid_idx; 68 int num_mux_nids; 69 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 70 int mux_idx; 71 hda_nid_t cvt_nid; 72 73 struct hda_codec *codec; 74 struct hdmi_eld sink_eld; 75 struct mutex lock; 76 struct delayed_work work; 77 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 78 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 79 int repoll_count; 80 bool setup; /* the stream has been set up by prepare callback */ 81 int channels; /* current number of channels */ 82 bool non_pcm; 83 bool chmap_set; /* channel-map override by ALSA API? */ 84 unsigned char chmap[8]; /* ALSA API channel-map */ 85 #ifdef CONFIG_SND_PROC_FS 86 struct snd_info_entry *proc_entry; 87 #endif 88 }; 89 90 /* operations used by generic code that can be overridden by patches */ 91 struct hdmi_ops { 92 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 93 int dev_id, unsigned char *buf, int *eld_size); 94 95 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 96 int dev_id, 97 int ca, int active_channels, int conn_type); 98 99 /* enable/disable HBR (HD passthrough) */ 100 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 101 int dev_id, bool hbr); 102 103 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 104 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 105 int format); 106 107 void (*pin_cvt_fixup)(struct hda_codec *codec, 108 struct hdmi_spec_per_pin *per_pin, 109 hda_nid_t cvt_nid); 110 }; 111 112 struct hdmi_pcm { 113 struct hda_pcm *pcm; 114 struct snd_jack *jack; 115 struct snd_kcontrol *eld_ctl; 116 }; 117 118 struct hdmi_spec { 119 struct hda_codec *codec; 120 int num_cvts; 121 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 122 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 123 124 /* 125 * num_pins is the number of virtual pins 126 * for example, there are 3 pins, and each pin 127 * has 4 device entries, then the num_pins is 12 128 */ 129 int num_pins; 130 /* 131 * num_nids is the number of real pins 132 * In the above example, num_nids is 3 133 */ 134 int num_nids; 135 /* 136 * dev_num is the number of device entries 137 * on each pin. 138 * In the above example, dev_num is 4 139 */ 140 int dev_num; 141 struct snd_array pins; /* struct hdmi_spec_per_pin */ 142 struct hdmi_pcm pcm_rec[16]; 143 struct mutex pcm_lock; 144 struct mutex bind_lock; /* for audio component binding */ 145 /* pcm_bitmap means which pcms have been assigned to pins*/ 146 unsigned long pcm_bitmap; 147 int pcm_used; /* counter of pcm_rec[] */ 148 /* bitmap shows whether the pcm is opened in user space 149 * bit 0 means the first playback PCM (PCM3); 150 * bit 1 means the second playback PCM, and so on. 151 */ 152 unsigned long pcm_in_use; 153 154 struct hdmi_eld temp_eld; 155 struct hdmi_ops ops; 156 157 bool dyn_pin_out; 158 bool dyn_pcm_assign; 159 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 160 /* 161 * Non-generic VIA/NVIDIA specific 162 */ 163 struct hda_multi_out multiout; 164 struct hda_pcm_stream pcm_playback; 165 166 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 167 bool acomp_registered; /* audio component registered in this driver */ 168 struct drm_audio_component_audio_ops drm_audio_ops; 169 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 170 171 struct hdac_chmap chmap; 172 hda_nid_t vendor_nid; 173 const int *port_map; 174 int port_num; 175 bool send_silent_stream; /* Flag to enable silent stream feature */ 176 }; 177 178 #ifdef CONFIG_SND_HDA_COMPONENT 179 static inline bool codec_has_acomp(struct hda_codec *codec) 180 { 181 struct hdmi_spec *spec = codec->spec; 182 return spec->use_acomp_notifier; 183 } 184 #else 185 #define codec_has_acomp(codec) false 186 #endif 187 188 struct hdmi_audio_infoframe { 189 u8 type; /* 0x84 */ 190 u8 ver; /* 0x01 */ 191 u8 len; /* 0x0a */ 192 193 u8 checksum; 194 195 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 196 u8 SS01_SF24; 197 u8 CXT04; 198 u8 CA; 199 u8 LFEPBL01_LSV36_DM_INH7; 200 }; 201 202 struct dp_audio_infoframe { 203 u8 type; /* 0x84 */ 204 u8 len; /* 0x1b */ 205 u8 ver; /* 0x11 << 2 */ 206 207 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 208 u8 SS01_SF24; 209 u8 CXT04; 210 u8 CA; 211 u8 LFEPBL01_LSV36_DM_INH7; 212 }; 213 214 union audio_infoframe { 215 struct hdmi_audio_infoframe hdmi; 216 struct dp_audio_infoframe dp; 217 u8 bytes[0]; 218 }; 219 220 /* 221 * HDMI routines 222 */ 223 224 #define get_pin(spec, idx) \ 225 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 226 #define get_cvt(spec, idx) \ 227 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 228 /* obtain hdmi_pcm object assigned to idx */ 229 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 230 /* obtain hda_pcm object assigned to idx */ 231 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 232 233 static int pin_id_to_pin_index(struct hda_codec *codec, 234 hda_nid_t pin_nid, int dev_id) 235 { 236 struct hdmi_spec *spec = codec->spec; 237 int pin_idx; 238 struct hdmi_spec_per_pin *per_pin; 239 240 /* 241 * (dev_id == -1) means it is NON-MST pin 242 * return the first virtual pin on this port 243 */ 244 if (dev_id == -1) 245 dev_id = 0; 246 247 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 248 per_pin = get_pin(spec, pin_idx); 249 if ((per_pin->pin_nid == pin_nid) && 250 (per_pin->dev_id == dev_id)) 251 return pin_idx; 252 } 253 254 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 255 return -EINVAL; 256 } 257 258 static int hinfo_to_pcm_index(struct hda_codec *codec, 259 struct hda_pcm_stream *hinfo) 260 { 261 struct hdmi_spec *spec = codec->spec; 262 int pcm_idx; 263 264 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 265 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 266 return pcm_idx; 267 268 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 269 return -EINVAL; 270 } 271 272 static int hinfo_to_pin_index(struct hda_codec *codec, 273 struct hda_pcm_stream *hinfo) 274 { 275 struct hdmi_spec *spec = codec->spec; 276 struct hdmi_spec_per_pin *per_pin; 277 int pin_idx; 278 279 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 280 per_pin = get_pin(spec, pin_idx); 281 if (per_pin->pcm && 282 per_pin->pcm->pcm->stream == hinfo) 283 return pin_idx; 284 } 285 286 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); 287 return -EINVAL; 288 } 289 290 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 291 int pcm_idx) 292 { 293 int i; 294 struct hdmi_spec_per_pin *per_pin; 295 296 for (i = 0; i < spec->num_pins; i++) { 297 per_pin = get_pin(spec, i); 298 if (per_pin->pcm_idx == pcm_idx) 299 return per_pin; 300 } 301 return NULL; 302 } 303 304 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 305 { 306 struct hdmi_spec *spec = codec->spec; 307 int cvt_idx; 308 309 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 310 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 311 return cvt_idx; 312 313 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 314 return -EINVAL; 315 } 316 317 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 318 struct snd_ctl_elem_info *uinfo) 319 { 320 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 321 struct hdmi_spec *spec = codec->spec; 322 struct hdmi_spec_per_pin *per_pin; 323 struct hdmi_eld *eld; 324 int pcm_idx; 325 326 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 327 328 pcm_idx = kcontrol->private_value; 329 mutex_lock(&spec->pcm_lock); 330 per_pin = pcm_idx_to_pin(spec, pcm_idx); 331 if (!per_pin) { 332 /* no pin is bound to the pcm */ 333 uinfo->count = 0; 334 goto unlock; 335 } 336 eld = &per_pin->sink_eld; 337 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 338 339 unlock: 340 mutex_unlock(&spec->pcm_lock); 341 return 0; 342 } 343 344 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 345 struct snd_ctl_elem_value *ucontrol) 346 { 347 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 348 struct hdmi_spec *spec = codec->spec; 349 struct hdmi_spec_per_pin *per_pin; 350 struct hdmi_eld *eld; 351 int pcm_idx; 352 int err = 0; 353 354 pcm_idx = kcontrol->private_value; 355 mutex_lock(&spec->pcm_lock); 356 per_pin = pcm_idx_to_pin(spec, pcm_idx); 357 if (!per_pin) { 358 /* no pin is bound to the pcm */ 359 memset(ucontrol->value.bytes.data, 0, 360 ARRAY_SIZE(ucontrol->value.bytes.data)); 361 goto unlock; 362 } 363 364 eld = &per_pin->sink_eld; 365 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 366 eld->eld_size > ELD_MAX_SIZE) { 367 snd_BUG(); 368 err = -EINVAL; 369 goto unlock; 370 } 371 372 memset(ucontrol->value.bytes.data, 0, 373 ARRAY_SIZE(ucontrol->value.bytes.data)); 374 if (eld->eld_valid) 375 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 376 eld->eld_size); 377 378 unlock: 379 mutex_unlock(&spec->pcm_lock); 380 return err; 381 } 382 383 static const struct snd_kcontrol_new eld_bytes_ctl = { 384 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 385 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 386 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 387 .name = "ELD", 388 .info = hdmi_eld_ctl_info, 389 .get = hdmi_eld_ctl_get, 390 }; 391 392 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 393 int device) 394 { 395 struct snd_kcontrol *kctl; 396 struct hdmi_spec *spec = codec->spec; 397 int err; 398 399 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 400 if (!kctl) 401 return -ENOMEM; 402 kctl->private_value = pcm_idx; 403 kctl->id.device = device; 404 405 /* no pin nid is associated with the kctl now 406 * tbd: associate pin nid to eld ctl later 407 */ 408 err = snd_hda_ctl_add(codec, 0, kctl); 409 if (err < 0) 410 return err; 411 412 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 413 return 0; 414 } 415 416 #ifdef BE_PARANOID 417 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 418 int *packet_index, int *byte_index) 419 { 420 int val; 421 422 val = snd_hda_codec_read(codec, pin_nid, 0, 423 AC_VERB_GET_HDMI_DIP_INDEX, 0); 424 425 *packet_index = val >> 5; 426 *byte_index = val & 0x1f; 427 } 428 #endif 429 430 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 431 int packet_index, int byte_index) 432 { 433 int val; 434 435 val = (packet_index << 5) | (byte_index & 0x1f); 436 437 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 438 } 439 440 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 441 unsigned char val) 442 { 443 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 444 } 445 446 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 447 { 448 struct hdmi_spec *spec = codec->spec; 449 int pin_out; 450 451 /* Unmute */ 452 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 453 snd_hda_codec_write(codec, pin_nid, 0, 454 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 455 456 if (spec->dyn_pin_out) 457 /* Disable pin out until stream is active */ 458 pin_out = 0; 459 else 460 /* Enable pin out: some machines with GM965 gets broken output 461 * when the pin is disabled or changed while using with HDMI 462 */ 463 pin_out = PIN_OUT; 464 465 snd_hda_codec_write(codec, pin_nid, 0, 466 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 467 } 468 469 /* 470 * ELD proc files 471 */ 472 473 #ifdef CONFIG_SND_PROC_FS 474 static void print_eld_info(struct snd_info_entry *entry, 475 struct snd_info_buffer *buffer) 476 { 477 struct hdmi_spec_per_pin *per_pin = entry->private_data; 478 479 mutex_lock(&per_pin->lock); 480 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 481 mutex_unlock(&per_pin->lock); 482 } 483 484 static void write_eld_info(struct snd_info_entry *entry, 485 struct snd_info_buffer *buffer) 486 { 487 struct hdmi_spec_per_pin *per_pin = entry->private_data; 488 489 mutex_lock(&per_pin->lock); 490 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 491 mutex_unlock(&per_pin->lock); 492 } 493 494 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 495 { 496 char name[32]; 497 struct hda_codec *codec = per_pin->codec; 498 struct snd_info_entry *entry; 499 int err; 500 501 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 502 err = snd_card_proc_new(codec->card, name, &entry); 503 if (err < 0) 504 return err; 505 506 snd_info_set_text_ops(entry, per_pin, print_eld_info); 507 entry->c.text.write = write_eld_info; 508 entry->mode |= 0200; 509 per_pin->proc_entry = entry; 510 511 return 0; 512 } 513 514 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 515 { 516 if (!per_pin->codec->bus->shutdown) { 517 snd_info_free_entry(per_pin->proc_entry); 518 per_pin->proc_entry = NULL; 519 } 520 } 521 #else 522 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 523 int index) 524 { 525 return 0; 526 } 527 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 528 { 529 } 530 #endif 531 532 /* 533 * Audio InfoFrame routines 534 */ 535 536 /* 537 * Enable Audio InfoFrame Transmission 538 */ 539 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 540 hda_nid_t pin_nid) 541 { 542 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 543 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 544 AC_DIPXMIT_BEST); 545 } 546 547 /* 548 * Disable Audio InfoFrame Transmission 549 */ 550 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 551 hda_nid_t pin_nid) 552 { 553 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 554 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 555 AC_DIPXMIT_DISABLE); 556 } 557 558 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 559 { 560 #ifdef CONFIG_SND_DEBUG_VERBOSE 561 int i; 562 int size; 563 564 size = snd_hdmi_get_eld_size(codec, pin_nid); 565 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 566 567 for (i = 0; i < 8; i++) { 568 size = snd_hda_codec_read(codec, pin_nid, 0, 569 AC_VERB_GET_HDMI_DIP_SIZE, i); 570 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 571 } 572 #endif 573 } 574 575 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 576 { 577 #ifdef BE_PARANOID 578 int i, j; 579 int size; 580 int pi, bi; 581 for (i = 0; i < 8; i++) { 582 size = snd_hda_codec_read(codec, pin_nid, 0, 583 AC_VERB_GET_HDMI_DIP_SIZE, i); 584 if (size == 0) 585 continue; 586 587 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 588 for (j = 1; j < 1000; j++) { 589 hdmi_write_dip_byte(codec, pin_nid, 0x0); 590 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 591 if (pi != i) 592 codec_dbg(codec, "dip index %d: %d != %d\n", 593 bi, pi, i); 594 if (bi == 0) /* byte index wrapped around */ 595 break; 596 } 597 codec_dbg(codec, 598 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 599 i, size, j); 600 } 601 #endif 602 } 603 604 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 605 { 606 u8 *bytes = (u8 *)hdmi_ai; 607 u8 sum = 0; 608 int i; 609 610 hdmi_ai->checksum = 0; 611 612 for (i = 0; i < sizeof(*hdmi_ai); i++) 613 sum += bytes[i]; 614 615 hdmi_ai->checksum = -sum; 616 } 617 618 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 619 hda_nid_t pin_nid, 620 u8 *dip, int size) 621 { 622 int i; 623 624 hdmi_debug_dip_size(codec, pin_nid); 625 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 626 627 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 628 for (i = 0; i < size; i++) 629 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 630 } 631 632 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 633 u8 *dip, int size) 634 { 635 u8 val; 636 int i; 637 638 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 639 != AC_DIPXMIT_BEST) 640 return false; 641 642 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 643 for (i = 0; i < size; i++) { 644 val = snd_hda_codec_read(codec, pin_nid, 0, 645 AC_VERB_GET_HDMI_DIP_DATA, 0); 646 if (val != dip[i]) 647 return false; 648 } 649 650 return true; 651 } 652 653 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 654 int dev_id, unsigned char *buf, int *eld_size) 655 { 656 snd_hda_set_dev_select(codec, nid, dev_id); 657 658 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 659 } 660 661 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 662 hda_nid_t pin_nid, int dev_id, 663 int ca, int active_channels, 664 int conn_type) 665 { 666 union audio_infoframe ai; 667 668 memset(&ai, 0, sizeof(ai)); 669 if (conn_type == 0) { /* HDMI */ 670 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 671 672 hdmi_ai->type = 0x84; 673 hdmi_ai->ver = 0x01; 674 hdmi_ai->len = 0x0a; 675 hdmi_ai->CC02_CT47 = active_channels - 1; 676 hdmi_ai->CA = ca; 677 hdmi_checksum_audio_infoframe(hdmi_ai); 678 } else if (conn_type == 1) { /* DisplayPort */ 679 struct dp_audio_infoframe *dp_ai = &ai.dp; 680 681 dp_ai->type = 0x84; 682 dp_ai->len = 0x1b; 683 dp_ai->ver = 0x11 << 2; 684 dp_ai->CC02_CT47 = active_channels - 1; 685 dp_ai->CA = ca; 686 } else { 687 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 688 pin_nid); 689 return; 690 } 691 692 snd_hda_set_dev_select(codec, pin_nid, dev_id); 693 694 /* 695 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 696 * sizeof(*dp_ai) to avoid partial match/update problems when 697 * the user switches between HDMI/DP monitors. 698 */ 699 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 700 sizeof(ai))) { 701 codec_dbg(codec, 702 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 703 pin_nid, 704 active_channels, ca); 705 hdmi_stop_infoframe_trans(codec, pin_nid); 706 hdmi_fill_audio_infoframe(codec, pin_nid, 707 ai.bytes, sizeof(ai)); 708 hdmi_start_infoframe_trans(codec, pin_nid); 709 } 710 } 711 712 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 713 struct hdmi_spec_per_pin *per_pin, 714 bool non_pcm) 715 { 716 struct hdmi_spec *spec = codec->spec; 717 struct hdac_chmap *chmap = &spec->chmap; 718 hda_nid_t pin_nid = per_pin->pin_nid; 719 int dev_id = per_pin->dev_id; 720 int channels = per_pin->channels; 721 int active_channels; 722 struct hdmi_eld *eld; 723 int ca; 724 725 if (!channels) 726 return; 727 728 snd_hda_set_dev_select(codec, pin_nid, dev_id); 729 730 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 731 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 732 snd_hda_codec_write(codec, pin_nid, 0, 733 AC_VERB_SET_AMP_GAIN_MUTE, 734 AMP_OUT_UNMUTE); 735 736 eld = &per_pin->sink_eld; 737 738 ca = snd_hdac_channel_allocation(&codec->core, 739 eld->info.spk_alloc, channels, 740 per_pin->chmap_set, non_pcm, per_pin->chmap); 741 742 active_channels = snd_hdac_get_active_channels(ca); 743 744 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 745 active_channels); 746 747 /* 748 * always configure channel mapping, it may have been changed by the 749 * user in the meantime 750 */ 751 snd_hdac_setup_channel_mapping(&spec->chmap, 752 pin_nid, non_pcm, ca, channels, 753 per_pin->chmap, per_pin->chmap_set); 754 755 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 756 ca, active_channels, eld->info.conn_type); 757 758 per_pin->non_pcm = non_pcm; 759 } 760 761 /* 762 * Unsolicited events 763 */ 764 765 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 766 767 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 768 int dev_id) 769 { 770 struct hdmi_spec *spec = codec->spec; 771 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 772 773 if (pin_idx < 0) 774 return; 775 mutex_lock(&spec->pcm_lock); 776 hdmi_present_sense(get_pin(spec, pin_idx), 1); 777 mutex_unlock(&spec->pcm_lock); 778 } 779 780 static void jack_callback(struct hda_codec *codec, 781 struct hda_jack_callback *jack) 782 { 783 /* stop polling when notification is enabled */ 784 if (codec_has_acomp(codec)) 785 return; 786 787 check_presence_and_report(codec, jack->nid, jack->dev_id); 788 } 789 790 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 791 struct hda_jack_tbl *jack) 792 { 793 jack->jack_dirty = 1; 794 795 codec_dbg(codec, 796 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 797 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 798 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 799 800 check_presence_and_report(codec, jack->nid, jack->dev_id); 801 } 802 803 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 804 { 805 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 806 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 807 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 808 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 809 810 codec_info(codec, 811 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 812 codec->addr, 813 tag, 814 subtag, 815 cp_state, 816 cp_ready); 817 818 /* TODO */ 819 if (cp_state) { 820 ; 821 } 822 if (cp_ready) { 823 ; 824 } 825 } 826 827 828 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 829 { 830 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 831 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 832 struct hda_jack_tbl *jack; 833 834 if (codec_has_acomp(codec)) 835 return; 836 837 if (codec->dp_mst) { 838 int dev_entry = 839 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 840 841 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 842 } else { 843 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 844 } 845 846 if (!jack) { 847 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 848 return; 849 } 850 851 if (subtag == 0) 852 hdmi_intrinsic_event(codec, res, jack); 853 else 854 hdmi_non_intrinsic_event(codec, res); 855 } 856 857 static void haswell_verify_D0(struct hda_codec *codec, 858 hda_nid_t cvt_nid, hda_nid_t nid) 859 { 860 int pwr; 861 862 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 863 * thus pins could only choose converter 0 for use. Make sure the 864 * converters are in correct power state */ 865 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 866 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 867 868 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 869 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 870 AC_PWRST_D0); 871 msleep(40); 872 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 873 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 874 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 875 } 876 } 877 878 /* 879 * Callbacks 880 */ 881 882 /* HBR should be Non-PCM, 8 channels */ 883 #define is_hbr_format(format) \ 884 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 885 886 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 887 int dev_id, bool hbr) 888 { 889 int pinctl, new_pinctl; 890 891 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 892 snd_hda_set_dev_select(codec, pin_nid, dev_id); 893 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 894 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 895 896 if (pinctl < 0) 897 return hbr ? -EINVAL : 0; 898 899 new_pinctl = pinctl & ~AC_PINCTL_EPT; 900 if (hbr) 901 new_pinctl |= AC_PINCTL_EPT_HBR; 902 else 903 new_pinctl |= AC_PINCTL_EPT_NATIVE; 904 905 codec_dbg(codec, 906 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 907 pin_nid, 908 pinctl == new_pinctl ? "" : "new-", 909 new_pinctl); 910 911 if (pinctl != new_pinctl) 912 snd_hda_codec_write(codec, pin_nid, 0, 913 AC_VERB_SET_PIN_WIDGET_CONTROL, 914 new_pinctl); 915 } else if (hbr) 916 return -EINVAL; 917 918 return 0; 919 } 920 921 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 922 hda_nid_t pin_nid, int dev_id, 923 u32 stream_tag, int format) 924 { 925 struct hdmi_spec *spec = codec->spec; 926 unsigned int param; 927 int err; 928 929 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 930 is_hbr_format(format)); 931 932 if (err) { 933 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 934 return err; 935 } 936 937 if (spec->intel_hsw_fixup) { 938 939 /* 940 * on recent platforms IEC Coding Type is required for HBR 941 * support, read current Digital Converter settings and set 942 * ICT bitfield if needed. 943 */ 944 param = snd_hda_codec_read(codec, cvt_nid, 0, 945 AC_VERB_GET_DIGI_CONVERT_1, 0); 946 947 param = (param >> 16) & ~(AC_DIG3_ICT); 948 949 /* on recent platforms ICT mode is required for HBR support */ 950 if (is_hbr_format(format)) 951 param |= 0x1; 952 953 snd_hda_codec_write(codec, cvt_nid, 0, 954 AC_VERB_SET_DIGI_CONVERT_3, param); 955 } 956 957 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 958 return 0; 959 } 960 961 /* Try to find an available converter 962 * If pin_idx is less then zero, just try to find an available converter. 963 * Otherwise, try to find an available converter and get the cvt mux index 964 * of the pin. 965 */ 966 static int hdmi_choose_cvt(struct hda_codec *codec, 967 int pin_idx, int *cvt_id) 968 { 969 struct hdmi_spec *spec = codec->spec; 970 struct hdmi_spec_per_pin *per_pin; 971 struct hdmi_spec_per_cvt *per_cvt = NULL; 972 int cvt_idx, mux_idx = 0; 973 974 /* pin_idx < 0 means no pin will be bound to the converter */ 975 if (pin_idx < 0) 976 per_pin = NULL; 977 else 978 per_pin = get_pin(spec, pin_idx); 979 980 /* Dynamically assign converter to stream */ 981 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 982 per_cvt = get_cvt(spec, cvt_idx); 983 984 /* Must not already be assigned */ 985 if (per_cvt->assigned) 986 continue; 987 if (per_pin == NULL) 988 break; 989 /* Must be in pin's mux's list of converters */ 990 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 991 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 992 break; 993 /* Not in mux list */ 994 if (mux_idx == per_pin->num_mux_nids) 995 continue; 996 break; 997 } 998 999 /* No free converters */ 1000 if (cvt_idx == spec->num_cvts) 1001 return -EBUSY; 1002 1003 if (per_pin != NULL) 1004 per_pin->mux_idx = mux_idx; 1005 1006 if (cvt_id) 1007 *cvt_id = cvt_idx; 1008 1009 return 0; 1010 } 1011 1012 /* Assure the pin select the right convetor */ 1013 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1014 struct hdmi_spec_per_pin *per_pin) 1015 { 1016 hda_nid_t pin_nid = per_pin->pin_nid; 1017 int mux_idx, curr; 1018 1019 mux_idx = per_pin->mux_idx; 1020 curr = snd_hda_codec_read(codec, pin_nid, 0, 1021 AC_VERB_GET_CONNECT_SEL, 0); 1022 if (curr != mux_idx) 1023 snd_hda_codec_write_cache(codec, pin_nid, 0, 1024 AC_VERB_SET_CONNECT_SEL, 1025 mux_idx); 1026 } 1027 1028 /* get the mux index for the converter of the pins 1029 * converter's mux index is the same for all pins on Intel platform 1030 */ 1031 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1032 hda_nid_t cvt_nid) 1033 { 1034 int i; 1035 1036 for (i = 0; i < spec->num_cvts; i++) 1037 if (spec->cvt_nids[i] == cvt_nid) 1038 return i; 1039 return -EINVAL; 1040 } 1041 1042 /* Intel HDMI workaround to fix audio routing issue: 1043 * For some Intel display codecs, pins share the same connection list. 1044 * So a conveter can be selected by multiple pins and playback on any of these 1045 * pins will generate sound on the external display, because audio flows from 1046 * the same converter to the display pipeline. Also muting one pin may make 1047 * other pins have no sound output. 1048 * So this function assures that an assigned converter for a pin is not selected 1049 * by any other pins. 1050 */ 1051 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1052 hda_nid_t pin_nid, 1053 int dev_id, int mux_idx) 1054 { 1055 struct hdmi_spec *spec = codec->spec; 1056 hda_nid_t nid; 1057 int cvt_idx, curr; 1058 struct hdmi_spec_per_cvt *per_cvt; 1059 struct hdmi_spec_per_pin *per_pin; 1060 int pin_idx; 1061 1062 /* configure the pins connections */ 1063 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1064 int dev_id_saved; 1065 int dev_num; 1066 1067 per_pin = get_pin(spec, pin_idx); 1068 /* 1069 * pin not connected to monitor 1070 * no need to operate on it 1071 */ 1072 if (!per_pin->pcm) 1073 continue; 1074 1075 if ((per_pin->pin_nid == pin_nid) && 1076 (per_pin->dev_id == dev_id)) 1077 continue; 1078 1079 /* 1080 * if per_pin->dev_id >= dev_num, 1081 * snd_hda_get_dev_select() will fail, 1082 * and the following operation is unpredictable. 1083 * So skip this situation. 1084 */ 1085 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1086 if (per_pin->dev_id >= dev_num) 1087 continue; 1088 1089 nid = per_pin->pin_nid; 1090 1091 /* 1092 * Calling this function should not impact 1093 * on the device entry selection 1094 * So let's save the dev id for each pin, 1095 * and restore it when return 1096 */ 1097 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1098 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1099 curr = snd_hda_codec_read(codec, nid, 0, 1100 AC_VERB_GET_CONNECT_SEL, 0); 1101 if (curr != mux_idx) { 1102 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1103 continue; 1104 } 1105 1106 1107 /* choose an unassigned converter. The conveters in the 1108 * connection list are in the same order as in the codec. 1109 */ 1110 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1111 per_cvt = get_cvt(spec, cvt_idx); 1112 if (!per_cvt->assigned) { 1113 codec_dbg(codec, 1114 "choose cvt %d for pin nid %d\n", 1115 cvt_idx, nid); 1116 snd_hda_codec_write_cache(codec, nid, 0, 1117 AC_VERB_SET_CONNECT_SEL, 1118 cvt_idx); 1119 break; 1120 } 1121 } 1122 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1123 } 1124 } 1125 1126 /* A wrapper of intel_not_share_asigned_cvt() */ 1127 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1128 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1129 { 1130 int mux_idx; 1131 struct hdmi_spec *spec = codec->spec; 1132 1133 /* On Intel platform, the mapping of converter nid to 1134 * mux index of the pins are always the same. 1135 * The pin nid may be 0, this means all pins will not 1136 * share the converter. 1137 */ 1138 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1139 if (mux_idx >= 0) 1140 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1141 } 1142 1143 /* skeleton caller of pin_cvt_fixup ops */ 1144 static void pin_cvt_fixup(struct hda_codec *codec, 1145 struct hdmi_spec_per_pin *per_pin, 1146 hda_nid_t cvt_nid) 1147 { 1148 struct hdmi_spec *spec = codec->spec; 1149 1150 if (spec->ops.pin_cvt_fixup) 1151 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1152 } 1153 1154 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1155 * in dyn_pcm_assign mode. 1156 */ 1157 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1158 struct hda_codec *codec, 1159 struct snd_pcm_substream *substream) 1160 { 1161 struct hdmi_spec *spec = codec->spec; 1162 struct snd_pcm_runtime *runtime = substream->runtime; 1163 int cvt_idx, pcm_idx; 1164 struct hdmi_spec_per_cvt *per_cvt = NULL; 1165 int err; 1166 1167 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1168 if (pcm_idx < 0) 1169 return -EINVAL; 1170 1171 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1172 if (err) 1173 return err; 1174 1175 per_cvt = get_cvt(spec, cvt_idx); 1176 per_cvt->assigned = 1; 1177 hinfo->nid = per_cvt->cvt_nid; 1178 1179 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1180 1181 set_bit(pcm_idx, &spec->pcm_in_use); 1182 /* todo: setup spdif ctls assign */ 1183 1184 /* Initially set the converter's capabilities */ 1185 hinfo->channels_min = per_cvt->channels_min; 1186 hinfo->channels_max = per_cvt->channels_max; 1187 hinfo->rates = per_cvt->rates; 1188 hinfo->formats = per_cvt->formats; 1189 hinfo->maxbps = per_cvt->maxbps; 1190 1191 /* Store the updated parameters */ 1192 runtime->hw.channels_min = hinfo->channels_min; 1193 runtime->hw.channels_max = hinfo->channels_max; 1194 runtime->hw.formats = hinfo->formats; 1195 runtime->hw.rates = hinfo->rates; 1196 1197 snd_pcm_hw_constraint_step(substream->runtime, 0, 1198 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1199 return 0; 1200 } 1201 1202 /* 1203 * HDA PCM callbacks 1204 */ 1205 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1206 struct hda_codec *codec, 1207 struct snd_pcm_substream *substream) 1208 { 1209 struct hdmi_spec *spec = codec->spec; 1210 struct snd_pcm_runtime *runtime = substream->runtime; 1211 int pin_idx, cvt_idx, pcm_idx; 1212 struct hdmi_spec_per_pin *per_pin; 1213 struct hdmi_eld *eld; 1214 struct hdmi_spec_per_cvt *per_cvt = NULL; 1215 int err; 1216 1217 /* Validate hinfo */ 1218 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1219 if (pcm_idx < 0) 1220 return -EINVAL; 1221 1222 mutex_lock(&spec->pcm_lock); 1223 pin_idx = hinfo_to_pin_index(codec, hinfo); 1224 if (!spec->dyn_pcm_assign) { 1225 if (snd_BUG_ON(pin_idx < 0)) { 1226 err = -EINVAL; 1227 goto unlock; 1228 } 1229 } else { 1230 /* no pin is assigned to the PCM 1231 * PA need pcm open successfully when probe 1232 */ 1233 if (pin_idx < 0) { 1234 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1235 goto unlock; 1236 } 1237 } 1238 1239 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1240 if (err < 0) 1241 goto unlock; 1242 1243 per_cvt = get_cvt(spec, cvt_idx); 1244 /* Claim converter */ 1245 per_cvt->assigned = 1; 1246 1247 set_bit(pcm_idx, &spec->pcm_in_use); 1248 per_pin = get_pin(spec, pin_idx); 1249 per_pin->cvt_nid = per_cvt->cvt_nid; 1250 hinfo->nid = per_cvt->cvt_nid; 1251 1252 /* flip stripe flag for the assigned stream if supported */ 1253 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1254 azx_stream(get_azx_dev(substream))->stripe = 1; 1255 1256 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1257 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1258 AC_VERB_SET_CONNECT_SEL, 1259 per_pin->mux_idx); 1260 1261 /* configure unused pins to choose other converters */ 1262 pin_cvt_fixup(codec, per_pin, 0); 1263 1264 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1265 1266 /* Initially set the converter's capabilities */ 1267 hinfo->channels_min = per_cvt->channels_min; 1268 hinfo->channels_max = per_cvt->channels_max; 1269 hinfo->rates = per_cvt->rates; 1270 hinfo->formats = per_cvt->formats; 1271 hinfo->maxbps = per_cvt->maxbps; 1272 1273 eld = &per_pin->sink_eld; 1274 /* Restrict capabilities by ELD if this isn't disabled */ 1275 if (!static_hdmi_pcm && eld->eld_valid) { 1276 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1277 if (hinfo->channels_min > hinfo->channels_max || 1278 !hinfo->rates || !hinfo->formats) { 1279 per_cvt->assigned = 0; 1280 hinfo->nid = 0; 1281 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1282 err = -ENODEV; 1283 goto unlock; 1284 } 1285 } 1286 1287 /* Store the updated parameters */ 1288 runtime->hw.channels_min = hinfo->channels_min; 1289 runtime->hw.channels_max = hinfo->channels_max; 1290 runtime->hw.formats = hinfo->formats; 1291 runtime->hw.rates = hinfo->rates; 1292 1293 snd_pcm_hw_constraint_step(substream->runtime, 0, 1294 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1295 unlock: 1296 mutex_unlock(&spec->pcm_lock); 1297 return err; 1298 } 1299 1300 /* 1301 * HDA/HDMI auto parsing 1302 */ 1303 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1304 { 1305 struct hdmi_spec *spec = codec->spec; 1306 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1307 hda_nid_t pin_nid = per_pin->pin_nid; 1308 int dev_id = per_pin->dev_id; 1309 int conns; 1310 1311 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1312 codec_warn(codec, 1313 "HDMI: pin %d wcaps %#x does not support connection list\n", 1314 pin_nid, get_wcaps(codec, pin_nid)); 1315 return -EINVAL; 1316 } 1317 1318 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1319 1320 if (spec->intel_hsw_fixup) { 1321 conns = spec->num_cvts; 1322 memcpy(per_pin->mux_nids, spec->cvt_nids, 1323 sizeof(hda_nid_t) * conns); 1324 } else { 1325 conns = snd_hda_get_raw_connections(codec, pin_nid, 1326 per_pin->mux_nids, 1327 HDA_MAX_CONNECTIONS); 1328 } 1329 1330 /* all the device entries on the same pin have the same conn list */ 1331 per_pin->num_mux_nids = conns; 1332 1333 return 0; 1334 } 1335 1336 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1337 struct hdmi_spec_per_pin *per_pin) 1338 { 1339 int i; 1340 1341 /* 1342 * generic_hdmi_build_pcms() may allocate extra PCMs on some 1343 * platforms (with maximum of 'num_nids + dev_num - 1') 1344 * 1345 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n 1346 * if m==0. This guarantees that dynamic pcm assignments are compatible 1347 * with the legacy static per_pin-pcm assignment that existed in the 1348 * days before DP-MST. 1349 * 1350 * Intel DP-MST prefers this legacy behavior for compatibility, too. 1351 * 1352 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). 1353 */ 1354 1355 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { 1356 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1357 return per_pin->pin_nid_idx; 1358 } else { 1359 i = spec->num_nids + (per_pin->dev_id - 1); 1360 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) 1361 return i; 1362 } 1363 1364 /* have a second try; check the area over num_nids */ 1365 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1366 if (!test_bit(i, &spec->pcm_bitmap)) 1367 return i; 1368 } 1369 1370 /* the last try; check the empty slots in pins */ 1371 for (i = 0; i < spec->num_nids; i++) { 1372 if (!test_bit(i, &spec->pcm_bitmap)) 1373 return i; 1374 } 1375 return -EBUSY; 1376 } 1377 1378 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1379 struct hdmi_spec_per_pin *per_pin) 1380 { 1381 int idx; 1382 1383 /* pcm already be attached to the pin */ 1384 if (per_pin->pcm) 1385 return; 1386 idx = hdmi_find_pcm_slot(spec, per_pin); 1387 if (idx == -EBUSY) 1388 return; 1389 per_pin->pcm_idx = idx; 1390 per_pin->pcm = get_hdmi_pcm(spec, idx); 1391 set_bit(idx, &spec->pcm_bitmap); 1392 } 1393 1394 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1395 struct hdmi_spec_per_pin *per_pin) 1396 { 1397 int idx; 1398 1399 /* pcm already be detached from the pin */ 1400 if (!per_pin->pcm) 1401 return; 1402 idx = per_pin->pcm_idx; 1403 per_pin->pcm_idx = -1; 1404 per_pin->pcm = NULL; 1405 if (idx >= 0 && idx < spec->pcm_used) 1406 clear_bit(idx, &spec->pcm_bitmap); 1407 } 1408 1409 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1410 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1411 { 1412 int mux_idx; 1413 1414 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1415 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1416 break; 1417 return mux_idx; 1418 } 1419 1420 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1421 1422 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1423 struct hdmi_spec_per_pin *per_pin) 1424 { 1425 struct hda_codec *codec = per_pin->codec; 1426 struct hda_pcm *pcm; 1427 struct hda_pcm_stream *hinfo; 1428 struct snd_pcm_substream *substream; 1429 int mux_idx; 1430 bool non_pcm; 1431 1432 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1433 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1434 else 1435 return; 1436 if (!pcm->pcm) 1437 return; 1438 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1439 return; 1440 1441 /* hdmi audio only uses playback and one substream */ 1442 hinfo = pcm->stream; 1443 substream = pcm->pcm->streams[0].substream; 1444 1445 per_pin->cvt_nid = hinfo->nid; 1446 1447 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1448 if (mux_idx < per_pin->num_mux_nids) { 1449 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1450 per_pin->dev_id); 1451 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1452 AC_VERB_SET_CONNECT_SEL, 1453 mux_idx); 1454 } 1455 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1456 1457 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1458 if (substream->runtime) 1459 per_pin->channels = substream->runtime->channels; 1460 per_pin->setup = true; 1461 per_pin->mux_idx = mux_idx; 1462 1463 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1464 } 1465 1466 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1467 struct hdmi_spec_per_pin *per_pin) 1468 { 1469 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1470 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1471 1472 per_pin->chmap_set = false; 1473 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1474 1475 per_pin->setup = false; 1476 per_pin->channels = 0; 1477 } 1478 1479 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1480 struct hdmi_spec_per_pin *per_pin) 1481 { 1482 struct hdmi_spec *spec = codec->spec; 1483 1484 if (per_pin->pcm_idx >= 0) 1485 return spec->pcm_rec[per_pin->pcm_idx].jack; 1486 else 1487 return NULL; 1488 } 1489 1490 /* update per_pin ELD from the given new ELD; 1491 * setup info frame and notification accordingly 1492 * also notify ELD kctl and report jack status changes 1493 */ 1494 static void update_eld(struct hda_codec *codec, 1495 struct hdmi_spec_per_pin *per_pin, 1496 struct hdmi_eld *eld, 1497 int repoll) 1498 { 1499 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1500 struct hdmi_spec *spec = codec->spec; 1501 struct snd_jack *pcm_jack; 1502 bool old_eld_valid = pin_eld->eld_valid; 1503 bool eld_changed; 1504 int pcm_idx; 1505 1506 if (eld->eld_valid) { 1507 if (eld->eld_size <= 0 || 1508 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1509 eld->eld_size) < 0) { 1510 eld->eld_valid = false; 1511 if (repoll) { 1512 schedule_delayed_work(&per_pin->work, 1513 msecs_to_jiffies(300)); 1514 return; 1515 } 1516 } 1517 } 1518 1519 if (!eld->eld_valid || eld->eld_size <= 0) { 1520 eld->eld_valid = false; 1521 eld->eld_size = 0; 1522 } 1523 1524 /* for monitor disconnection, save pcm_idx firstly */ 1525 pcm_idx = per_pin->pcm_idx; 1526 1527 /* 1528 * pcm_idx >=0 before update_eld() means it is in monitor 1529 * disconnected event. Jack must be fetched before update_eld(). 1530 */ 1531 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1532 1533 if (spec->dyn_pcm_assign) { 1534 if (eld->eld_valid) { 1535 hdmi_attach_hda_pcm(spec, per_pin); 1536 hdmi_pcm_setup_pin(spec, per_pin); 1537 } else { 1538 hdmi_pcm_reset_pin(spec, per_pin); 1539 hdmi_detach_hda_pcm(spec, per_pin); 1540 } 1541 } 1542 /* if pcm_idx == -1, it means this is in monitor connection event 1543 * we can get the correct pcm_idx now. 1544 */ 1545 if (pcm_idx == -1) 1546 pcm_idx = per_pin->pcm_idx; 1547 if (!pcm_jack) 1548 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1549 1550 if (eld->eld_valid) 1551 snd_hdmi_show_eld(codec, &eld->info); 1552 1553 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1554 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1555 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1556 if (pin_eld->eld_size != eld->eld_size || 1557 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1558 eld->eld_size) != 0) 1559 eld_changed = true; 1560 1561 if (eld_changed) { 1562 pin_eld->monitor_present = eld->monitor_present; 1563 pin_eld->eld_valid = eld->eld_valid; 1564 pin_eld->eld_size = eld->eld_size; 1565 if (eld->eld_valid) 1566 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1567 eld->eld_size); 1568 pin_eld->info = eld->info; 1569 } 1570 1571 /* 1572 * Re-setup pin and infoframe. This is needed e.g. when 1573 * - sink is first plugged-in 1574 * - transcoder can change during stream playback on Haswell 1575 * and this can make HW reset converter selection on a pin. 1576 */ 1577 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1578 pin_cvt_fixup(codec, per_pin, 0); 1579 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1580 } 1581 1582 if (eld_changed && pcm_idx >= 0) 1583 snd_ctl_notify(codec->card, 1584 SNDRV_CTL_EVENT_MASK_VALUE | 1585 SNDRV_CTL_EVENT_MASK_INFO, 1586 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1587 1588 if (eld_changed && pcm_jack) 1589 snd_jack_report(pcm_jack, 1590 (eld->monitor_present && eld->eld_valid) ? 1591 SND_JACK_AVOUT : 0); 1592 } 1593 1594 /* update ELD and jack state via HD-audio verbs */ 1595 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1596 int repoll) 1597 { 1598 struct hda_codec *codec = per_pin->codec; 1599 struct hdmi_spec *spec = codec->spec; 1600 struct hdmi_eld *eld = &spec->temp_eld; 1601 hda_nid_t pin_nid = per_pin->pin_nid; 1602 int dev_id = per_pin->dev_id; 1603 /* 1604 * Always execute a GetPinSense verb here, even when called from 1605 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1606 * response's PD bit is not the real PD value, but indicates that 1607 * the real PD value changed. An older version of the HD-audio 1608 * specification worked this way. Hence, we just ignore the data in 1609 * the unsolicited response to avoid custom WARs. 1610 */ 1611 int present; 1612 int ret; 1613 1614 ret = snd_hda_power_up_pm(codec); 1615 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) 1616 goto out; 1617 1618 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1619 1620 mutex_lock(&per_pin->lock); 1621 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1622 if (eld->monitor_present) 1623 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1624 else 1625 eld->eld_valid = false; 1626 1627 codec_dbg(codec, 1628 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1629 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1630 1631 if (eld->eld_valid) { 1632 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1633 eld->eld_buffer, &eld->eld_size) < 0) 1634 eld->eld_valid = false; 1635 } 1636 1637 update_eld(codec, per_pin, eld, repoll); 1638 mutex_unlock(&per_pin->lock); 1639 out: 1640 snd_hda_power_down_pm(codec); 1641 } 1642 1643 static void silent_stream_enable(struct hda_codec *codec, 1644 struct hdmi_spec_per_pin *per_pin) 1645 { 1646 unsigned int newval, oldval; 1647 1648 codec_dbg(codec, "hdmi: enabling silent stream for NID %d\n", 1649 per_pin->pin_nid); 1650 1651 mutex_lock(&per_pin->lock); 1652 1653 if (!per_pin->channels) 1654 per_pin->channels = 2; 1655 1656 oldval = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1657 AC_VERB_GET_CONV, 0); 1658 newval = (oldval & 0xF0) | 0xF; 1659 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1660 AC_VERB_SET_CHANNEL_STREAMID, newval); 1661 1662 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1663 1664 mutex_unlock(&per_pin->lock); 1665 } 1666 1667 /* update ELD and jack state via audio component */ 1668 static void sync_eld_via_acomp(struct hda_codec *codec, 1669 struct hdmi_spec_per_pin *per_pin) 1670 { 1671 struct hdmi_spec *spec = codec->spec; 1672 struct hdmi_eld *eld = &spec->temp_eld; 1673 bool monitor_prev, monitor_next; 1674 1675 mutex_lock(&per_pin->lock); 1676 eld->monitor_present = false; 1677 monitor_prev = per_pin->sink_eld.monitor_present; 1678 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1679 per_pin->dev_id, &eld->monitor_present, 1680 eld->eld_buffer, ELD_MAX_SIZE); 1681 eld->eld_valid = (eld->eld_size > 0); 1682 update_eld(codec, per_pin, eld, 0); 1683 monitor_next = per_pin->sink_eld.monitor_present; 1684 mutex_unlock(&per_pin->lock); 1685 1686 /* 1687 * Power-up will call hdmi_present_sense, so the PM calls 1688 * have to be done without mutex held. 1689 */ 1690 1691 if (spec->send_silent_stream) { 1692 int pm_ret; 1693 1694 if (!monitor_prev && monitor_next) { 1695 pm_ret = snd_hda_power_up_pm(codec); 1696 if (pm_ret < 0) 1697 codec_err(codec, 1698 "Monitor plugged-in, Failed to power up codec ret=[%d]\n", 1699 pm_ret); 1700 silent_stream_enable(codec, per_pin); 1701 } else if (monitor_prev && !monitor_next) { 1702 pm_ret = snd_hda_power_down_pm(codec); 1703 if (pm_ret < 0) 1704 codec_err(codec, 1705 "Monitor plugged-out, Failed to power down codec ret=[%d]\n", 1706 pm_ret); 1707 } 1708 } 1709 } 1710 1711 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1712 { 1713 struct hda_codec *codec = per_pin->codec; 1714 1715 if (!codec_has_acomp(codec)) 1716 hdmi_present_sense_via_verbs(per_pin, repoll); 1717 else 1718 sync_eld_via_acomp(codec, per_pin); 1719 } 1720 1721 static void hdmi_repoll_eld(struct work_struct *work) 1722 { 1723 struct hdmi_spec_per_pin *per_pin = 1724 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1725 struct hda_codec *codec = per_pin->codec; 1726 struct hdmi_spec *spec = codec->spec; 1727 struct hda_jack_tbl *jack; 1728 1729 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1730 per_pin->dev_id); 1731 if (jack) 1732 jack->jack_dirty = 1; 1733 1734 if (per_pin->repoll_count++ > 6) 1735 per_pin->repoll_count = 0; 1736 1737 mutex_lock(&spec->pcm_lock); 1738 hdmi_present_sense(per_pin, per_pin->repoll_count); 1739 mutex_unlock(&spec->pcm_lock); 1740 } 1741 1742 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1743 { 1744 struct hdmi_spec *spec = codec->spec; 1745 unsigned int caps, config; 1746 int pin_idx; 1747 struct hdmi_spec_per_pin *per_pin; 1748 int err; 1749 int dev_num, i; 1750 1751 caps = snd_hda_query_pin_caps(codec, pin_nid); 1752 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1753 return 0; 1754 1755 /* 1756 * For DP MST audio, Configuration Default is the same for 1757 * all device entries on the same pin 1758 */ 1759 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1760 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1761 return 0; 1762 1763 /* 1764 * To simplify the implementation, malloc all 1765 * the virtual pins in the initialization statically 1766 */ 1767 if (spec->intel_hsw_fixup) { 1768 /* 1769 * On Intel platforms, device entries number is 1770 * changed dynamically. If there is a DP MST 1771 * hub connected, the device entries number is 3. 1772 * Otherwise, it is 1. 1773 * Here we manually set dev_num to 3, so that 1774 * we can initialize all the device entries when 1775 * bootup statically. 1776 */ 1777 dev_num = 3; 1778 spec->dev_num = 3; 1779 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1780 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1781 /* 1782 * spec->dev_num is the maxinum number of device entries 1783 * among all the pins 1784 */ 1785 spec->dev_num = (spec->dev_num > dev_num) ? 1786 spec->dev_num : dev_num; 1787 } else { 1788 /* 1789 * If the platform doesn't support DP MST, 1790 * manually set dev_num to 1. This means 1791 * the pin has only one device entry. 1792 */ 1793 dev_num = 1; 1794 spec->dev_num = 1; 1795 } 1796 1797 for (i = 0; i < dev_num; i++) { 1798 pin_idx = spec->num_pins; 1799 per_pin = snd_array_new(&spec->pins); 1800 1801 if (!per_pin) 1802 return -ENOMEM; 1803 1804 if (spec->dyn_pcm_assign) { 1805 per_pin->pcm = NULL; 1806 per_pin->pcm_idx = -1; 1807 } else { 1808 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1809 per_pin->pcm_idx = pin_idx; 1810 } 1811 per_pin->pin_nid = pin_nid; 1812 per_pin->pin_nid_idx = spec->num_nids; 1813 per_pin->dev_id = i; 1814 per_pin->non_pcm = false; 1815 snd_hda_set_dev_select(codec, pin_nid, i); 1816 err = hdmi_read_pin_conn(codec, pin_idx); 1817 if (err < 0) 1818 return err; 1819 spec->num_pins++; 1820 } 1821 spec->num_nids++; 1822 1823 return 0; 1824 } 1825 1826 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1827 { 1828 struct hdmi_spec *spec = codec->spec; 1829 struct hdmi_spec_per_cvt *per_cvt; 1830 unsigned int chans; 1831 int err; 1832 1833 chans = get_wcaps(codec, cvt_nid); 1834 chans = get_wcaps_channels(chans); 1835 1836 per_cvt = snd_array_new(&spec->cvts); 1837 if (!per_cvt) 1838 return -ENOMEM; 1839 1840 per_cvt->cvt_nid = cvt_nid; 1841 per_cvt->channels_min = 2; 1842 if (chans <= 16) { 1843 per_cvt->channels_max = chans; 1844 if (chans > spec->chmap.channels_max) 1845 spec->chmap.channels_max = chans; 1846 } 1847 1848 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1849 &per_cvt->rates, 1850 &per_cvt->formats, 1851 &per_cvt->maxbps); 1852 if (err < 0) 1853 return err; 1854 1855 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1856 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1857 spec->num_cvts++; 1858 1859 return 0; 1860 } 1861 1862 static int hdmi_parse_codec(struct hda_codec *codec) 1863 { 1864 hda_nid_t nid; 1865 int i, nodes; 1866 1867 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1868 if (!nid || nodes < 0) { 1869 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1870 return -EINVAL; 1871 } 1872 1873 for (i = 0; i < nodes; i++, nid++) { 1874 unsigned int caps; 1875 unsigned int type; 1876 1877 caps = get_wcaps(codec, nid); 1878 type = get_wcaps_type(caps); 1879 1880 if (!(caps & AC_WCAP_DIGITAL)) 1881 continue; 1882 1883 switch (type) { 1884 case AC_WID_AUD_OUT: 1885 hdmi_add_cvt(codec, nid); 1886 break; 1887 case AC_WID_PIN: 1888 hdmi_add_pin(codec, nid); 1889 break; 1890 } 1891 } 1892 1893 return 0; 1894 } 1895 1896 /* 1897 */ 1898 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1899 { 1900 struct hda_spdif_out *spdif; 1901 bool non_pcm; 1902 1903 mutex_lock(&codec->spdif_mutex); 1904 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1905 /* Add sanity check to pass klockwork check. 1906 * This should never happen. 1907 */ 1908 if (WARN_ON(spdif == NULL)) { 1909 mutex_unlock(&codec->spdif_mutex); 1910 return true; 1911 } 1912 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1913 mutex_unlock(&codec->spdif_mutex); 1914 return non_pcm; 1915 } 1916 1917 /* 1918 * HDMI callbacks 1919 */ 1920 1921 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1922 struct hda_codec *codec, 1923 unsigned int stream_tag, 1924 unsigned int format, 1925 struct snd_pcm_substream *substream) 1926 { 1927 hda_nid_t cvt_nid = hinfo->nid; 1928 struct hdmi_spec *spec = codec->spec; 1929 int pin_idx; 1930 struct hdmi_spec_per_pin *per_pin; 1931 struct snd_pcm_runtime *runtime = substream->runtime; 1932 bool non_pcm; 1933 int pinctl, stripe; 1934 int err = 0; 1935 1936 mutex_lock(&spec->pcm_lock); 1937 pin_idx = hinfo_to_pin_index(codec, hinfo); 1938 if (spec->dyn_pcm_assign && pin_idx < 0) { 1939 /* when dyn_pcm_assign and pcm is not bound to a pin 1940 * skip pin setup and return 0 to make audio playback 1941 * be ongoing 1942 */ 1943 pin_cvt_fixup(codec, NULL, cvt_nid); 1944 snd_hda_codec_setup_stream(codec, cvt_nid, 1945 stream_tag, 0, format); 1946 goto unlock; 1947 } 1948 1949 if (snd_BUG_ON(pin_idx < 0)) { 1950 err = -EINVAL; 1951 goto unlock; 1952 } 1953 per_pin = get_pin(spec, pin_idx); 1954 1955 /* Verify pin:cvt selections to avoid silent audio after S3. 1956 * After S3, the audio driver restores pin:cvt selections 1957 * but this can happen before gfx is ready and such selection 1958 * is overlooked by HW. Thus multiple pins can share a same 1959 * default convertor and mute control will affect each other, 1960 * which can cause a resumed audio playback become silent 1961 * after S3. 1962 */ 1963 pin_cvt_fixup(codec, per_pin, 0); 1964 1965 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1966 /* Todo: add DP1.2 MST audio support later */ 1967 if (codec_has_acomp(codec)) 1968 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1969 per_pin->dev_id, runtime->rate); 1970 1971 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1972 mutex_lock(&per_pin->lock); 1973 per_pin->channels = substream->runtime->channels; 1974 per_pin->setup = true; 1975 1976 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 1977 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 1978 substream); 1979 snd_hda_codec_write(codec, cvt_nid, 0, 1980 AC_VERB_SET_STRIPE_CONTROL, 1981 stripe); 1982 } 1983 1984 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1985 mutex_unlock(&per_pin->lock); 1986 if (spec->dyn_pin_out) { 1987 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1988 per_pin->dev_id); 1989 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1990 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1991 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1992 AC_VERB_SET_PIN_WIDGET_CONTROL, 1993 pinctl | PIN_OUT); 1994 } 1995 1996 /* snd_hda_set_dev_select() has been called before */ 1997 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 1998 per_pin->dev_id, stream_tag, format); 1999 unlock: 2000 mutex_unlock(&spec->pcm_lock); 2001 return err; 2002 } 2003 2004 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2005 struct hda_codec *codec, 2006 struct snd_pcm_substream *substream) 2007 { 2008 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2009 return 0; 2010 } 2011 2012 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2013 struct hda_codec *codec, 2014 struct snd_pcm_substream *substream) 2015 { 2016 struct hdmi_spec *spec = codec->spec; 2017 int cvt_idx, pin_idx, pcm_idx; 2018 struct hdmi_spec_per_cvt *per_cvt; 2019 struct hdmi_spec_per_pin *per_pin; 2020 int pinctl; 2021 int err = 0; 2022 2023 if (hinfo->nid) { 2024 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2025 if (snd_BUG_ON(pcm_idx < 0)) 2026 return -EINVAL; 2027 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2028 if (snd_BUG_ON(cvt_idx < 0)) 2029 return -EINVAL; 2030 per_cvt = get_cvt(spec, cvt_idx); 2031 2032 snd_BUG_ON(!per_cvt->assigned); 2033 per_cvt->assigned = 0; 2034 hinfo->nid = 0; 2035 2036 azx_stream(get_azx_dev(substream))->stripe = 0; 2037 2038 mutex_lock(&spec->pcm_lock); 2039 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2040 clear_bit(pcm_idx, &spec->pcm_in_use); 2041 pin_idx = hinfo_to_pin_index(codec, hinfo); 2042 if (spec->dyn_pcm_assign && pin_idx < 0) 2043 goto unlock; 2044 2045 if (snd_BUG_ON(pin_idx < 0)) { 2046 err = -EINVAL; 2047 goto unlock; 2048 } 2049 per_pin = get_pin(spec, pin_idx); 2050 2051 if (spec->dyn_pin_out) { 2052 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2053 per_pin->dev_id); 2054 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2055 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2056 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2057 AC_VERB_SET_PIN_WIDGET_CONTROL, 2058 pinctl & ~PIN_OUT); 2059 } 2060 2061 mutex_lock(&per_pin->lock); 2062 per_pin->chmap_set = false; 2063 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2064 2065 per_pin->setup = false; 2066 per_pin->channels = 0; 2067 mutex_unlock(&per_pin->lock); 2068 unlock: 2069 mutex_unlock(&spec->pcm_lock); 2070 } 2071 2072 return err; 2073 } 2074 2075 static const struct hda_pcm_ops generic_ops = { 2076 .open = hdmi_pcm_open, 2077 .close = hdmi_pcm_close, 2078 .prepare = generic_hdmi_playback_pcm_prepare, 2079 .cleanup = generic_hdmi_playback_pcm_cleanup, 2080 }; 2081 2082 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2083 { 2084 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2085 struct hdmi_spec *spec = codec->spec; 2086 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2087 2088 if (!per_pin) 2089 return 0; 2090 2091 return per_pin->sink_eld.info.spk_alloc; 2092 } 2093 2094 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2095 unsigned char *chmap) 2096 { 2097 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2098 struct hdmi_spec *spec = codec->spec; 2099 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2100 2101 /* chmap is already set to 0 in caller */ 2102 if (!per_pin) 2103 return; 2104 2105 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2106 } 2107 2108 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2109 unsigned char *chmap, int prepared) 2110 { 2111 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2112 struct hdmi_spec *spec = codec->spec; 2113 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2114 2115 if (!per_pin) 2116 return; 2117 mutex_lock(&per_pin->lock); 2118 per_pin->chmap_set = true; 2119 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2120 if (prepared) 2121 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2122 mutex_unlock(&per_pin->lock); 2123 } 2124 2125 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2126 { 2127 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2128 struct hdmi_spec *spec = codec->spec; 2129 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2130 2131 return per_pin ? true:false; 2132 } 2133 2134 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2135 { 2136 struct hdmi_spec *spec = codec->spec; 2137 int idx, pcm_num; 2138 2139 /* 2140 * for non-mst mode, pcm number is the same as before 2141 * for DP MST mode without extra PCM, pcm number is same 2142 * for DP MST mode with extra PCMs, pcm number is 2143 * (nid number + dev_num - 1) 2144 * dev_num is the device entry number in a pin 2145 */ 2146 2147 if (codec->mst_no_extra_pcms) 2148 pcm_num = spec->num_nids; 2149 else 2150 pcm_num = spec->num_nids + spec->dev_num - 1; 2151 2152 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2153 2154 for (idx = 0; idx < pcm_num; idx++) { 2155 struct hda_pcm *info; 2156 struct hda_pcm_stream *pstr; 2157 2158 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2159 if (!info) 2160 return -ENOMEM; 2161 2162 spec->pcm_rec[idx].pcm = info; 2163 spec->pcm_used++; 2164 info->pcm_type = HDA_PCM_TYPE_HDMI; 2165 info->own_chmap = true; 2166 2167 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2168 pstr->substreams = 1; 2169 pstr->ops = generic_ops; 2170 /* pcm number is less than 16 */ 2171 if (spec->pcm_used >= 16) 2172 break; 2173 /* other pstr fields are set in open */ 2174 } 2175 2176 return 0; 2177 } 2178 2179 static void free_hdmi_jack_priv(struct snd_jack *jack) 2180 { 2181 struct hdmi_pcm *pcm = jack->private_data; 2182 2183 pcm->jack = NULL; 2184 } 2185 2186 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2187 { 2188 char hdmi_str[32] = "HDMI/DP"; 2189 struct hdmi_spec *spec = codec->spec; 2190 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx); 2191 struct snd_jack *jack; 2192 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2193 int err; 2194 2195 if (pcmdev > 0) 2196 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2197 if (!spec->dyn_pcm_assign && 2198 !is_jack_detectable(codec, per_pin->pin_nid)) 2199 strncat(hdmi_str, " Phantom", 2200 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2201 2202 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2203 true, false); 2204 if (err < 0) 2205 return err; 2206 2207 spec->pcm_rec[pcm_idx].jack = jack; 2208 jack->private_data = &spec->pcm_rec[pcm_idx]; 2209 jack->private_free = free_hdmi_jack_priv; 2210 return 0; 2211 } 2212 2213 static int generic_hdmi_build_controls(struct hda_codec *codec) 2214 { 2215 struct hdmi_spec *spec = codec->spec; 2216 int dev, err; 2217 int pin_idx, pcm_idx; 2218 2219 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2220 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2221 /* no PCM: mark this for skipping permanently */ 2222 set_bit(pcm_idx, &spec->pcm_bitmap); 2223 continue; 2224 } 2225 2226 err = generic_hdmi_build_jack(codec, pcm_idx); 2227 if (err < 0) 2228 return err; 2229 2230 /* create the spdif for each pcm 2231 * pin will be bound when monitor is connected 2232 */ 2233 if (spec->dyn_pcm_assign) 2234 err = snd_hda_create_dig_out_ctls(codec, 2235 0, spec->cvt_nids[0], 2236 HDA_PCM_TYPE_HDMI); 2237 else { 2238 struct hdmi_spec_per_pin *per_pin = 2239 get_pin(spec, pcm_idx); 2240 err = snd_hda_create_dig_out_ctls(codec, 2241 per_pin->pin_nid, 2242 per_pin->mux_nids[0], 2243 HDA_PCM_TYPE_HDMI); 2244 } 2245 if (err < 0) 2246 return err; 2247 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2248 2249 dev = get_pcm_rec(spec, pcm_idx)->device; 2250 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2251 /* add control for ELD Bytes */ 2252 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2253 if (err < 0) 2254 return err; 2255 } 2256 } 2257 2258 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2259 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2260 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2261 2262 pin_eld->eld_valid = false; 2263 hdmi_present_sense(per_pin, 0); 2264 } 2265 2266 /* add channel maps */ 2267 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2268 struct hda_pcm *pcm; 2269 2270 pcm = get_pcm_rec(spec, pcm_idx); 2271 if (!pcm || !pcm->pcm) 2272 break; 2273 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2274 if (err < 0) 2275 return err; 2276 } 2277 2278 return 0; 2279 } 2280 2281 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2282 { 2283 struct hdmi_spec *spec = codec->spec; 2284 int pin_idx; 2285 2286 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2287 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2288 2289 per_pin->codec = codec; 2290 mutex_init(&per_pin->lock); 2291 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2292 eld_proc_new(per_pin, pin_idx); 2293 } 2294 return 0; 2295 } 2296 2297 static int generic_hdmi_init(struct hda_codec *codec) 2298 { 2299 struct hdmi_spec *spec = codec->spec; 2300 int pin_idx; 2301 2302 mutex_lock(&spec->bind_lock); 2303 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2304 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2305 hda_nid_t pin_nid = per_pin->pin_nid; 2306 int dev_id = per_pin->dev_id; 2307 2308 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2309 hdmi_init_pin(codec, pin_nid); 2310 if (codec_has_acomp(codec)) 2311 continue; 2312 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2313 jack_callback); 2314 } 2315 mutex_unlock(&spec->bind_lock); 2316 return 0; 2317 } 2318 2319 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2320 { 2321 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2322 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2323 } 2324 2325 static void hdmi_array_free(struct hdmi_spec *spec) 2326 { 2327 snd_array_free(&spec->pins); 2328 snd_array_free(&spec->cvts); 2329 } 2330 2331 static void generic_spec_free(struct hda_codec *codec) 2332 { 2333 struct hdmi_spec *spec = codec->spec; 2334 2335 if (spec) { 2336 hdmi_array_free(spec); 2337 kfree(spec); 2338 codec->spec = NULL; 2339 } 2340 codec->dp_mst = false; 2341 } 2342 2343 static void generic_hdmi_free(struct hda_codec *codec) 2344 { 2345 struct hdmi_spec *spec = codec->spec; 2346 int pin_idx, pcm_idx; 2347 2348 if (spec->acomp_registered) { 2349 snd_hdac_acomp_exit(&codec->bus->core); 2350 } else if (codec_has_acomp(codec)) { 2351 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2352 } 2353 codec->relaxed_resume = 0; 2354 2355 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2356 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2357 cancel_delayed_work_sync(&per_pin->work); 2358 eld_proc_free(per_pin); 2359 } 2360 2361 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2362 if (spec->pcm_rec[pcm_idx].jack == NULL) 2363 continue; 2364 if (spec->dyn_pcm_assign) 2365 snd_device_free(codec->card, 2366 spec->pcm_rec[pcm_idx].jack); 2367 else 2368 spec->pcm_rec[pcm_idx].jack = NULL; 2369 } 2370 2371 generic_spec_free(codec); 2372 } 2373 2374 #ifdef CONFIG_PM 2375 static int generic_hdmi_resume(struct hda_codec *codec) 2376 { 2377 struct hdmi_spec *spec = codec->spec; 2378 int pin_idx; 2379 2380 codec->patch_ops.init(codec); 2381 snd_hda_regmap_sync(codec); 2382 2383 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2384 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2385 hdmi_present_sense(per_pin, 1); 2386 } 2387 return 0; 2388 } 2389 #endif 2390 2391 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2392 .init = generic_hdmi_init, 2393 .free = generic_hdmi_free, 2394 .build_pcms = generic_hdmi_build_pcms, 2395 .build_controls = generic_hdmi_build_controls, 2396 .unsol_event = hdmi_unsol_event, 2397 #ifdef CONFIG_PM 2398 .resume = generic_hdmi_resume, 2399 #endif 2400 }; 2401 2402 static const struct hdmi_ops generic_standard_hdmi_ops = { 2403 .pin_get_eld = hdmi_pin_get_eld, 2404 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2405 .pin_hbr_setup = hdmi_pin_hbr_setup, 2406 .setup_stream = hdmi_setup_stream, 2407 }; 2408 2409 /* allocate codec->spec and assign/initialize generic parser ops */ 2410 static int alloc_generic_hdmi(struct hda_codec *codec) 2411 { 2412 struct hdmi_spec *spec; 2413 2414 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2415 if (!spec) 2416 return -ENOMEM; 2417 2418 spec->codec = codec; 2419 spec->ops = generic_standard_hdmi_ops; 2420 spec->dev_num = 1; /* initialize to 1 */ 2421 mutex_init(&spec->pcm_lock); 2422 mutex_init(&spec->bind_lock); 2423 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2424 2425 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2426 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2427 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2428 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2429 2430 codec->spec = spec; 2431 hdmi_array_init(spec, 4); 2432 2433 codec->patch_ops = generic_hdmi_patch_ops; 2434 2435 return 0; 2436 } 2437 2438 /* generic HDMI parser */ 2439 static int patch_generic_hdmi(struct hda_codec *codec) 2440 { 2441 int err; 2442 2443 err = alloc_generic_hdmi(codec); 2444 if (err < 0) 2445 return err; 2446 2447 err = hdmi_parse_codec(codec); 2448 if (err < 0) { 2449 generic_spec_free(codec); 2450 return err; 2451 } 2452 2453 generic_hdmi_init_per_pins(codec); 2454 return 0; 2455 } 2456 2457 /* 2458 * generic audio component binding 2459 */ 2460 2461 /* turn on / off the unsol event jack detection dynamically */ 2462 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2463 int dev_id, bool use_acomp) 2464 { 2465 struct hda_jack_tbl *tbl; 2466 2467 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2468 if (tbl) { 2469 /* clear unsol even if component notifier is used, or re-enable 2470 * if notifier is cleared 2471 */ 2472 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2473 snd_hda_codec_write_cache(codec, nid, 0, 2474 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2475 } 2476 } 2477 2478 /* set up / clear component notifier dynamically */ 2479 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2480 bool use_acomp) 2481 { 2482 struct hdmi_spec *spec; 2483 int i; 2484 2485 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2486 mutex_lock(&spec->bind_lock); 2487 spec->use_acomp_notifier = use_acomp; 2488 spec->codec->relaxed_resume = use_acomp; 2489 /* reprogram each jack detection logic depending on the notifier */ 2490 for (i = 0; i < spec->num_pins; i++) 2491 reprogram_jack_detect(spec->codec, 2492 get_pin(spec, i)->pin_nid, 2493 get_pin(spec, i)->dev_id, 2494 use_acomp); 2495 mutex_unlock(&spec->bind_lock); 2496 } 2497 2498 /* enable / disable the notifier via master bind / unbind */ 2499 static int generic_acomp_master_bind(struct device *dev, 2500 struct drm_audio_component *acomp) 2501 { 2502 generic_acomp_notifier_set(acomp, true); 2503 return 0; 2504 } 2505 2506 static void generic_acomp_master_unbind(struct device *dev, 2507 struct drm_audio_component *acomp) 2508 { 2509 generic_acomp_notifier_set(acomp, false); 2510 } 2511 2512 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2513 static int match_bound_vga(struct device *dev, int subtype, void *data) 2514 { 2515 struct hdac_bus *bus = data; 2516 struct pci_dev *pci, *master; 2517 2518 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2519 return 0; 2520 master = to_pci_dev(bus->dev); 2521 pci = to_pci_dev(dev); 2522 return master->bus == pci->bus; 2523 } 2524 2525 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2526 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2527 { 2528 struct hda_codec *codec = audio_ptr; 2529 struct hdmi_spec *spec = codec->spec; 2530 hda_nid_t pin_nid = spec->port2pin(codec, port); 2531 2532 if (!pin_nid) 2533 return; 2534 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2535 return; 2536 /* skip notification during system suspend (but not in runtime PM); 2537 * the state will be updated at resume 2538 */ 2539 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2540 return; 2541 /* ditto during suspend/resume process itself */ 2542 if (snd_hdac_is_in_pm(&codec->core)) 2543 return; 2544 2545 check_presence_and_report(codec, pin_nid, dev_id); 2546 } 2547 2548 /* set up the private drm_audio_ops from the template */ 2549 static void setup_drm_audio_ops(struct hda_codec *codec, 2550 const struct drm_audio_component_audio_ops *ops) 2551 { 2552 struct hdmi_spec *spec = codec->spec; 2553 2554 spec->drm_audio_ops.audio_ptr = codec; 2555 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2556 * will call pin_eld_notify with using audio_ptr pointer 2557 * We need make sure audio_ptr is really setup 2558 */ 2559 wmb(); 2560 spec->drm_audio_ops.pin2port = ops->pin2port; 2561 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2562 spec->drm_audio_ops.master_bind = ops->master_bind; 2563 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2564 } 2565 2566 /* initialize the generic HDMI audio component */ 2567 static void generic_acomp_init(struct hda_codec *codec, 2568 const struct drm_audio_component_audio_ops *ops, 2569 int (*port2pin)(struct hda_codec *, int)) 2570 { 2571 struct hdmi_spec *spec = codec->spec; 2572 2573 if (!enable_acomp) { 2574 codec_info(codec, "audio component disabled by module option\n"); 2575 return; 2576 } 2577 2578 spec->port2pin = port2pin; 2579 setup_drm_audio_ops(codec, ops); 2580 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2581 match_bound_vga, 0)) { 2582 spec->acomp_registered = true; 2583 codec->bus->keep_power = 0; 2584 } 2585 } 2586 2587 /* 2588 * Intel codec parsers and helpers 2589 */ 2590 2591 #define INTEL_GET_VENDOR_VERB 0xf81 2592 #define INTEL_SET_VENDOR_VERB 0x781 2593 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2594 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2595 2596 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2597 bool update_tree) 2598 { 2599 unsigned int vendor_param; 2600 struct hdmi_spec *spec = codec->spec; 2601 2602 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2603 INTEL_GET_VENDOR_VERB, 0); 2604 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2605 return; 2606 2607 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2608 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2609 INTEL_SET_VENDOR_VERB, vendor_param); 2610 if (vendor_param == -1) 2611 return; 2612 2613 if (update_tree) 2614 snd_hda_codec_update_widgets(codec); 2615 } 2616 2617 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2618 { 2619 unsigned int vendor_param; 2620 struct hdmi_spec *spec = codec->spec; 2621 2622 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2623 INTEL_GET_VENDOR_VERB, 0); 2624 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2625 return; 2626 2627 /* enable DP1.2 mode */ 2628 vendor_param |= INTEL_EN_DP12; 2629 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2630 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2631 INTEL_SET_VENDOR_VERB, vendor_param); 2632 } 2633 2634 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2635 * Otherwise you may get severe h/w communication errors. 2636 */ 2637 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2638 unsigned int power_state) 2639 { 2640 if (power_state == AC_PWRST_D0) { 2641 intel_haswell_enable_all_pins(codec, false); 2642 intel_haswell_fixup_enable_dp12(codec); 2643 } 2644 2645 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2646 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2647 } 2648 2649 /* There is a fixed mapping between audio pin node and display port. 2650 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2651 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2652 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2653 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2654 * 2655 * on VLV, ILK: 2656 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2657 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2658 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2659 */ 2660 static int intel_base_nid(struct hda_codec *codec) 2661 { 2662 switch (codec->core.vendor_id) { 2663 case 0x80860054: /* ILK */ 2664 case 0x80862804: /* ILK */ 2665 case 0x80862882: /* VLV */ 2666 return 4; 2667 default: 2668 return 5; 2669 } 2670 } 2671 2672 static int intel_pin2port(void *audio_ptr, int pin_nid) 2673 { 2674 struct hda_codec *codec = audio_ptr; 2675 struct hdmi_spec *spec = codec->spec; 2676 int base_nid, i; 2677 2678 if (!spec->port_num) { 2679 base_nid = intel_base_nid(codec); 2680 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2681 return -1; 2682 return pin_nid - base_nid + 1; 2683 } 2684 2685 /* 2686 * looking for the pin number in the mapping table and return 2687 * the index which indicate the port number 2688 */ 2689 for (i = 0; i < spec->port_num; i++) { 2690 if (pin_nid == spec->port_map[i]) 2691 return i; 2692 } 2693 2694 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); 2695 return -1; 2696 } 2697 2698 static int intel_port2pin(struct hda_codec *codec, int port) 2699 { 2700 struct hdmi_spec *spec = codec->spec; 2701 2702 if (!spec->port_num) { 2703 /* we assume only from port-B to port-D */ 2704 if (port < 1 || port > 3) 2705 return 0; 2706 return port + intel_base_nid(codec) - 1; 2707 } 2708 2709 if (port < 0 || port >= spec->port_num) 2710 return 0; 2711 return spec->port_map[port]; 2712 } 2713 2714 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2715 { 2716 struct hda_codec *codec = audio_ptr; 2717 int pin_nid; 2718 int dev_id = pipe; 2719 2720 pin_nid = intel_port2pin(codec, port); 2721 if (!pin_nid) 2722 return; 2723 /* skip notification during system suspend (but not in runtime PM); 2724 * the state will be updated at resume 2725 */ 2726 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2727 return; 2728 /* ditto during suspend/resume process itself */ 2729 if (snd_hdac_is_in_pm(&codec->core)) 2730 return; 2731 2732 snd_hdac_i915_set_bclk(&codec->bus->core); 2733 check_presence_and_report(codec, pin_nid, dev_id); 2734 } 2735 2736 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2737 .pin2port = intel_pin2port, 2738 .pin_eld_notify = intel_pin_eld_notify, 2739 }; 2740 2741 /* register i915 component pin_eld_notify callback */ 2742 static void register_i915_notifier(struct hda_codec *codec) 2743 { 2744 struct hdmi_spec *spec = codec->spec; 2745 2746 spec->use_acomp_notifier = true; 2747 spec->port2pin = intel_port2pin; 2748 setup_drm_audio_ops(codec, &intel_audio_ops); 2749 snd_hdac_acomp_register_notifier(&codec->bus->core, 2750 &spec->drm_audio_ops); 2751 /* no need for forcible resume for jack check thanks to notifier */ 2752 codec->relaxed_resume = 1; 2753 } 2754 2755 /* setup_stream ops override for HSW+ */ 2756 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2757 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2758 int format) 2759 { 2760 haswell_verify_D0(codec, cvt_nid, pin_nid); 2761 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2762 stream_tag, format); 2763 } 2764 2765 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2766 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2767 struct hdmi_spec_per_pin *per_pin, 2768 hda_nid_t cvt_nid) 2769 { 2770 if (per_pin) { 2771 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2772 per_pin->dev_id); 2773 intel_verify_pin_cvt_connect(codec, per_pin); 2774 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2775 per_pin->dev_id, per_pin->mux_idx); 2776 } else { 2777 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2778 } 2779 } 2780 2781 /* precondition and allocation for Intel codecs */ 2782 static int alloc_intel_hdmi(struct hda_codec *codec) 2783 { 2784 int err; 2785 2786 /* requires i915 binding */ 2787 if (!codec->bus->core.audio_component) { 2788 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2789 /* set probe_id here to prevent generic fallback binding */ 2790 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2791 return -ENODEV; 2792 } 2793 2794 err = alloc_generic_hdmi(codec); 2795 if (err < 0) 2796 return err; 2797 /* no need to handle unsol events */ 2798 codec->patch_ops.unsol_event = NULL; 2799 return 0; 2800 } 2801 2802 /* parse and post-process for Intel codecs */ 2803 static int parse_intel_hdmi(struct hda_codec *codec) 2804 { 2805 int err, retries = 3; 2806 2807 do { 2808 err = hdmi_parse_codec(codec); 2809 } while (err < 0 && retries--); 2810 2811 if (err < 0) { 2812 generic_spec_free(codec); 2813 return err; 2814 } 2815 2816 generic_hdmi_init_per_pins(codec); 2817 register_i915_notifier(codec); 2818 return 0; 2819 } 2820 2821 /* Intel Haswell and onwards; audio component with eld notifier */ 2822 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2823 const int *port_map, int port_num) 2824 { 2825 struct hdmi_spec *spec; 2826 int err; 2827 2828 err = alloc_intel_hdmi(codec); 2829 if (err < 0) 2830 return err; 2831 spec = codec->spec; 2832 codec->dp_mst = true; 2833 spec->dyn_pcm_assign = true; 2834 spec->vendor_nid = vendor_nid; 2835 spec->port_map = port_map; 2836 spec->port_num = port_num; 2837 spec->intel_hsw_fixup = true; 2838 2839 intel_haswell_enable_all_pins(codec, true); 2840 intel_haswell_fixup_enable_dp12(codec); 2841 2842 codec->display_power_control = 1; 2843 2844 codec->patch_ops.set_power_state = haswell_set_power_state; 2845 codec->depop_delay = 0; 2846 codec->auto_runtime_pm = 1; 2847 2848 spec->ops.setup_stream = i915_hsw_setup_stream; 2849 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2850 2851 /* 2852 * Enable silent stream feature, if it is enabled via 2853 * module param or Kconfig option 2854 */ 2855 if (enable_silent_stream) 2856 spec->send_silent_stream = true; 2857 2858 return parse_intel_hdmi(codec); 2859 } 2860 2861 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2862 { 2863 return intel_hsw_common_init(codec, 0x08, NULL, 0); 2864 } 2865 2866 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2867 { 2868 return intel_hsw_common_init(codec, 0x0b, NULL, 0); 2869 } 2870 2871 static int patch_i915_icl_hdmi(struct hda_codec *codec) 2872 { 2873 /* 2874 * pin to port mapping table where the value indicate the pin number and 2875 * the index indicate the port number. 2876 */ 2877 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 2878 2879 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2880 } 2881 2882 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 2883 { 2884 /* 2885 * pin to port mapping table where the value indicate the pin number and 2886 * the index indicate the port number. 2887 */ 2888 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 2889 2890 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2891 } 2892 2893 /* Intel Baytrail and Braswell; with eld notifier */ 2894 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2895 { 2896 struct hdmi_spec *spec; 2897 int err; 2898 2899 err = alloc_intel_hdmi(codec); 2900 if (err < 0) 2901 return err; 2902 spec = codec->spec; 2903 2904 /* For Valleyview/Cherryview, only the display codec is in the display 2905 * power well and can use link_power ops to request/release the power. 2906 */ 2907 codec->display_power_control = 1; 2908 2909 codec->depop_delay = 0; 2910 codec->auto_runtime_pm = 1; 2911 2912 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2913 2914 return parse_intel_hdmi(codec); 2915 } 2916 2917 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2918 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2919 { 2920 int err; 2921 2922 err = alloc_intel_hdmi(codec); 2923 if (err < 0) 2924 return err; 2925 return parse_intel_hdmi(codec); 2926 } 2927 2928 /* 2929 * Shared non-generic implementations 2930 */ 2931 2932 static int simple_playback_build_pcms(struct hda_codec *codec) 2933 { 2934 struct hdmi_spec *spec = codec->spec; 2935 struct hda_pcm *info; 2936 unsigned int chans; 2937 struct hda_pcm_stream *pstr; 2938 struct hdmi_spec_per_cvt *per_cvt; 2939 2940 per_cvt = get_cvt(spec, 0); 2941 chans = get_wcaps(codec, per_cvt->cvt_nid); 2942 chans = get_wcaps_channels(chans); 2943 2944 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2945 if (!info) 2946 return -ENOMEM; 2947 spec->pcm_rec[0].pcm = info; 2948 info->pcm_type = HDA_PCM_TYPE_HDMI; 2949 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2950 *pstr = spec->pcm_playback; 2951 pstr->nid = per_cvt->cvt_nid; 2952 if (pstr->channels_max <= 2 && chans && chans <= 16) 2953 pstr->channels_max = chans; 2954 2955 return 0; 2956 } 2957 2958 /* unsolicited event for jack sensing */ 2959 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2960 unsigned int res) 2961 { 2962 snd_hda_jack_set_dirty_all(codec); 2963 snd_hda_jack_report_sync(codec); 2964 } 2965 2966 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2967 * as long as spec->pins[] is set correctly 2968 */ 2969 #define simple_hdmi_build_jack generic_hdmi_build_jack 2970 2971 static int simple_playback_build_controls(struct hda_codec *codec) 2972 { 2973 struct hdmi_spec *spec = codec->spec; 2974 struct hdmi_spec_per_cvt *per_cvt; 2975 int err; 2976 2977 per_cvt = get_cvt(spec, 0); 2978 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2979 per_cvt->cvt_nid, 2980 HDA_PCM_TYPE_HDMI); 2981 if (err < 0) 2982 return err; 2983 return simple_hdmi_build_jack(codec, 0); 2984 } 2985 2986 static int simple_playback_init(struct hda_codec *codec) 2987 { 2988 struct hdmi_spec *spec = codec->spec; 2989 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 2990 hda_nid_t pin = per_pin->pin_nid; 2991 2992 snd_hda_codec_write(codec, pin, 0, 2993 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 2994 /* some codecs require to unmute the pin */ 2995 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 2996 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 2997 AMP_OUT_UNMUTE); 2998 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 2999 return 0; 3000 } 3001 3002 static void simple_playback_free(struct hda_codec *codec) 3003 { 3004 struct hdmi_spec *spec = codec->spec; 3005 3006 hdmi_array_free(spec); 3007 kfree(spec); 3008 } 3009 3010 /* 3011 * Nvidia specific implementations 3012 */ 3013 3014 #define Nv_VERB_SET_Channel_Allocation 0xF79 3015 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3016 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3017 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3018 3019 #define nvhdmi_master_con_nid_7x 0x04 3020 #define nvhdmi_master_pin_nid_7x 0x05 3021 3022 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3023 /*front, rear, clfe, rear_surr */ 3024 0x6, 0x8, 0xa, 0xc, 3025 }; 3026 3027 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3028 /* set audio protect on */ 3029 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3030 /* enable digital output on pin widget */ 3031 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3032 {} /* terminator */ 3033 }; 3034 3035 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3036 /* set audio protect on */ 3037 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3038 /* enable digital output on pin widget */ 3039 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3040 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3041 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3042 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3043 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3044 {} /* terminator */ 3045 }; 3046 3047 #ifdef LIMITED_RATE_FMT_SUPPORT 3048 /* support only the safe format and rate */ 3049 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3050 #define SUPPORTED_MAXBPS 16 3051 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3052 #else 3053 /* support all rates and formats */ 3054 #define SUPPORTED_RATES \ 3055 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3056 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3057 SNDRV_PCM_RATE_192000) 3058 #define SUPPORTED_MAXBPS 24 3059 #define SUPPORTED_FORMATS \ 3060 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3061 #endif 3062 3063 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3064 { 3065 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3066 return 0; 3067 } 3068 3069 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3070 { 3071 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3072 return 0; 3073 } 3074 3075 static const unsigned int channels_2_6_8[] = { 3076 2, 6, 8 3077 }; 3078 3079 static const unsigned int channels_2_8[] = { 3080 2, 8 3081 }; 3082 3083 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3084 .count = ARRAY_SIZE(channels_2_6_8), 3085 .list = channels_2_6_8, 3086 .mask = 0, 3087 }; 3088 3089 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3090 .count = ARRAY_SIZE(channels_2_8), 3091 .list = channels_2_8, 3092 .mask = 0, 3093 }; 3094 3095 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3096 struct hda_codec *codec, 3097 struct snd_pcm_substream *substream) 3098 { 3099 struct hdmi_spec *spec = codec->spec; 3100 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3101 3102 switch (codec->preset->vendor_id) { 3103 case 0x10de0002: 3104 case 0x10de0003: 3105 case 0x10de0005: 3106 case 0x10de0006: 3107 hw_constraints_channels = &hw_constraints_2_8_channels; 3108 break; 3109 case 0x10de0007: 3110 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3111 break; 3112 default: 3113 break; 3114 } 3115 3116 if (hw_constraints_channels != NULL) { 3117 snd_pcm_hw_constraint_list(substream->runtime, 0, 3118 SNDRV_PCM_HW_PARAM_CHANNELS, 3119 hw_constraints_channels); 3120 } else { 3121 snd_pcm_hw_constraint_step(substream->runtime, 0, 3122 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3123 } 3124 3125 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3126 } 3127 3128 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3129 struct hda_codec *codec, 3130 struct snd_pcm_substream *substream) 3131 { 3132 struct hdmi_spec *spec = codec->spec; 3133 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3134 } 3135 3136 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3137 struct hda_codec *codec, 3138 unsigned int stream_tag, 3139 unsigned int format, 3140 struct snd_pcm_substream *substream) 3141 { 3142 struct hdmi_spec *spec = codec->spec; 3143 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3144 stream_tag, format, substream); 3145 } 3146 3147 static const struct hda_pcm_stream simple_pcm_playback = { 3148 .substreams = 1, 3149 .channels_min = 2, 3150 .channels_max = 2, 3151 .ops = { 3152 .open = simple_playback_pcm_open, 3153 .close = simple_playback_pcm_close, 3154 .prepare = simple_playback_pcm_prepare 3155 }, 3156 }; 3157 3158 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3159 .build_controls = simple_playback_build_controls, 3160 .build_pcms = simple_playback_build_pcms, 3161 .init = simple_playback_init, 3162 .free = simple_playback_free, 3163 .unsol_event = simple_hdmi_unsol_event, 3164 }; 3165 3166 static int patch_simple_hdmi(struct hda_codec *codec, 3167 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3168 { 3169 struct hdmi_spec *spec; 3170 struct hdmi_spec_per_cvt *per_cvt; 3171 struct hdmi_spec_per_pin *per_pin; 3172 3173 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3174 if (!spec) 3175 return -ENOMEM; 3176 3177 spec->codec = codec; 3178 codec->spec = spec; 3179 hdmi_array_init(spec, 1); 3180 3181 spec->multiout.num_dacs = 0; /* no analog */ 3182 spec->multiout.max_channels = 2; 3183 spec->multiout.dig_out_nid = cvt_nid; 3184 spec->num_cvts = 1; 3185 spec->num_pins = 1; 3186 per_pin = snd_array_new(&spec->pins); 3187 per_cvt = snd_array_new(&spec->cvts); 3188 if (!per_pin || !per_cvt) { 3189 simple_playback_free(codec); 3190 return -ENOMEM; 3191 } 3192 per_cvt->cvt_nid = cvt_nid; 3193 per_pin->pin_nid = pin_nid; 3194 spec->pcm_playback = simple_pcm_playback; 3195 3196 codec->patch_ops = simple_hdmi_patch_ops; 3197 3198 return 0; 3199 } 3200 3201 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3202 int channels) 3203 { 3204 unsigned int chanmask; 3205 int chan = channels ? (channels - 1) : 1; 3206 3207 switch (channels) { 3208 default: 3209 case 0: 3210 case 2: 3211 chanmask = 0x00; 3212 break; 3213 case 4: 3214 chanmask = 0x08; 3215 break; 3216 case 6: 3217 chanmask = 0x0b; 3218 break; 3219 case 8: 3220 chanmask = 0x13; 3221 break; 3222 } 3223 3224 /* Set the audio infoframe channel allocation and checksum fields. The 3225 * channel count is computed implicitly by the hardware. */ 3226 snd_hda_codec_write(codec, 0x1, 0, 3227 Nv_VERB_SET_Channel_Allocation, chanmask); 3228 3229 snd_hda_codec_write(codec, 0x1, 0, 3230 Nv_VERB_SET_Info_Frame_Checksum, 3231 (0x71 - chan - chanmask)); 3232 } 3233 3234 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3235 struct hda_codec *codec, 3236 struct snd_pcm_substream *substream) 3237 { 3238 struct hdmi_spec *spec = codec->spec; 3239 int i; 3240 3241 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3242 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3243 for (i = 0; i < 4; i++) { 3244 /* set the stream id */ 3245 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3246 AC_VERB_SET_CHANNEL_STREAMID, 0); 3247 /* set the stream format */ 3248 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3249 AC_VERB_SET_STREAM_FORMAT, 0); 3250 } 3251 3252 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3253 * streams are disabled. */ 3254 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3255 3256 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3257 } 3258 3259 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3260 struct hda_codec *codec, 3261 unsigned int stream_tag, 3262 unsigned int format, 3263 struct snd_pcm_substream *substream) 3264 { 3265 int chs; 3266 unsigned int dataDCC2, channel_id; 3267 int i; 3268 struct hdmi_spec *spec = codec->spec; 3269 struct hda_spdif_out *spdif; 3270 struct hdmi_spec_per_cvt *per_cvt; 3271 3272 mutex_lock(&codec->spdif_mutex); 3273 per_cvt = get_cvt(spec, 0); 3274 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3275 3276 chs = substream->runtime->channels; 3277 3278 dataDCC2 = 0x2; 3279 3280 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3281 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3282 snd_hda_codec_write(codec, 3283 nvhdmi_master_con_nid_7x, 3284 0, 3285 AC_VERB_SET_DIGI_CONVERT_1, 3286 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3287 3288 /* set the stream id */ 3289 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3290 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3291 3292 /* set the stream format */ 3293 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3294 AC_VERB_SET_STREAM_FORMAT, format); 3295 3296 /* turn on again (if needed) */ 3297 /* enable and set the channel status audio/data flag */ 3298 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3299 snd_hda_codec_write(codec, 3300 nvhdmi_master_con_nid_7x, 3301 0, 3302 AC_VERB_SET_DIGI_CONVERT_1, 3303 spdif->ctls & 0xff); 3304 snd_hda_codec_write(codec, 3305 nvhdmi_master_con_nid_7x, 3306 0, 3307 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3308 } 3309 3310 for (i = 0; i < 4; i++) { 3311 if (chs == 2) 3312 channel_id = 0; 3313 else 3314 channel_id = i * 2; 3315 3316 /* turn off SPDIF once; 3317 *otherwise the IEC958 bits won't be updated 3318 */ 3319 if (codec->spdif_status_reset && 3320 (spdif->ctls & AC_DIG1_ENABLE)) 3321 snd_hda_codec_write(codec, 3322 nvhdmi_con_nids_7x[i], 3323 0, 3324 AC_VERB_SET_DIGI_CONVERT_1, 3325 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3326 /* set the stream id */ 3327 snd_hda_codec_write(codec, 3328 nvhdmi_con_nids_7x[i], 3329 0, 3330 AC_VERB_SET_CHANNEL_STREAMID, 3331 (stream_tag << 4) | channel_id); 3332 /* set the stream format */ 3333 snd_hda_codec_write(codec, 3334 nvhdmi_con_nids_7x[i], 3335 0, 3336 AC_VERB_SET_STREAM_FORMAT, 3337 format); 3338 /* turn on again (if needed) */ 3339 /* enable and set the channel status audio/data flag */ 3340 if (codec->spdif_status_reset && 3341 (spdif->ctls & AC_DIG1_ENABLE)) { 3342 snd_hda_codec_write(codec, 3343 nvhdmi_con_nids_7x[i], 3344 0, 3345 AC_VERB_SET_DIGI_CONVERT_1, 3346 spdif->ctls & 0xff); 3347 snd_hda_codec_write(codec, 3348 nvhdmi_con_nids_7x[i], 3349 0, 3350 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3351 } 3352 } 3353 3354 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3355 3356 mutex_unlock(&codec->spdif_mutex); 3357 return 0; 3358 } 3359 3360 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3361 .substreams = 1, 3362 .channels_min = 2, 3363 .channels_max = 8, 3364 .nid = nvhdmi_master_con_nid_7x, 3365 .rates = SUPPORTED_RATES, 3366 .maxbps = SUPPORTED_MAXBPS, 3367 .formats = SUPPORTED_FORMATS, 3368 .ops = { 3369 .open = simple_playback_pcm_open, 3370 .close = nvhdmi_8ch_7x_pcm_close, 3371 .prepare = nvhdmi_8ch_7x_pcm_prepare 3372 }, 3373 }; 3374 3375 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3376 { 3377 struct hdmi_spec *spec; 3378 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3379 nvhdmi_master_pin_nid_7x); 3380 if (err < 0) 3381 return err; 3382 3383 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3384 /* override the PCM rates, etc, as the codec doesn't give full list */ 3385 spec = codec->spec; 3386 spec->pcm_playback.rates = SUPPORTED_RATES; 3387 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3388 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3389 return 0; 3390 } 3391 3392 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3393 { 3394 struct hdmi_spec *spec = codec->spec; 3395 int err = simple_playback_build_pcms(codec); 3396 if (!err) { 3397 struct hda_pcm *info = get_pcm_rec(spec, 0); 3398 info->own_chmap = true; 3399 } 3400 return err; 3401 } 3402 3403 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3404 { 3405 struct hdmi_spec *spec = codec->spec; 3406 struct hda_pcm *info; 3407 struct snd_pcm_chmap *chmap; 3408 int err; 3409 3410 err = simple_playback_build_controls(codec); 3411 if (err < 0) 3412 return err; 3413 3414 /* add channel maps */ 3415 info = get_pcm_rec(spec, 0); 3416 err = snd_pcm_add_chmap_ctls(info->pcm, 3417 SNDRV_PCM_STREAM_PLAYBACK, 3418 snd_pcm_alt_chmaps, 8, 0, &chmap); 3419 if (err < 0) 3420 return err; 3421 switch (codec->preset->vendor_id) { 3422 case 0x10de0002: 3423 case 0x10de0003: 3424 case 0x10de0005: 3425 case 0x10de0006: 3426 chmap->channel_mask = (1U << 2) | (1U << 8); 3427 break; 3428 case 0x10de0007: 3429 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3430 } 3431 return 0; 3432 } 3433 3434 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3435 { 3436 struct hdmi_spec *spec; 3437 int err = patch_nvhdmi_2ch(codec); 3438 if (err < 0) 3439 return err; 3440 spec = codec->spec; 3441 spec->multiout.max_channels = 8; 3442 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3443 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3444 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3445 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3446 3447 /* Initialize the audio infoframe channel mask and checksum to something 3448 * valid */ 3449 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3450 3451 return 0; 3452 } 3453 3454 /* 3455 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3456 * - 0x10de0015 3457 * - 0x10de0040 3458 */ 3459 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3460 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3461 { 3462 if (cap->ca_index == 0x00 && channels == 2) 3463 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3464 3465 /* If the speaker allocation matches the channel count, it is OK. */ 3466 if (cap->channels != channels) 3467 return -1; 3468 3469 /* all channels are remappable freely */ 3470 return SNDRV_CTL_TLVT_CHMAP_VAR; 3471 } 3472 3473 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3474 int ca, int chs, unsigned char *map) 3475 { 3476 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3477 return -EINVAL; 3478 3479 return 0; 3480 } 3481 3482 /* map from pin NID to port; port is 0-based */ 3483 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3484 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3485 { 3486 return pin_nid - 4; 3487 } 3488 3489 /* reverse-map from port to pin NID: see above */ 3490 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3491 { 3492 return port + 4; 3493 } 3494 3495 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3496 .pin2port = nvhdmi_pin2port, 3497 .pin_eld_notify = generic_acomp_pin_eld_notify, 3498 .master_bind = generic_acomp_master_bind, 3499 .master_unbind = generic_acomp_master_unbind, 3500 }; 3501 3502 static int patch_nvhdmi(struct hda_codec *codec) 3503 { 3504 struct hdmi_spec *spec; 3505 int err; 3506 3507 err = alloc_generic_hdmi(codec); 3508 if (err < 0) 3509 return err; 3510 codec->dp_mst = true; 3511 3512 spec = codec->spec; 3513 spec->dyn_pcm_assign = true; 3514 3515 err = hdmi_parse_codec(codec); 3516 if (err < 0) { 3517 generic_spec_free(codec); 3518 return err; 3519 } 3520 3521 generic_hdmi_init_per_pins(codec); 3522 3523 spec->dyn_pin_out = true; 3524 3525 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3526 nvhdmi_chmap_cea_alloc_validate_get_type; 3527 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3528 3529 codec->link_down_at_suspend = 1; 3530 3531 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3532 3533 return 0; 3534 } 3535 3536 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3537 { 3538 struct hdmi_spec *spec; 3539 int err; 3540 3541 err = patch_generic_hdmi(codec); 3542 if (err) 3543 return err; 3544 3545 spec = codec->spec; 3546 spec->dyn_pin_out = true; 3547 3548 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3549 nvhdmi_chmap_cea_alloc_validate_get_type; 3550 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3551 3552 codec->link_down_at_suspend = 1; 3553 3554 return 0; 3555 } 3556 3557 /* 3558 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3559 * accessed using vendor-defined verbs. These registers can be used for 3560 * interoperability between the HDA and HDMI drivers. 3561 */ 3562 3563 /* Audio Function Group node */ 3564 #define NVIDIA_AFG_NID 0x01 3565 3566 /* 3567 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3568 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3569 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3570 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3571 * additional bit (at position 30) to signal the validity of the format. 3572 * 3573 * | 31 | 30 | 29 16 | 15 0 | 3574 * +---------+-------+--------+--------+ 3575 * | TRIGGER | VALID | UNUSED | FORMAT | 3576 * +-----------------------------------| 3577 * 3578 * Note that for the trigger bit to take effect it needs to change value 3579 * (i.e. it needs to be toggled). 3580 */ 3581 #define NVIDIA_GET_SCRATCH0 0xfa6 3582 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3583 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3584 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3585 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3586 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3587 #define NVIDIA_SCRATCH_VALID (1 << 6) 3588 3589 #define NVIDIA_GET_SCRATCH1 0xfab 3590 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3591 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3592 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3593 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3594 3595 /* 3596 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3597 * the format is invalidated so that the HDMI codec can be disabled. 3598 */ 3599 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3600 { 3601 unsigned int value; 3602 3603 /* bits [31:30] contain the trigger and valid bits */ 3604 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3605 NVIDIA_GET_SCRATCH0, 0); 3606 value = (value >> 24) & 0xff; 3607 3608 /* bits [15:0] are used to store the HDA format */ 3609 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3610 NVIDIA_SET_SCRATCH0_BYTE0, 3611 (format >> 0) & 0xff); 3612 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3613 NVIDIA_SET_SCRATCH0_BYTE1, 3614 (format >> 8) & 0xff); 3615 3616 /* bits [16:24] are unused */ 3617 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3618 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3619 3620 /* 3621 * Bit 30 signals that the data is valid and hence that HDMI audio can 3622 * be enabled. 3623 */ 3624 if (format == 0) 3625 value &= ~NVIDIA_SCRATCH_VALID; 3626 else 3627 value |= NVIDIA_SCRATCH_VALID; 3628 3629 /* 3630 * Whenever the trigger bit is toggled, an interrupt is raised in the 3631 * HDMI codec. The HDMI driver will use that as trigger to update its 3632 * configuration. 3633 */ 3634 value ^= NVIDIA_SCRATCH_TRIGGER; 3635 3636 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3637 NVIDIA_SET_SCRATCH0_BYTE3, value); 3638 } 3639 3640 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3641 struct hda_codec *codec, 3642 unsigned int stream_tag, 3643 unsigned int format, 3644 struct snd_pcm_substream *substream) 3645 { 3646 int err; 3647 3648 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3649 format, substream); 3650 if (err < 0) 3651 return err; 3652 3653 /* notify the HDMI codec of the format change */ 3654 tegra_hdmi_set_format(codec, format); 3655 3656 return 0; 3657 } 3658 3659 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3660 struct hda_codec *codec, 3661 struct snd_pcm_substream *substream) 3662 { 3663 /* invalidate the format in the HDMI codec */ 3664 tegra_hdmi_set_format(codec, 0); 3665 3666 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3667 } 3668 3669 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3670 { 3671 struct hdmi_spec *spec = codec->spec; 3672 unsigned int i; 3673 3674 for (i = 0; i < spec->num_pins; i++) { 3675 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3676 3677 if (pcm->pcm_type == type) 3678 return pcm; 3679 } 3680 3681 return NULL; 3682 } 3683 3684 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3685 { 3686 struct hda_pcm_stream *stream; 3687 struct hda_pcm *pcm; 3688 int err; 3689 3690 err = generic_hdmi_build_pcms(codec); 3691 if (err < 0) 3692 return err; 3693 3694 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3695 if (!pcm) 3696 return -ENODEV; 3697 3698 /* 3699 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3700 * codec about format changes. 3701 */ 3702 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3703 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3704 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3705 3706 return 0; 3707 } 3708 3709 static int patch_tegra_hdmi(struct hda_codec *codec) 3710 { 3711 int err; 3712 3713 err = patch_generic_hdmi(codec); 3714 if (err) 3715 return err; 3716 3717 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3718 3719 return 0; 3720 } 3721 3722 /* 3723 * ATI/AMD-specific implementations 3724 */ 3725 3726 #define is_amdhdmi_rev3_or_later(codec) \ 3727 ((codec)->core.vendor_id == 0x1002aa01 && \ 3728 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3729 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3730 3731 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3732 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3733 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3734 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3735 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3736 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3737 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3738 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3739 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3740 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3741 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3742 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3743 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3744 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3745 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3746 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3747 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3748 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3749 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3750 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3751 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3752 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3753 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3754 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3755 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3756 3757 /* AMD specific HDA cvt verbs */ 3758 #define ATI_VERB_SET_RAMP_RATE 0x770 3759 #define ATI_VERB_GET_RAMP_RATE 0xf70 3760 3761 #define ATI_OUT_ENABLE 0x1 3762 3763 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3764 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3765 3766 #define ATI_HBR_CAPABLE 0x01 3767 #define ATI_HBR_ENABLE 0x10 3768 3769 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3770 int dev_id, unsigned char *buf, int *eld_size) 3771 { 3772 WARN_ON(dev_id != 0); 3773 /* call hda_eld.c ATI/AMD-specific function */ 3774 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3775 is_amdhdmi_rev3_or_later(codec)); 3776 } 3777 3778 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 3779 hda_nid_t pin_nid, int dev_id, int ca, 3780 int active_channels, int conn_type) 3781 { 3782 WARN_ON(dev_id != 0); 3783 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3784 } 3785 3786 static int atihdmi_paired_swap_fc_lfe(int pos) 3787 { 3788 /* 3789 * ATI/AMD have automatic FC/LFE swap built-in 3790 * when in pairwise mapping mode. 3791 */ 3792 3793 switch (pos) { 3794 /* see channel_allocations[].speakers[] */ 3795 case 2: return 3; 3796 case 3: return 2; 3797 default: break; 3798 } 3799 3800 return pos; 3801 } 3802 3803 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3804 int ca, int chs, unsigned char *map) 3805 { 3806 struct hdac_cea_channel_speaker_allocation *cap; 3807 int i, j; 3808 3809 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3810 3811 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3812 for (i = 0; i < chs; ++i) { 3813 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3814 bool ok = false; 3815 bool companion_ok = false; 3816 3817 if (!mask) 3818 continue; 3819 3820 for (j = 0 + i % 2; j < 8; j += 2) { 3821 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3822 if (cap->speakers[chan_idx] == mask) { 3823 /* channel is in a supported position */ 3824 ok = true; 3825 3826 if (i % 2 == 0 && i + 1 < chs) { 3827 /* even channel, check the odd companion */ 3828 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3829 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3830 int comp_mask_act = cap->speakers[comp_chan_idx]; 3831 3832 if (comp_mask_req == comp_mask_act) 3833 companion_ok = true; 3834 else 3835 return -EINVAL; 3836 } 3837 break; 3838 } 3839 } 3840 3841 if (!ok) 3842 return -EINVAL; 3843 3844 if (companion_ok) 3845 i++; /* companion channel already checked */ 3846 } 3847 3848 return 0; 3849 } 3850 3851 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3852 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3853 { 3854 struct hda_codec *codec = hdac_to_hda_codec(hdac); 3855 int verb; 3856 int ati_channel_setup = 0; 3857 3858 if (hdmi_slot > 7) 3859 return -EINVAL; 3860 3861 if (!has_amd_full_remap_support(codec)) { 3862 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3863 3864 /* In case this is an odd slot but without stream channel, do not 3865 * disable the slot since the corresponding even slot could have a 3866 * channel. In case neither have a channel, the slot pair will be 3867 * disabled when this function is called for the even slot. */ 3868 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3869 return 0; 3870 3871 hdmi_slot -= hdmi_slot % 2; 3872 3873 if (stream_channel != 0xf) 3874 stream_channel -= stream_channel % 2; 3875 } 3876 3877 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3878 3879 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3880 3881 if (stream_channel != 0xf) 3882 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3883 3884 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3885 } 3886 3887 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3888 hda_nid_t pin_nid, int asp_slot) 3889 { 3890 struct hda_codec *codec = hdac_to_hda_codec(hdac); 3891 bool was_odd = false; 3892 int ati_asp_slot = asp_slot; 3893 int verb; 3894 int ati_channel_setup; 3895 3896 if (asp_slot > 7) 3897 return -EINVAL; 3898 3899 if (!has_amd_full_remap_support(codec)) { 3900 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3901 if (ati_asp_slot % 2 != 0) { 3902 ati_asp_slot -= 1; 3903 was_odd = true; 3904 } 3905 } 3906 3907 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3908 3909 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3910 3911 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3912 return 0xf; 3913 3914 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3915 } 3916 3917 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3918 struct hdac_chmap *chmap, 3919 struct hdac_cea_channel_speaker_allocation *cap, 3920 int channels) 3921 { 3922 int c; 3923 3924 /* 3925 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3926 * we need to take that into account (a single channel may take 2 3927 * channel slots if we need to carry a silent channel next to it). 3928 * On Rev3+ AMD codecs this function is not used. 3929 */ 3930 int chanpairs = 0; 3931 3932 /* We only produce even-numbered channel count TLVs */ 3933 if ((channels % 2) != 0) 3934 return -1; 3935 3936 for (c = 0; c < 7; c += 2) { 3937 if (cap->speakers[c] || cap->speakers[c+1]) 3938 chanpairs++; 3939 } 3940 3941 if (chanpairs * 2 != channels) 3942 return -1; 3943 3944 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3945 } 3946 3947 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3948 struct hdac_cea_channel_speaker_allocation *cap, 3949 unsigned int *chmap, int channels) 3950 { 3951 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3952 int count = 0; 3953 int c; 3954 3955 for (c = 7; c >= 0; c--) { 3956 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3957 int spk = cap->speakers[chan]; 3958 if (!spk) { 3959 /* add N/A channel if the companion channel is occupied */ 3960 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3961 chmap[count++] = SNDRV_CHMAP_NA; 3962 3963 continue; 3964 } 3965 3966 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3967 } 3968 3969 WARN_ON(count != channels); 3970 } 3971 3972 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3973 int dev_id, bool hbr) 3974 { 3975 int hbr_ctl, hbr_ctl_new; 3976 3977 WARN_ON(dev_id != 0); 3978 3979 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3980 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3981 if (hbr) 3982 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 3983 else 3984 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 3985 3986 codec_dbg(codec, 3987 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 3988 pin_nid, 3989 hbr_ctl == hbr_ctl_new ? "" : "new-", 3990 hbr_ctl_new); 3991 3992 if (hbr_ctl != hbr_ctl_new) 3993 snd_hda_codec_write(codec, pin_nid, 0, 3994 ATI_VERB_SET_HBR_CONTROL, 3995 hbr_ctl_new); 3996 3997 } else if (hbr) 3998 return -EINVAL; 3999 4000 return 0; 4001 } 4002 4003 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4004 hda_nid_t pin_nid, int dev_id, 4005 u32 stream_tag, int format) 4006 { 4007 if (is_amdhdmi_rev3_or_later(codec)) { 4008 int ramp_rate = 180; /* default as per AMD spec */ 4009 /* disable ramp-up/down for non-pcm as per AMD spec */ 4010 if (format & AC_FMT_TYPE_NON_PCM) 4011 ramp_rate = 0; 4012 4013 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4014 } 4015 4016 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4017 stream_tag, format); 4018 } 4019 4020 4021 static int atihdmi_init(struct hda_codec *codec) 4022 { 4023 struct hdmi_spec *spec = codec->spec; 4024 int pin_idx, err; 4025 4026 err = generic_hdmi_init(codec); 4027 4028 if (err) 4029 return err; 4030 4031 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4032 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4033 4034 /* make sure downmix information in infoframe is zero */ 4035 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4036 4037 /* enable channel-wise remap mode if supported */ 4038 if (has_amd_full_remap_support(codec)) 4039 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4040 ATI_VERB_SET_MULTICHANNEL_MODE, 4041 ATI_MULTICHANNEL_MODE_SINGLE); 4042 } 4043 codec->auto_runtime_pm = 1; 4044 4045 return 0; 4046 } 4047 4048 /* map from pin NID to port; port is 0-based */ 4049 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4050 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4051 { 4052 return pin_nid / 2 - 1; 4053 } 4054 4055 /* reverse-map from port to pin NID: see above */ 4056 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4057 { 4058 return port * 2 + 3; 4059 } 4060 4061 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4062 .pin2port = atihdmi_pin2port, 4063 .pin_eld_notify = generic_acomp_pin_eld_notify, 4064 .master_bind = generic_acomp_master_bind, 4065 .master_unbind = generic_acomp_master_unbind, 4066 }; 4067 4068 static int patch_atihdmi(struct hda_codec *codec) 4069 { 4070 struct hdmi_spec *spec; 4071 struct hdmi_spec_per_cvt *per_cvt; 4072 int err, cvt_idx; 4073 4074 err = patch_generic_hdmi(codec); 4075 4076 if (err) 4077 return err; 4078 4079 codec->patch_ops.init = atihdmi_init; 4080 4081 spec = codec->spec; 4082 4083 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4084 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4085 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4086 spec->ops.setup_stream = atihdmi_setup_stream; 4087 4088 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4089 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4090 4091 if (!has_amd_full_remap_support(codec)) { 4092 /* override to ATI/AMD-specific versions with pairwise mapping */ 4093 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4094 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4095 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4096 atihdmi_paired_cea_alloc_to_tlv_chmap; 4097 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4098 } 4099 4100 /* ATI/AMD converters do not advertise all of their capabilities */ 4101 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4102 per_cvt = get_cvt(spec, cvt_idx); 4103 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4104 per_cvt->rates |= SUPPORTED_RATES; 4105 per_cvt->formats |= SUPPORTED_FORMATS; 4106 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4107 } 4108 4109 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4110 4111 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4112 * the link-down as is. Tell the core to allow it. 4113 */ 4114 codec->link_down_at_suspend = 1; 4115 4116 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4117 4118 return 0; 4119 } 4120 4121 /* VIA HDMI Implementation */ 4122 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4123 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4124 4125 static int patch_via_hdmi(struct hda_codec *codec) 4126 { 4127 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4128 } 4129 4130 /* 4131 * patch entries 4132 */ 4133 static const struct hda_device_id snd_hda_id_hdmi[] = { 4134 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4135 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4136 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4137 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4138 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4139 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4140 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4141 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4142 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4143 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4144 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4145 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4146 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4147 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4148 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4149 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4150 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4151 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4152 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4153 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4154 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4155 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4156 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4157 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4158 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4159 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4160 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4161 /* 17 is known to be absent */ 4162 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4163 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4164 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4165 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4166 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4167 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4168 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4169 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4170 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4171 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4172 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4173 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4174 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4175 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4176 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4177 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4178 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4179 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4180 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4181 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4182 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4183 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4184 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4185 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4186 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4187 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4188 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4189 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4190 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4191 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4192 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4193 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4194 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4195 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4196 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4197 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4198 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4199 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4200 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4201 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4202 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4203 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4204 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4205 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4206 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4207 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4208 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4209 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4210 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4211 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4212 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4213 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4214 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4215 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4216 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4217 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4218 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4219 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4220 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4221 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4222 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4223 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4224 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4225 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4226 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4227 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4228 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4229 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4230 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4231 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4232 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4233 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4234 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4235 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4236 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4237 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4238 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4239 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4240 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4241 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4242 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4243 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4244 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4245 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4246 /* special ID for generic HDMI */ 4247 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4248 {} /* terminator */ 4249 }; 4250 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4251 4252 MODULE_LICENSE("GPL"); 4253 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4254 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4255 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4256 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4257 4258 static struct hda_codec_driver hdmi_driver = { 4259 .id = snd_hda_id_hdmi, 4260 }; 4261 4262 module_hda_codec_driver(hdmi_driver); 4263