1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 40 #ifdef CONFIG_X86 41 /* for snoop control */ 42 #include <asm/pgtable.h> 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/firmware.h> 54 #include <sound/hda_codec.h> 55 #include "hda_controller.h" 56 #include "hda_intel.h" 57 58 #define CREATE_TRACE_POINTS 59 #include "hda_intel_trace.h" 60 61 /* position fix mode */ 62 enum { 63 POS_FIX_AUTO, 64 POS_FIX_LPIB, 65 POS_FIX_POSBUF, 66 POS_FIX_VIACOMBO, 67 POS_FIX_COMBO, 68 POS_FIX_SKL, 69 POS_FIX_FIFO, 70 }; 71 72 /* Defines for ATI HD Audio support in SB450 south bridge */ 73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 75 76 /* Defines for Nvidia HDA support */ 77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 79 #define NVIDIA_HDA_ISTRM_COH 0x4d 80 #define NVIDIA_HDA_OSTRM_COH 0x4c 81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 82 83 /* Defines for Intel SCH HDA snoop control */ 84 #define INTEL_HDA_CGCTL 0x48 85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 86 #define INTEL_SCH_HDA_DEVC 0x78 87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 88 89 /* Define VIA HD Audio Device ID*/ 90 #define VIA_HDAC_DEVICE_ID 0x3288 91 92 /* max number of SDs */ 93 /* ICH, ATI and VIA have 4 playback and 4 capture */ 94 #define ICH6_NUM_CAPTURE 4 95 #define ICH6_NUM_PLAYBACK 4 96 97 /* ULI has 6 playback and 5 capture */ 98 #define ULI_NUM_CAPTURE 5 99 #define ULI_NUM_PLAYBACK 6 100 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 102 #define ATIHDMI_NUM_CAPTURE 0 103 #define ATIHDMI_NUM_PLAYBACK 8 104 105 /* TERA has 4 playback and 3 capture */ 106 #define TERA_NUM_CAPTURE 3 107 #define TERA_NUM_PLAYBACK 4 108 109 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 113 static char *model[SNDRV_CARDS]; 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 117 static int probe_only[SNDRV_CARDS]; 118 static int jackpoll_ms[SNDRV_CARDS]; 119 static int single_cmd = -1; 120 static int enable_msi = -1; 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER 122 static char *patch[SNDRV_CARDS]; 123 #endif 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 126 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 127 #endif 128 static bool dsp_driver = 1; 129 130 module_param_array(index, int, NULL, 0444); 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 132 module_param_array(id, charp, NULL, 0444); 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 134 module_param_array(enable, bool, NULL, 0444); 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 136 module_param_array(model, charp, NULL, 0444); 137 MODULE_PARM_DESC(model, "Use the given board model."); 138 module_param_array(position_fix, int, NULL, 0444); 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 141 module_param_array(bdl_pos_adj, int, NULL, 0644); 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 143 module_param_array(probe_mask, int, NULL, 0444); 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 145 module_param_array(probe_only, int, NULL, 0444); 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 147 module_param_array(jackpoll_ms, int, NULL, 0444); 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 149 module_param(single_cmd, bint, 0444); 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 151 "(for debugging only)."); 152 module_param(enable_msi, bint, 0444); 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER 155 module_param_array(patch, charp, NULL, 0444); 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 157 #endif 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP 159 module_param_array(beep_mode, bool, NULL, 0444); 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 161 "(0=off, 1=on) (default=1)."); 162 #endif 163 module_param(dsp_driver, bool, 0444); 164 MODULE_PARM_DESC(dsp_driver, "Allow DSP driver selection (bypass this driver) " 165 "(0=off, 1=on) (default=1)"); 166 167 #ifdef CONFIG_PM 168 static int param_set_xint(const char *val, const struct kernel_param *kp); 169 static const struct kernel_param_ops param_ops_xint = { 170 .set = param_set_xint, 171 .get = param_get_int, 172 }; 173 #define param_check_xint param_check_int 174 175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 176 module_param(power_save, xint, 0644); 177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 178 "(in second, 0 = disable)."); 179 180 static bool pm_blacklist = true; 181 module_param(pm_blacklist, bool, 0644); 182 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist"); 183 184 /* reset the HD-audio controller in power save mode. 185 * this may give more power-saving, but will take longer time to 186 * wake up. 187 */ 188 static bool power_save_controller = 1; 189 module_param(power_save_controller, bool, 0644); 190 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 191 #else 192 #define power_save 0 193 #endif /* CONFIG_PM */ 194 195 static int align_buffer_size = -1; 196 module_param(align_buffer_size, bint, 0644); 197 MODULE_PARM_DESC(align_buffer_size, 198 "Force buffer and period sizes to be multiple of 128 bytes."); 199 200 #ifdef CONFIG_X86 201 static int hda_snoop = -1; 202 module_param_named(snoop, hda_snoop, bint, 0444); 203 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 204 #else 205 #define hda_snoop true 206 #endif 207 208 209 MODULE_LICENSE("GPL"); 210 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 211 "{Intel, ICH6M}," 212 "{Intel, ICH7}," 213 "{Intel, ESB2}," 214 "{Intel, ICH8}," 215 "{Intel, ICH9}," 216 "{Intel, ICH10}," 217 "{Intel, PCH}," 218 "{Intel, CPT}," 219 "{Intel, PPT}," 220 "{Intel, LPT}," 221 "{Intel, LPT_LP}," 222 "{Intel, WPT_LP}," 223 "{Intel, SPT}," 224 "{Intel, SPT_LP}," 225 "{Intel, HPT}," 226 "{Intel, PBG}," 227 "{Intel, SCH}," 228 "{ATI, SB450}," 229 "{ATI, SB600}," 230 "{ATI, RS600}," 231 "{ATI, RS690}," 232 "{ATI, RS780}," 233 "{ATI, R600}," 234 "{ATI, RV630}," 235 "{ATI, RV610}," 236 "{ATI, RV670}," 237 "{ATI, RV635}," 238 "{ATI, RV620}," 239 "{ATI, RV770}," 240 "{VIA, VT8251}," 241 "{VIA, VT8237A}," 242 "{SiS, SIS966}," 243 "{ULI, M5461}}"); 244 MODULE_DESCRIPTION("Intel HDA driver"); 245 246 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 247 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 248 #define SUPPORT_VGA_SWITCHEROO 249 #endif 250 #endif 251 252 253 /* 254 */ 255 256 /* driver types */ 257 enum { 258 AZX_DRIVER_ICH, 259 AZX_DRIVER_PCH, 260 AZX_DRIVER_SCH, 261 AZX_DRIVER_SKL, 262 AZX_DRIVER_HDMI, 263 AZX_DRIVER_ATI, 264 AZX_DRIVER_ATIHDMI, 265 AZX_DRIVER_ATIHDMI_NS, 266 AZX_DRIVER_VIA, 267 AZX_DRIVER_SIS, 268 AZX_DRIVER_ULI, 269 AZX_DRIVER_NVIDIA, 270 AZX_DRIVER_TERA, 271 AZX_DRIVER_CTX, 272 AZX_DRIVER_CTHDA, 273 AZX_DRIVER_CMEDIA, 274 AZX_DRIVER_ZHAOXIN, 275 AZX_DRIVER_GENERIC, 276 AZX_NUM_DRIVERS, /* keep this as last entry */ 277 }; 278 279 #define azx_get_snoop_type(chip) \ 280 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 281 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 282 283 /* quirks for old Intel chipsets */ 284 #define AZX_DCAPS_INTEL_ICH \ 285 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE |\ 286 AZX_DCAPS_SYNC_WRITE) 287 288 /* quirks for Intel PCH */ 289 #define AZX_DCAPS_INTEL_PCH_BASE \ 290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 291 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE) 292 293 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 294 #define AZX_DCAPS_INTEL_PCH_NOPM \ 295 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 296 297 /* PCH for HSW/BDW; with runtime PM */ 298 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 299 #define AZX_DCAPS_INTEL_PCH \ 300 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 301 302 /* HSW HDMI */ 303 #define AZX_DCAPS_INTEL_HASWELL \ 304 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 305 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 306 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE) 307 308 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 309 #define AZX_DCAPS_INTEL_BROADWELL \ 310 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 311 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 312 AZX_DCAPS_SNOOP_TYPE(SCH) | AZX_DCAPS_SYNC_WRITE) 313 314 #define AZX_DCAPS_INTEL_BAYTRAIL \ 315 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 316 317 #define AZX_DCAPS_INTEL_BRASWELL \ 318 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 319 AZX_DCAPS_I915_COMPONENT) 320 321 #define AZX_DCAPS_INTEL_SKYLAKE \ 322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 323 AZX_DCAPS_SYNC_WRITE |\ 324 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 325 326 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 327 328 /* quirks for ATI SB / AMD Hudson */ 329 #define AZX_DCAPS_PRESET_ATI_SB \ 330 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\ 331 AZX_DCAPS_SNOOP_TYPE(ATI)) 332 333 /* quirks for ATI/AMD HDMI */ 334 #define AZX_DCAPS_PRESET_ATI_HDMI \ 335 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\ 336 AZX_DCAPS_NO_MSI64) 337 338 /* quirks for ATI HDMI with snoop off */ 339 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 340 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 341 342 /* quirks for AMD SB */ 343 #define AZX_DCAPS_PRESET_AMD_SB \ 344 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_AMD_WORKAROUND |\ 345 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME) 346 347 /* quirks for Nvidia */ 348 #define AZX_DCAPS_PRESET_NVIDIA \ 349 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 350 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 351 352 #define AZX_DCAPS_PRESET_CTHDA \ 353 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 354 AZX_DCAPS_NO_64BIT |\ 355 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 356 357 /* 358 * vga_switcheroo support 359 */ 360 #ifdef SUPPORT_VGA_SWITCHEROO 361 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 362 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 363 #else 364 #define use_vga_switcheroo(chip) 0 365 #define needs_eld_notify_link(chip) false 366 #endif 367 368 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 369 ((pci)->device == 0x0c0c) || \ 370 ((pci)->device == 0x0d0c) || \ 371 ((pci)->device == 0x160c)) 372 373 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 374 375 static const char * const driver_short_names[] = { 376 [AZX_DRIVER_ICH] = "HDA Intel", 377 [AZX_DRIVER_PCH] = "HDA Intel PCH", 378 [AZX_DRIVER_SCH] = "HDA Intel MID", 379 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 380 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 381 [AZX_DRIVER_ATI] = "HDA ATI SB", 382 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 383 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 384 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 385 [AZX_DRIVER_SIS] = "HDA SIS966", 386 [AZX_DRIVER_ULI] = "HDA ULI M5461", 387 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 388 [AZX_DRIVER_TERA] = "HDA Teradici", 389 [AZX_DRIVER_CTX] = "HDA Creative", 390 [AZX_DRIVER_CTHDA] = "HDA Creative", 391 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 392 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 393 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 394 }; 395 396 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 397 static void set_default_power_save(struct azx *chip); 398 399 /* 400 * initialize the PCI registers 401 */ 402 /* update bits in a PCI register byte */ 403 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 404 unsigned char mask, unsigned char val) 405 { 406 unsigned char data; 407 408 pci_read_config_byte(pci, reg, &data); 409 data &= ~mask; 410 data |= (val & mask); 411 pci_write_config_byte(pci, reg, data); 412 } 413 414 static void azx_init_pci(struct azx *chip) 415 { 416 int snoop_type = azx_get_snoop_type(chip); 417 418 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 419 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 420 * Ensuring these bits are 0 clears playback static on some HD Audio 421 * codecs. 422 * The PCI register TCSEL is defined in the Intel manuals. 423 */ 424 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 425 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 426 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 427 } 428 429 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 430 * we need to enable snoop. 431 */ 432 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 433 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 434 azx_snoop(chip)); 435 update_pci_byte(chip->pci, 436 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 437 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 438 } 439 440 /* For NVIDIA HDA, enable snoop */ 441 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 442 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 443 azx_snoop(chip)); 444 update_pci_byte(chip->pci, 445 NVIDIA_HDA_TRANSREG_ADDR, 446 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 447 update_pci_byte(chip->pci, 448 NVIDIA_HDA_ISTRM_COH, 449 0x01, NVIDIA_HDA_ENABLE_COHBIT); 450 update_pci_byte(chip->pci, 451 NVIDIA_HDA_OSTRM_COH, 452 0x01, NVIDIA_HDA_ENABLE_COHBIT); 453 } 454 455 /* Enable SCH/PCH snoop if needed */ 456 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 457 unsigned short snoop; 458 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 459 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 460 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 461 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 462 if (!azx_snoop(chip)) 463 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 464 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 465 pci_read_config_word(chip->pci, 466 INTEL_SCH_HDA_DEVC, &snoop); 467 } 468 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 469 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 470 "Disabled" : "Enabled"); 471 } 472 } 473 474 /* 475 * In BXT-P A0, HD-Audio DMA requests is later than expected, 476 * and makes an audio stream sensitive to system latencies when 477 * 24/32 bits are playing. 478 * Adjusting threshold of DMA fifo to force the DMA request 479 * sooner to improve latency tolerance at the expense of power. 480 */ 481 static void bxt_reduce_dma_latency(struct azx *chip) 482 { 483 u32 val; 484 485 val = azx_readl(chip, VS_EM4L); 486 val &= (0x3 << 20); 487 azx_writel(chip, VS_EM4L, val); 488 } 489 490 /* 491 * ML_LCAP bits: 492 * bit 0: 6 MHz Supported 493 * bit 1: 12 MHz Supported 494 * bit 2: 24 MHz Supported 495 * bit 3: 48 MHz Supported 496 * bit 4: 96 MHz Supported 497 * bit 5: 192 MHz Supported 498 */ 499 static int intel_get_lctl_scf(struct azx *chip) 500 { 501 struct hdac_bus *bus = azx_bus(chip); 502 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 503 u32 val, t; 504 int i; 505 506 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 507 508 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 509 t = preferred_bits[i]; 510 if (val & (1 << t)) 511 return t; 512 } 513 514 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 515 return 0; 516 } 517 518 static int intel_ml_lctl_set_power(struct azx *chip, int state) 519 { 520 struct hdac_bus *bus = azx_bus(chip); 521 u32 val; 522 int timeout; 523 524 /* 525 * the codecs are sharing the first link setting by default 526 * If other links are enabled for stream, they need similar fix 527 */ 528 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 529 val &= ~AZX_MLCTL_SPA; 530 val |= state << AZX_MLCTL_SPA_SHIFT; 531 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 532 /* wait for CPA */ 533 timeout = 50; 534 while (timeout) { 535 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 536 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 537 return 0; 538 timeout--; 539 udelay(10); 540 } 541 542 return -1; 543 } 544 545 static void intel_init_lctl(struct azx *chip) 546 { 547 struct hdac_bus *bus = azx_bus(chip); 548 u32 val; 549 int ret; 550 551 /* 0. check lctl register value is correct or not */ 552 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 553 /* if SCF is already set, let's use it */ 554 if ((val & ML_LCTL_SCF_MASK) != 0) 555 return; 556 557 /* 558 * Before operating on SPA, CPA must match SPA. 559 * Any deviation may result in undefined behavior. 560 */ 561 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 562 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 563 return; 564 565 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 566 ret = intel_ml_lctl_set_power(chip, 0); 567 udelay(100); 568 if (ret) 569 goto set_spa; 570 571 /* 2. update SCF to select a properly audio clock*/ 572 val &= ~ML_LCTL_SCF_MASK; 573 val |= intel_get_lctl_scf(chip); 574 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 575 576 set_spa: 577 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 578 intel_ml_lctl_set_power(chip, 1); 579 udelay(100); 580 } 581 582 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 583 { 584 struct hdac_bus *bus = azx_bus(chip); 585 struct pci_dev *pci = chip->pci; 586 u32 val; 587 588 snd_hdac_set_codec_wakeup(bus, true); 589 if (chip->driver_type == AZX_DRIVER_SKL) { 590 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 591 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 592 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 593 } 594 azx_init_chip(chip, full_reset); 595 if (chip->driver_type == AZX_DRIVER_SKL) { 596 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 597 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 598 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 599 } 600 601 snd_hdac_set_codec_wakeup(bus, false); 602 603 /* reduce dma latency to avoid noise */ 604 if (IS_BXT(pci)) 605 bxt_reduce_dma_latency(chip); 606 607 if (bus->mlcap != NULL) 608 intel_init_lctl(chip); 609 } 610 611 /* calculate runtime delay from LPIB */ 612 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 613 unsigned int pos) 614 { 615 struct snd_pcm_substream *substream = azx_dev->core.substream; 616 int stream = substream->stream; 617 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 618 int delay; 619 620 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 621 delay = pos - lpib_pos; 622 else 623 delay = lpib_pos - pos; 624 if (delay < 0) { 625 if (delay >= azx_dev->core.delay_negative_threshold) 626 delay = 0; 627 else 628 delay += azx_dev->core.bufsize; 629 } 630 631 if (delay >= azx_dev->core.period_bytes) { 632 dev_info(chip->card->dev, 633 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 634 delay, azx_dev->core.period_bytes); 635 delay = 0; 636 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 637 chip->get_delay[stream] = NULL; 638 } 639 640 return bytes_to_frames(substream->runtime, delay); 641 } 642 643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 644 645 /* called from IRQ */ 646 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 647 { 648 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 649 int ok; 650 651 ok = azx_position_ok(chip, azx_dev); 652 if (ok == 1) { 653 azx_dev->irq_pending = 0; 654 return ok; 655 } else if (ok == 0) { 656 /* bogus IRQ, process it later */ 657 azx_dev->irq_pending = 1; 658 schedule_work(&hda->irq_pending_work); 659 } 660 return 0; 661 } 662 663 #define display_power(chip, enable) \ 664 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 665 666 /* 667 * Check whether the current DMA position is acceptable for updating 668 * periods. Returns non-zero if it's OK. 669 * 670 * Many HD-audio controllers appear pretty inaccurate about 671 * the update-IRQ timing. The IRQ is issued before actually the 672 * data is processed. So, we need to process it afterwords in a 673 * workqueue. 674 */ 675 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 676 { 677 struct snd_pcm_substream *substream = azx_dev->core.substream; 678 int stream = substream->stream; 679 u32 wallclk; 680 unsigned int pos; 681 682 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 683 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 684 return -1; /* bogus (too early) interrupt */ 685 686 if (chip->get_position[stream]) 687 pos = chip->get_position[stream](chip, azx_dev); 688 else { /* use the position buffer as default */ 689 pos = azx_get_pos_posbuf(chip, azx_dev); 690 if (!pos || pos == (u32)-1) { 691 dev_info(chip->card->dev, 692 "Invalid position buffer, using LPIB read method instead.\n"); 693 chip->get_position[stream] = azx_get_pos_lpib; 694 if (chip->get_position[0] == azx_get_pos_lpib && 695 chip->get_position[1] == azx_get_pos_lpib) 696 azx_bus(chip)->use_posbuf = false; 697 pos = azx_get_pos_lpib(chip, azx_dev); 698 chip->get_delay[stream] = NULL; 699 } else { 700 chip->get_position[stream] = azx_get_pos_posbuf; 701 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 702 chip->get_delay[stream] = azx_get_delay_from_lpib; 703 } 704 } 705 706 if (pos >= azx_dev->core.bufsize) 707 pos = 0; 708 709 if (WARN_ONCE(!azx_dev->core.period_bytes, 710 "hda-intel: zero azx_dev->period_bytes")) 711 return -1; /* this shouldn't happen! */ 712 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 713 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 714 /* NG - it's below the first next period boundary */ 715 return chip->bdl_pos_adj ? 0 : -1; 716 azx_dev->core.start_wallclk += wallclk; 717 return 1; /* OK, it's fine */ 718 } 719 720 /* 721 * The work for pending PCM period updates. 722 */ 723 static void azx_irq_pending_work(struct work_struct *work) 724 { 725 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 726 struct azx *chip = &hda->chip; 727 struct hdac_bus *bus = azx_bus(chip); 728 struct hdac_stream *s; 729 int pending, ok; 730 731 if (!hda->irq_pending_warned) { 732 dev_info(chip->card->dev, 733 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 734 chip->card->number); 735 hda->irq_pending_warned = 1; 736 } 737 738 for (;;) { 739 pending = 0; 740 spin_lock_irq(&bus->reg_lock); 741 list_for_each_entry(s, &bus->stream_list, list) { 742 struct azx_dev *azx_dev = stream_to_azx_dev(s); 743 if (!azx_dev->irq_pending || 744 !s->substream || 745 !s->running) 746 continue; 747 ok = azx_position_ok(chip, azx_dev); 748 if (ok > 0) { 749 azx_dev->irq_pending = 0; 750 spin_unlock(&bus->reg_lock); 751 snd_pcm_period_elapsed(s->substream); 752 spin_lock(&bus->reg_lock); 753 } else if (ok < 0) { 754 pending = 0; /* too early */ 755 } else 756 pending++; 757 } 758 spin_unlock_irq(&bus->reg_lock); 759 if (!pending) 760 return; 761 msleep(1); 762 } 763 } 764 765 /* clear irq_pending flags and assure no on-going workq */ 766 static void azx_clear_irq_pending(struct azx *chip) 767 { 768 struct hdac_bus *bus = azx_bus(chip); 769 struct hdac_stream *s; 770 771 spin_lock_irq(&bus->reg_lock); 772 list_for_each_entry(s, &bus->stream_list, list) { 773 struct azx_dev *azx_dev = stream_to_azx_dev(s); 774 azx_dev->irq_pending = 0; 775 } 776 spin_unlock_irq(&bus->reg_lock); 777 } 778 779 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 780 { 781 struct hdac_bus *bus = azx_bus(chip); 782 783 if (request_irq(chip->pci->irq, azx_interrupt, 784 chip->msi ? 0 : IRQF_SHARED, 785 chip->card->irq_descr, chip)) { 786 dev_err(chip->card->dev, 787 "unable to grab IRQ %d, disabling device\n", 788 chip->pci->irq); 789 if (do_disconnect) 790 snd_card_disconnect(chip->card); 791 return -1; 792 } 793 bus->irq = chip->pci->irq; 794 chip->card->sync_irq = bus->irq; 795 pci_intx(chip->pci, !chip->msi); 796 return 0; 797 } 798 799 /* get the current DMA position with correction on VIA chips */ 800 static unsigned int azx_via_get_position(struct azx *chip, 801 struct azx_dev *azx_dev) 802 { 803 unsigned int link_pos, mini_pos, bound_pos; 804 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 805 unsigned int fifo_size; 806 807 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 808 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 809 /* Playback, no problem using link position */ 810 return link_pos; 811 } 812 813 /* Capture */ 814 /* For new chipset, 815 * use mod to get the DMA position just like old chipset 816 */ 817 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 818 mod_dma_pos %= azx_dev->core.period_bytes; 819 820 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 821 822 if (azx_dev->insufficient) { 823 /* Link position never gather than FIFO size */ 824 if (link_pos <= fifo_size) 825 return 0; 826 827 azx_dev->insufficient = 0; 828 } 829 830 if (link_pos <= fifo_size) 831 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 832 else 833 mini_pos = link_pos - fifo_size; 834 835 /* Find nearest previous boudary */ 836 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 837 mod_link_pos = link_pos % azx_dev->core.period_bytes; 838 if (mod_link_pos >= fifo_size) 839 bound_pos = link_pos - mod_link_pos; 840 else if (mod_dma_pos >= mod_mini_pos) 841 bound_pos = mini_pos - mod_mini_pos; 842 else { 843 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 844 if (bound_pos >= azx_dev->core.bufsize) 845 bound_pos = 0; 846 } 847 848 /* Calculate real DMA position we want */ 849 return bound_pos + mod_dma_pos; 850 } 851 852 #define AMD_FIFO_SIZE 32 853 854 /* get the current DMA position with FIFO size correction */ 855 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 856 { 857 struct snd_pcm_substream *substream = azx_dev->core.substream; 858 struct snd_pcm_runtime *runtime = substream->runtime; 859 unsigned int pos, delay; 860 861 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 862 if (!runtime) 863 return pos; 864 865 runtime->delay = AMD_FIFO_SIZE; 866 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 867 if (azx_dev->insufficient) { 868 if (pos < delay) { 869 delay = pos; 870 runtime->delay = bytes_to_frames(runtime, pos); 871 } else { 872 azx_dev->insufficient = 0; 873 } 874 } 875 876 /* correct the DMA position for capture stream */ 877 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 878 if (pos < delay) 879 pos += azx_dev->core.bufsize; 880 pos -= delay; 881 } 882 883 return pos; 884 } 885 886 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 887 unsigned int pos) 888 { 889 struct snd_pcm_substream *substream = azx_dev->core.substream; 890 891 /* just read back the calculated value in the above */ 892 return substream->runtime->delay; 893 } 894 895 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 896 struct azx_dev *azx_dev) 897 { 898 return _snd_hdac_chip_readl(azx_bus(chip), 899 AZX_REG_VS_SDXDPIB_XBASE + 900 (AZX_REG_VS_SDXDPIB_XINTERVAL * 901 azx_dev->core.index)); 902 } 903 904 /* get the current DMA position with correction on SKL+ chips */ 905 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 906 { 907 /* DPIB register gives a more accurate position for playback */ 908 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 909 return azx_skl_get_dpib_pos(chip, azx_dev); 910 911 /* For capture, we need to read posbuf, but it requires a delay 912 * for the possible boundary overlap; the read of DPIB fetches the 913 * actual posbuf 914 */ 915 udelay(20); 916 azx_skl_get_dpib_pos(chip, azx_dev); 917 return azx_get_pos_posbuf(chip, azx_dev); 918 } 919 920 #ifdef CONFIG_PM 921 static DEFINE_MUTEX(card_list_lock); 922 static LIST_HEAD(card_list); 923 924 static void azx_add_card_list(struct azx *chip) 925 { 926 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 927 mutex_lock(&card_list_lock); 928 list_add(&hda->list, &card_list); 929 mutex_unlock(&card_list_lock); 930 } 931 932 static void azx_del_card_list(struct azx *chip) 933 { 934 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 935 mutex_lock(&card_list_lock); 936 list_del_init(&hda->list); 937 mutex_unlock(&card_list_lock); 938 } 939 940 /* trigger power-save check at writing parameter */ 941 static int param_set_xint(const char *val, const struct kernel_param *kp) 942 { 943 struct hda_intel *hda; 944 struct azx *chip; 945 int prev = power_save; 946 int ret = param_set_int(val, kp); 947 948 if (ret || prev == power_save) 949 return ret; 950 951 mutex_lock(&card_list_lock); 952 list_for_each_entry(hda, &card_list, list) { 953 chip = &hda->chip; 954 if (!hda->probe_continued || chip->disabled) 955 continue; 956 snd_hda_set_power_save(&chip->bus, power_save * 1000); 957 } 958 mutex_unlock(&card_list_lock); 959 return 0; 960 } 961 962 /* 963 * power management 964 */ 965 static bool azx_is_pm_ready(struct snd_card *card) 966 { 967 struct azx *chip; 968 struct hda_intel *hda; 969 970 if (!card) 971 return false; 972 chip = card->private_data; 973 hda = container_of(chip, struct hda_intel, chip); 974 if (chip->disabled || hda->init_failed || !chip->running) 975 return false; 976 return true; 977 } 978 979 static void __azx_runtime_suspend(struct azx *chip) 980 { 981 azx_stop_chip(chip); 982 azx_enter_link_reset(chip); 983 azx_clear_irq_pending(chip); 984 display_power(chip, false); 985 } 986 987 static void __azx_runtime_resume(struct azx *chip, bool from_rt) 988 { 989 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 990 struct hdac_bus *bus = azx_bus(chip); 991 struct hda_codec *codec; 992 int status; 993 994 display_power(chip, true); 995 if (hda->need_i915_power) 996 snd_hdac_i915_set_bclk(bus); 997 998 /* Read STATESTS before controller reset */ 999 status = azx_readw(chip, STATESTS); 1000 1001 azx_init_pci(chip); 1002 hda_intel_init_chip(chip, true); 1003 1004 if (status && from_rt) { 1005 list_for_each_codec(codec, &chip->bus) 1006 if (status & (1 << codec->addr)) 1007 schedule_delayed_work(&codec->jackpoll_work, 1008 codec->jackpoll_interval); 1009 } 1010 1011 /* power down again for link-controlled chips */ 1012 if (!hda->need_i915_power) 1013 display_power(chip, false); 1014 } 1015 1016 #ifdef CONFIG_PM_SLEEP 1017 static int azx_suspend(struct device *dev) 1018 { 1019 struct snd_card *card = dev_get_drvdata(dev); 1020 struct azx *chip; 1021 struct hdac_bus *bus; 1022 1023 if (!azx_is_pm_ready(card)) 1024 return 0; 1025 1026 chip = card->private_data; 1027 bus = azx_bus(chip); 1028 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1029 __azx_runtime_suspend(chip); 1030 if (bus->irq >= 0) { 1031 free_irq(bus->irq, chip); 1032 bus->irq = -1; 1033 chip->card->sync_irq = -1; 1034 } 1035 1036 if (chip->msi) 1037 pci_disable_msi(chip->pci); 1038 1039 trace_azx_suspend(chip); 1040 return 0; 1041 } 1042 1043 static int azx_resume(struct device *dev) 1044 { 1045 struct snd_card *card = dev_get_drvdata(dev); 1046 struct azx *chip; 1047 1048 if (!azx_is_pm_ready(card)) 1049 return 0; 1050 1051 chip = card->private_data; 1052 if (chip->msi) 1053 if (pci_enable_msi(chip->pci) < 0) 1054 chip->msi = 0; 1055 if (azx_acquire_irq(chip, 1) < 0) 1056 return -EIO; 1057 __azx_runtime_resume(chip, false); 1058 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1059 1060 trace_azx_resume(chip); 1061 return 0; 1062 } 1063 1064 /* put codec down to D3 at hibernation for Intel SKL+; 1065 * otherwise BIOS may still access the codec and screw up the driver 1066 */ 1067 static int azx_freeze_noirq(struct device *dev) 1068 { 1069 struct snd_card *card = dev_get_drvdata(dev); 1070 struct azx *chip = card->private_data; 1071 struct pci_dev *pci = to_pci_dev(dev); 1072 1073 if (chip->driver_type == AZX_DRIVER_SKL) 1074 pci_set_power_state(pci, PCI_D3hot); 1075 1076 return 0; 1077 } 1078 1079 static int azx_thaw_noirq(struct device *dev) 1080 { 1081 struct snd_card *card = dev_get_drvdata(dev); 1082 struct azx *chip = card->private_data; 1083 struct pci_dev *pci = to_pci_dev(dev); 1084 1085 if (chip->driver_type == AZX_DRIVER_SKL) 1086 pci_set_power_state(pci, PCI_D0); 1087 1088 return 0; 1089 } 1090 #endif /* CONFIG_PM_SLEEP */ 1091 1092 static int azx_runtime_suspend(struct device *dev) 1093 { 1094 struct snd_card *card = dev_get_drvdata(dev); 1095 struct azx *chip; 1096 1097 if (!azx_is_pm_ready(card)) 1098 return 0; 1099 chip = card->private_data; 1100 if (!azx_has_pm_runtime(chip)) 1101 return 0; 1102 1103 /* enable controller wake up event */ 1104 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 1105 STATESTS_INT_MASK); 1106 1107 __azx_runtime_suspend(chip); 1108 trace_azx_runtime_suspend(chip); 1109 return 0; 1110 } 1111 1112 static int azx_runtime_resume(struct device *dev) 1113 { 1114 struct snd_card *card = dev_get_drvdata(dev); 1115 struct azx *chip; 1116 1117 if (!azx_is_pm_ready(card)) 1118 return 0; 1119 chip = card->private_data; 1120 if (!azx_has_pm_runtime(chip)) 1121 return 0; 1122 __azx_runtime_resume(chip, true); 1123 1124 /* disable controller Wake Up event*/ 1125 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1126 ~STATESTS_INT_MASK); 1127 1128 trace_azx_runtime_resume(chip); 1129 return 0; 1130 } 1131 1132 static int azx_runtime_idle(struct device *dev) 1133 { 1134 struct snd_card *card = dev_get_drvdata(dev); 1135 struct azx *chip; 1136 struct hda_intel *hda; 1137 1138 if (!card) 1139 return 0; 1140 1141 chip = card->private_data; 1142 hda = container_of(chip, struct hda_intel, chip); 1143 if (chip->disabled || hda->init_failed) 1144 return 0; 1145 1146 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1147 azx_bus(chip)->codec_powered || !chip->running) 1148 return -EBUSY; 1149 1150 /* ELD notification gets broken when HD-audio bus is off */ 1151 if (needs_eld_notify_link(chip)) 1152 return -EBUSY; 1153 1154 return 0; 1155 } 1156 1157 static const struct dev_pm_ops azx_pm = { 1158 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1159 #ifdef CONFIG_PM_SLEEP 1160 .freeze_noirq = azx_freeze_noirq, 1161 .thaw_noirq = azx_thaw_noirq, 1162 #endif 1163 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1164 }; 1165 1166 #define AZX_PM_OPS &azx_pm 1167 #else 1168 #define azx_add_card_list(chip) /* NOP */ 1169 #define azx_del_card_list(chip) /* NOP */ 1170 #define AZX_PM_OPS NULL 1171 #endif /* CONFIG_PM */ 1172 1173 1174 static int azx_probe_continue(struct azx *chip); 1175 1176 #ifdef SUPPORT_VGA_SWITCHEROO 1177 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1178 1179 static void azx_vs_set_state(struct pci_dev *pci, 1180 enum vga_switcheroo_state state) 1181 { 1182 struct snd_card *card = pci_get_drvdata(pci); 1183 struct azx *chip = card->private_data; 1184 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1185 struct hda_codec *codec; 1186 bool disabled; 1187 1188 wait_for_completion(&hda->probe_wait); 1189 if (hda->init_failed) 1190 return; 1191 1192 disabled = (state == VGA_SWITCHEROO_OFF); 1193 if (chip->disabled == disabled) 1194 return; 1195 1196 if (!hda->probe_continued) { 1197 chip->disabled = disabled; 1198 if (!disabled) { 1199 dev_info(chip->card->dev, 1200 "Start delayed initialization\n"); 1201 if (azx_probe_continue(chip) < 0) { 1202 dev_err(chip->card->dev, "initialization error\n"); 1203 hda->init_failed = true; 1204 } 1205 } 1206 } else { 1207 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1208 disabled ? "Disabling" : "Enabling"); 1209 if (disabled) { 1210 list_for_each_codec(codec, &chip->bus) { 1211 pm_runtime_suspend(hda_codec_dev(codec)); 1212 pm_runtime_disable(hda_codec_dev(codec)); 1213 } 1214 pm_runtime_suspend(card->dev); 1215 pm_runtime_disable(card->dev); 1216 /* when we get suspended by vga_switcheroo we end up in D3cold, 1217 * however we have no ACPI handle, so pci/acpi can't put us there, 1218 * put ourselves there */ 1219 pci->current_state = PCI_D3cold; 1220 chip->disabled = true; 1221 if (snd_hda_lock_devices(&chip->bus)) 1222 dev_warn(chip->card->dev, 1223 "Cannot lock devices!\n"); 1224 } else { 1225 snd_hda_unlock_devices(&chip->bus); 1226 chip->disabled = false; 1227 pm_runtime_enable(card->dev); 1228 list_for_each_codec(codec, &chip->bus) { 1229 pm_runtime_enable(hda_codec_dev(codec)); 1230 pm_runtime_resume(hda_codec_dev(codec)); 1231 } 1232 } 1233 } 1234 } 1235 1236 static bool azx_vs_can_switch(struct pci_dev *pci) 1237 { 1238 struct snd_card *card = pci_get_drvdata(pci); 1239 struct azx *chip = card->private_data; 1240 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1241 1242 wait_for_completion(&hda->probe_wait); 1243 if (hda->init_failed) 1244 return false; 1245 if (chip->disabled || !hda->probe_continued) 1246 return true; 1247 if (snd_hda_lock_devices(&chip->bus)) 1248 return false; 1249 snd_hda_unlock_devices(&chip->bus); 1250 return true; 1251 } 1252 1253 /* 1254 * The discrete GPU cannot power down unless the HDA controller runtime 1255 * suspends, so activate runtime PM on codecs even if power_save == 0. 1256 */ 1257 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1258 { 1259 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1260 struct hda_codec *codec; 1261 1262 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1263 list_for_each_codec(codec, &chip->bus) 1264 codec->auto_runtime_pm = 1; 1265 /* reset the power save setup */ 1266 if (chip->running) 1267 set_default_power_save(chip); 1268 } 1269 } 1270 1271 static void azx_vs_gpu_bound(struct pci_dev *pci, 1272 enum vga_switcheroo_client_id client_id) 1273 { 1274 struct snd_card *card = pci_get_drvdata(pci); 1275 struct azx *chip = card->private_data; 1276 1277 if (client_id == VGA_SWITCHEROO_DIS) 1278 chip->bus.keep_power = 0; 1279 setup_vga_switcheroo_runtime_pm(chip); 1280 } 1281 1282 static void init_vga_switcheroo(struct azx *chip) 1283 { 1284 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1285 struct pci_dev *p = get_bound_vga(chip->pci); 1286 struct pci_dev *parent; 1287 if (p) { 1288 dev_info(chip->card->dev, 1289 "Handle vga_switcheroo audio client\n"); 1290 hda->use_vga_switcheroo = 1; 1291 1292 /* cleared in either gpu_bound op or codec probe, or when its 1293 * upstream port has _PR3 (i.e. dGPU). 1294 */ 1295 parent = pci_upstream_bridge(p); 1296 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1297 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1298 pci_dev_put(p); 1299 } 1300 } 1301 1302 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1303 .set_gpu_state = azx_vs_set_state, 1304 .can_switch = azx_vs_can_switch, 1305 .gpu_bound = azx_vs_gpu_bound, 1306 }; 1307 1308 static int register_vga_switcheroo(struct azx *chip) 1309 { 1310 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1311 struct pci_dev *p; 1312 int err; 1313 1314 if (!hda->use_vga_switcheroo) 1315 return 0; 1316 1317 p = get_bound_vga(chip->pci); 1318 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1319 pci_dev_put(p); 1320 1321 if (err < 0) 1322 return err; 1323 hda->vga_switcheroo_registered = 1; 1324 1325 return 0; 1326 } 1327 #else 1328 #define init_vga_switcheroo(chip) /* NOP */ 1329 #define register_vga_switcheroo(chip) 0 1330 #define check_hdmi_disabled(pci) false 1331 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1332 #endif /* SUPPORT_VGA_SWITCHER */ 1333 1334 /* 1335 * destructor 1336 */ 1337 static int azx_free(struct azx *chip) 1338 { 1339 struct pci_dev *pci = chip->pci; 1340 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1341 struct hdac_bus *bus = azx_bus(chip); 1342 1343 if (azx_has_pm_runtime(chip) && chip->running) 1344 pm_runtime_get_noresume(&pci->dev); 1345 chip->running = 0; 1346 1347 azx_del_card_list(chip); 1348 1349 hda->init_failed = 1; /* to be sure */ 1350 complete_all(&hda->probe_wait); 1351 1352 if (use_vga_switcheroo(hda)) { 1353 if (chip->disabled && hda->probe_continued) 1354 snd_hda_unlock_devices(&chip->bus); 1355 if (hda->vga_switcheroo_registered) 1356 vga_switcheroo_unregister_client(chip->pci); 1357 } 1358 1359 if (bus->chip_init) { 1360 azx_clear_irq_pending(chip); 1361 azx_stop_all_streams(chip); 1362 azx_stop_chip(chip); 1363 } 1364 1365 if (bus->irq >= 0) 1366 free_irq(bus->irq, (void*)chip); 1367 if (chip->msi) 1368 pci_disable_msi(chip->pci); 1369 iounmap(bus->remap_addr); 1370 1371 azx_free_stream_pages(chip); 1372 azx_free_streams(chip); 1373 snd_hdac_bus_exit(bus); 1374 1375 if (chip->region_requested) 1376 pci_release_regions(chip->pci); 1377 1378 pci_disable_device(chip->pci); 1379 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1380 release_firmware(chip->fw); 1381 #endif 1382 display_power(chip, false); 1383 1384 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1385 snd_hdac_i915_exit(bus); 1386 kfree(hda); 1387 1388 return 0; 1389 } 1390 1391 static int azx_dev_disconnect(struct snd_device *device) 1392 { 1393 struct azx *chip = device->device_data; 1394 struct hdac_bus *bus = azx_bus(chip); 1395 1396 chip->bus.shutdown = 1; 1397 cancel_work_sync(&bus->unsol_work); 1398 1399 return 0; 1400 } 1401 1402 static int azx_dev_free(struct snd_device *device) 1403 { 1404 return azx_free(device->device_data); 1405 } 1406 1407 #ifdef SUPPORT_VGA_SWITCHEROO 1408 #ifdef CONFIG_ACPI 1409 /* ATPX is in the integrated GPU's namespace */ 1410 static bool atpx_present(void) 1411 { 1412 struct pci_dev *pdev = NULL; 1413 acpi_handle dhandle, atpx_handle; 1414 acpi_status status; 1415 1416 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 1417 dhandle = ACPI_HANDLE(&pdev->dev); 1418 if (dhandle) { 1419 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1420 if (!ACPI_FAILURE(status)) { 1421 pci_dev_put(pdev); 1422 return true; 1423 } 1424 } 1425 } 1426 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 1427 dhandle = ACPI_HANDLE(&pdev->dev); 1428 if (dhandle) { 1429 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1430 if (!ACPI_FAILURE(status)) { 1431 pci_dev_put(pdev); 1432 return true; 1433 } 1434 } 1435 } 1436 return false; 1437 } 1438 #else 1439 static bool atpx_present(void) 1440 { 1441 return false; 1442 } 1443 #endif 1444 1445 /* 1446 * Check of disabled HDMI controller by vga_switcheroo 1447 */ 1448 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1449 { 1450 struct pci_dev *p; 1451 1452 /* check only discrete GPU */ 1453 switch (pci->vendor) { 1454 case PCI_VENDOR_ID_ATI: 1455 case PCI_VENDOR_ID_AMD: 1456 if (pci->devfn == 1) { 1457 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1458 pci->bus->number, 0); 1459 if (p) { 1460 /* ATPX is in the integrated GPU's ACPI namespace 1461 * rather than the dGPU's namespace. However, 1462 * the dGPU is the one who is involved in 1463 * vgaswitcheroo. 1464 */ 1465 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1466 atpx_present()) 1467 return p; 1468 pci_dev_put(p); 1469 } 1470 } 1471 break; 1472 case PCI_VENDOR_ID_NVIDIA: 1473 if (pci->devfn == 1) { 1474 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1475 pci->bus->number, 0); 1476 if (p) { 1477 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1478 return p; 1479 pci_dev_put(p); 1480 } 1481 } 1482 break; 1483 } 1484 return NULL; 1485 } 1486 1487 static bool check_hdmi_disabled(struct pci_dev *pci) 1488 { 1489 bool vga_inactive = false; 1490 struct pci_dev *p = get_bound_vga(pci); 1491 1492 if (p) { 1493 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1494 vga_inactive = true; 1495 pci_dev_put(p); 1496 } 1497 return vga_inactive; 1498 } 1499 #endif /* SUPPORT_VGA_SWITCHEROO */ 1500 1501 /* 1502 * white/black-listing for position_fix 1503 */ 1504 static const struct snd_pci_quirk position_fix_list[] = { 1505 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1506 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1507 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1508 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1509 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1510 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1511 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1512 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1513 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1514 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1515 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1516 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1517 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1518 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1519 {} 1520 }; 1521 1522 static int check_position_fix(struct azx *chip, int fix) 1523 { 1524 const struct snd_pci_quirk *q; 1525 1526 switch (fix) { 1527 case POS_FIX_AUTO: 1528 case POS_FIX_LPIB: 1529 case POS_FIX_POSBUF: 1530 case POS_FIX_VIACOMBO: 1531 case POS_FIX_COMBO: 1532 case POS_FIX_SKL: 1533 case POS_FIX_FIFO: 1534 return fix; 1535 } 1536 1537 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1538 if (q) { 1539 dev_info(chip->card->dev, 1540 "position_fix set to %d for device %04x:%04x\n", 1541 q->value, q->subvendor, q->subdevice); 1542 return q->value; 1543 } 1544 1545 /* Check VIA/ATI HD Audio Controller exist */ 1546 if (chip->driver_type == AZX_DRIVER_VIA) { 1547 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1548 return POS_FIX_VIACOMBO; 1549 } 1550 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1551 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1552 return POS_FIX_FIFO; 1553 } 1554 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1555 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1556 return POS_FIX_LPIB; 1557 } 1558 if (chip->driver_type == AZX_DRIVER_SKL) { 1559 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1560 return POS_FIX_SKL; 1561 } 1562 return POS_FIX_AUTO; 1563 } 1564 1565 static void assign_position_fix(struct azx *chip, int fix) 1566 { 1567 static const azx_get_pos_callback_t callbacks[] = { 1568 [POS_FIX_AUTO] = NULL, 1569 [POS_FIX_LPIB] = azx_get_pos_lpib, 1570 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1571 [POS_FIX_VIACOMBO] = azx_via_get_position, 1572 [POS_FIX_COMBO] = azx_get_pos_lpib, 1573 [POS_FIX_SKL] = azx_get_pos_skl, 1574 [POS_FIX_FIFO] = azx_get_pos_fifo, 1575 }; 1576 1577 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1578 1579 /* combo mode uses LPIB only for playback */ 1580 if (fix == POS_FIX_COMBO) 1581 chip->get_position[1] = NULL; 1582 1583 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1584 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1585 chip->get_delay[0] = chip->get_delay[1] = 1586 azx_get_delay_from_lpib; 1587 } 1588 1589 if (fix == POS_FIX_FIFO) 1590 chip->get_delay[0] = chip->get_delay[1] = 1591 azx_get_delay_from_fifo; 1592 } 1593 1594 /* 1595 * black-lists for probe_mask 1596 */ 1597 static const struct snd_pci_quirk probe_mask_list[] = { 1598 /* Thinkpad often breaks the controller communication when accessing 1599 * to the non-working (or non-existing) modem codec slot. 1600 */ 1601 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1602 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1603 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1604 /* broken BIOS */ 1605 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1606 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1607 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1608 /* forced codec slots */ 1609 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1610 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1611 /* WinFast VP200 H (Teradici) user reported broken communication */ 1612 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1613 {} 1614 }; 1615 1616 #define AZX_FORCE_CODEC_MASK 0x100 1617 1618 static void check_probe_mask(struct azx *chip, int dev) 1619 { 1620 const struct snd_pci_quirk *q; 1621 1622 chip->codec_probe_mask = probe_mask[dev]; 1623 if (chip->codec_probe_mask == -1) { 1624 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1625 if (q) { 1626 dev_info(chip->card->dev, 1627 "probe_mask set to 0x%x for device %04x:%04x\n", 1628 q->value, q->subvendor, q->subdevice); 1629 chip->codec_probe_mask = q->value; 1630 } 1631 } 1632 1633 /* check forced option */ 1634 if (chip->codec_probe_mask != -1 && 1635 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1636 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1637 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1638 (int)azx_bus(chip)->codec_mask); 1639 } 1640 } 1641 1642 /* 1643 * white/black-list for enable_msi 1644 */ 1645 static const struct snd_pci_quirk msi_black_list[] = { 1646 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1647 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1648 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1649 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1650 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1651 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1652 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1653 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1654 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1655 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1656 {} 1657 }; 1658 1659 static void check_msi(struct azx *chip) 1660 { 1661 const struct snd_pci_quirk *q; 1662 1663 if (enable_msi >= 0) { 1664 chip->msi = !!enable_msi; 1665 return; 1666 } 1667 chip->msi = 1; /* enable MSI as default */ 1668 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1669 if (q) { 1670 dev_info(chip->card->dev, 1671 "msi for device %04x:%04x set to %d\n", 1672 q->subvendor, q->subdevice, q->value); 1673 chip->msi = q->value; 1674 return; 1675 } 1676 1677 /* NVidia chipsets seem to cause troubles with MSI */ 1678 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1679 dev_info(chip->card->dev, "Disabling MSI\n"); 1680 chip->msi = 0; 1681 } 1682 } 1683 1684 /* check the snoop mode availability */ 1685 static void azx_check_snoop_available(struct azx *chip) 1686 { 1687 int snoop = hda_snoop; 1688 1689 if (snoop >= 0) { 1690 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1691 snoop ? "snoop" : "non-snoop"); 1692 chip->snoop = snoop; 1693 chip->uc_buffer = !snoop; 1694 return; 1695 } 1696 1697 snoop = true; 1698 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1699 chip->driver_type == AZX_DRIVER_VIA) { 1700 /* force to non-snoop mode for a new VIA controller 1701 * when BIOS is set 1702 */ 1703 u8 val; 1704 pci_read_config_byte(chip->pci, 0x42, &val); 1705 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1706 chip->pci->revision == 0x20)) 1707 snoop = false; 1708 } 1709 1710 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1711 snoop = false; 1712 1713 chip->snoop = snoop; 1714 if (!snoop) { 1715 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1716 /* C-Media requires non-cached pages only for CORB/RIRB */ 1717 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1718 chip->uc_buffer = true; 1719 } 1720 } 1721 1722 static void azx_probe_work(struct work_struct *work) 1723 { 1724 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1725 azx_probe_continue(&hda->chip); 1726 } 1727 1728 static int default_bdl_pos_adj(struct azx *chip) 1729 { 1730 /* some exceptions: Atoms seem problematic with value 1 */ 1731 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1732 switch (chip->pci->device) { 1733 case 0x0f04: /* Baytrail */ 1734 case 0x2284: /* Braswell */ 1735 return 32; 1736 } 1737 } 1738 1739 switch (chip->driver_type) { 1740 case AZX_DRIVER_ICH: 1741 case AZX_DRIVER_PCH: 1742 return 1; 1743 default: 1744 return 32; 1745 } 1746 } 1747 1748 /* 1749 * constructor 1750 */ 1751 static const struct hda_controller_ops pci_hda_ops; 1752 1753 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1754 int dev, unsigned int driver_caps, 1755 struct azx **rchip) 1756 { 1757 static const struct snd_device_ops ops = { 1758 .dev_disconnect = azx_dev_disconnect, 1759 .dev_free = azx_dev_free, 1760 }; 1761 struct hda_intel *hda; 1762 struct azx *chip; 1763 int err; 1764 1765 *rchip = NULL; 1766 1767 err = pci_enable_device(pci); 1768 if (err < 0) 1769 return err; 1770 1771 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1772 if (!hda) { 1773 pci_disable_device(pci); 1774 return -ENOMEM; 1775 } 1776 1777 chip = &hda->chip; 1778 mutex_init(&chip->open_mutex); 1779 chip->card = card; 1780 chip->pci = pci; 1781 chip->ops = &pci_hda_ops; 1782 chip->driver_caps = driver_caps; 1783 chip->driver_type = driver_caps & 0xff; 1784 check_msi(chip); 1785 chip->dev_index = dev; 1786 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1787 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1788 INIT_LIST_HEAD(&chip->pcm_list); 1789 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1790 INIT_LIST_HEAD(&hda->list); 1791 init_vga_switcheroo(chip); 1792 init_completion(&hda->probe_wait); 1793 1794 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1795 1796 check_probe_mask(chip, dev); 1797 1798 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1799 chip->fallback_to_single_cmd = 1; 1800 else /* explicitly set to single_cmd or not */ 1801 chip->single_cmd = single_cmd; 1802 1803 azx_check_snoop_available(chip); 1804 1805 if (bdl_pos_adj[dev] < 0) 1806 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1807 else 1808 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1809 1810 err = azx_bus_init(chip, model[dev]); 1811 if (err < 0) { 1812 kfree(hda); 1813 pci_disable_device(pci); 1814 return err; 1815 } 1816 1817 /* use the non-cached pages in non-snoop mode */ 1818 if (!azx_snoop(chip)) 1819 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC; 1820 1821 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1822 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1823 chip->bus.core.needs_damn_long_delay = 1; 1824 } 1825 1826 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1827 if (err < 0) { 1828 dev_err(card->dev, "Error creating device [card]!\n"); 1829 azx_free(chip); 1830 return err; 1831 } 1832 1833 /* continue probing in work context as may trigger request module */ 1834 INIT_WORK(&hda->probe_work, azx_probe_work); 1835 1836 *rchip = chip; 1837 1838 return 0; 1839 } 1840 1841 static int azx_first_init(struct azx *chip) 1842 { 1843 int dev = chip->dev_index; 1844 struct pci_dev *pci = chip->pci; 1845 struct snd_card *card = chip->card; 1846 struct hdac_bus *bus = azx_bus(chip); 1847 int err; 1848 unsigned short gcap; 1849 unsigned int dma_bits = 64; 1850 1851 #if BITS_PER_LONG != 64 1852 /* Fix up base address on ULI M5461 */ 1853 if (chip->driver_type == AZX_DRIVER_ULI) { 1854 u16 tmp3; 1855 pci_read_config_word(pci, 0x40, &tmp3); 1856 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1857 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1858 } 1859 #endif 1860 1861 err = pci_request_regions(pci, "ICH HD audio"); 1862 if (err < 0) 1863 return err; 1864 chip->region_requested = 1; 1865 1866 bus->addr = pci_resource_start(pci, 0); 1867 bus->remap_addr = pci_ioremap_bar(pci, 0); 1868 if (bus->remap_addr == NULL) { 1869 dev_err(card->dev, "ioremap error\n"); 1870 return -ENXIO; 1871 } 1872 1873 if (chip->driver_type == AZX_DRIVER_SKL) 1874 snd_hdac_bus_parse_capabilities(bus); 1875 1876 /* 1877 * Some Intel CPUs has always running timer (ART) feature and 1878 * controller may have Global time sync reporting capability, so 1879 * check both of these before declaring synchronized time reporting 1880 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1881 */ 1882 chip->gts_present = false; 1883 1884 #ifdef CONFIG_X86 1885 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1886 chip->gts_present = true; 1887 #endif 1888 1889 if (chip->msi) { 1890 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1891 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1892 pci->no_64bit_msi = true; 1893 } 1894 if (pci_enable_msi(pci) < 0) 1895 chip->msi = 0; 1896 } 1897 1898 pci_set_master(pci); 1899 1900 gcap = azx_readw(chip, GCAP); 1901 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1902 1903 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1904 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1905 dma_bits = 40; 1906 1907 /* disable SB600 64bit support for safety */ 1908 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1909 struct pci_dev *p_smbus; 1910 dma_bits = 40; 1911 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1912 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1913 NULL); 1914 if (p_smbus) { 1915 if (p_smbus->revision < 0x30) 1916 gcap &= ~AZX_GCAP_64OK; 1917 pci_dev_put(p_smbus); 1918 } 1919 } 1920 1921 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1922 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1923 dma_bits = 40; 1924 1925 /* disable 64bit DMA address on some devices */ 1926 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1927 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1928 gcap &= ~AZX_GCAP_64OK; 1929 } 1930 1931 /* disable buffer size rounding to 128-byte multiples if supported */ 1932 if (align_buffer_size >= 0) 1933 chip->align_buffer_size = !!align_buffer_size; 1934 else { 1935 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1936 chip->align_buffer_size = 0; 1937 else 1938 chip->align_buffer_size = 1; 1939 } 1940 1941 /* allow 64bit DMA address if supported by H/W */ 1942 if (!(gcap & AZX_GCAP_64OK)) 1943 dma_bits = 32; 1944 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1945 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1946 } else { 1947 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1948 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1949 } 1950 1951 /* read number of streams from GCAP register instead of using 1952 * hardcoded value 1953 */ 1954 chip->capture_streams = (gcap >> 8) & 0x0f; 1955 chip->playback_streams = (gcap >> 12) & 0x0f; 1956 if (!chip->playback_streams && !chip->capture_streams) { 1957 /* gcap didn't give any info, switching to old method */ 1958 1959 switch (chip->driver_type) { 1960 case AZX_DRIVER_ULI: 1961 chip->playback_streams = ULI_NUM_PLAYBACK; 1962 chip->capture_streams = ULI_NUM_CAPTURE; 1963 break; 1964 case AZX_DRIVER_ATIHDMI: 1965 case AZX_DRIVER_ATIHDMI_NS: 1966 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1967 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1968 break; 1969 case AZX_DRIVER_GENERIC: 1970 default: 1971 chip->playback_streams = ICH6_NUM_PLAYBACK; 1972 chip->capture_streams = ICH6_NUM_CAPTURE; 1973 break; 1974 } 1975 } 1976 chip->capture_index_offset = 0; 1977 chip->playback_index_offset = chip->capture_streams; 1978 chip->num_streams = chip->playback_streams + chip->capture_streams; 1979 1980 /* sanity check for the SDxCTL.STRM field overflow */ 1981 if (chip->num_streams > 15 && 1982 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1983 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1984 "forcing separate stream tags", chip->num_streams); 1985 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1986 } 1987 1988 /* initialize streams */ 1989 err = azx_init_streams(chip); 1990 if (err < 0) 1991 return err; 1992 1993 err = azx_alloc_stream_pages(chip); 1994 if (err < 0) 1995 return err; 1996 1997 /* initialize chip */ 1998 azx_init_pci(chip); 1999 2000 snd_hdac_i915_set_bclk(bus); 2001 2002 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2003 2004 /* codec detection */ 2005 if (!azx_bus(chip)->codec_mask) { 2006 dev_err(card->dev, "no codecs found!\n"); 2007 return -ENODEV; 2008 } 2009 2010 if (azx_acquire_irq(chip, 0) < 0) 2011 return -EBUSY; 2012 2013 strcpy(card->driver, "HDA-Intel"); 2014 strlcpy(card->shortname, driver_short_names[chip->driver_type], 2015 sizeof(card->shortname)); 2016 snprintf(card->longname, sizeof(card->longname), 2017 "%s at 0x%lx irq %i", 2018 card->shortname, bus->addr, bus->irq); 2019 2020 return 0; 2021 } 2022 2023 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2024 /* callback from request_firmware_nowait() */ 2025 static void azx_firmware_cb(const struct firmware *fw, void *context) 2026 { 2027 struct snd_card *card = context; 2028 struct azx *chip = card->private_data; 2029 struct pci_dev *pci = chip->pci; 2030 2031 if (!fw) { 2032 dev_err(card->dev, "Cannot load firmware, aborting\n"); 2033 goto error; 2034 } 2035 2036 chip->fw = fw; 2037 if (!chip->disabled) { 2038 /* continue probing */ 2039 if (azx_probe_continue(chip)) 2040 goto error; 2041 } 2042 return; /* OK */ 2043 2044 error: 2045 snd_card_free(card); 2046 pci_set_drvdata(pci, NULL); 2047 } 2048 #endif 2049 2050 static int disable_msi_reset_irq(struct azx *chip) 2051 { 2052 struct hdac_bus *bus = azx_bus(chip); 2053 int err; 2054 2055 free_irq(bus->irq, chip); 2056 bus->irq = -1; 2057 chip->card->sync_irq = -1; 2058 pci_disable_msi(chip->pci); 2059 chip->msi = 0; 2060 err = azx_acquire_irq(chip, 1); 2061 if (err < 0) 2062 return err; 2063 2064 return 0; 2065 } 2066 2067 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2068 struct vm_area_struct *area) 2069 { 2070 #ifdef CONFIG_X86 2071 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2072 struct azx *chip = apcm->chip; 2073 if (chip->uc_buffer) 2074 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2075 #endif 2076 } 2077 2078 static const struct hda_controller_ops pci_hda_ops = { 2079 .disable_msi_reset_irq = disable_msi_reset_irq, 2080 .pcm_mmap_prepare = pcm_mmap_prepare, 2081 .position_check = azx_position_check, 2082 }; 2083 2084 static int azx_probe(struct pci_dev *pci, 2085 const struct pci_device_id *pci_id) 2086 { 2087 static int dev; 2088 struct snd_card *card; 2089 struct hda_intel *hda; 2090 struct azx *chip; 2091 bool schedule_probe; 2092 int err; 2093 2094 if (dev >= SNDRV_CARDS) 2095 return -ENODEV; 2096 if (!enable[dev]) { 2097 dev++; 2098 return -ENOENT; 2099 } 2100 2101 /* 2102 * stop probe if another Intel's DSP driver should be activated 2103 */ 2104 if (dsp_driver) { 2105 err = snd_intel_dsp_driver_probe(pci); 2106 if (err != SND_INTEL_DSP_DRIVER_ANY && 2107 err != SND_INTEL_DSP_DRIVER_LEGACY) 2108 return -ENODEV; 2109 } 2110 2111 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2112 0, &card); 2113 if (err < 0) { 2114 dev_err(&pci->dev, "Error creating card!\n"); 2115 return err; 2116 } 2117 2118 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2119 if (err < 0) 2120 goto out_free; 2121 card->private_data = chip; 2122 hda = container_of(chip, struct hda_intel, chip); 2123 2124 pci_set_drvdata(pci, card); 2125 2126 err = register_vga_switcheroo(chip); 2127 if (err < 0) { 2128 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2129 goto out_free; 2130 } 2131 2132 if (check_hdmi_disabled(pci)) { 2133 dev_info(card->dev, "VGA controller is disabled\n"); 2134 dev_info(card->dev, "Delaying initialization\n"); 2135 chip->disabled = true; 2136 } 2137 2138 schedule_probe = !chip->disabled; 2139 2140 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2141 if (patch[dev] && *patch[dev]) { 2142 dev_info(card->dev, "Applying patch firmware '%s'\n", 2143 patch[dev]); 2144 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2145 &pci->dev, GFP_KERNEL, card, 2146 azx_firmware_cb); 2147 if (err < 0) 2148 goto out_free; 2149 schedule_probe = false; /* continued in azx_firmware_cb() */ 2150 } 2151 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2152 2153 #ifndef CONFIG_SND_HDA_I915 2154 if (CONTROLLER_IN_GPU(pci)) 2155 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2156 #endif 2157 2158 if (schedule_probe) 2159 schedule_work(&hda->probe_work); 2160 2161 dev++; 2162 if (chip->disabled) 2163 complete_all(&hda->probe_wait); 2164 return 0; 2165 2166 out_free: 2167 snd_card_free(card); 2168 return err; 2169 } 2170 2171 #ifdef CONFIG_PM 2172 /* On some boards setting power_save to a non 0 value leads to clicking / 2173 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2174 * figure out how to avoid these sounds, but that is not always feasible. 2175 * So we keep a list of devices where we disable powersaving as its known 2176 * to causes problems on these devices. 2177 */ 2178 static const struct snd_pci_quirk power_save_blacklist[] = { 2179 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2180 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2181 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2182 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2183 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2184 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2185 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2186 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2187 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ 2188 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), 2189 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2190 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2191 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2192 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2193 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2194 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2195 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2196 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2197 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2198 /* https://bugs.launchpad.net/bugs/1821663 */ 2199 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2200 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2201 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2202 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2203 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2204 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2205 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2206 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2207 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2208 /* https://bugs.launchpad.net/bugs/1821663 */ 2209 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2210 {} 2211 }; 2212 #endif /* CONFIG_PM */ 2213 2214 static void set_default_power_save(struct azx *chip) 2215 { 2216 int val = power_save; 2217 2218 #ifdef CONFIG_PM 2219 if (pm_blacklist) { 2220 const struct snd_pci_quirk *q; 2221 2222 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist); 2223 if (q && val) { 2224 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n", 2225 q->subvendor, q->subdevice); 2226 val = 0; 2227 } 2228 } 2229 #endif /* CONFIG_PM */ 2230 snd_hda_set_power_save(&chip->bus, val * 1000); 2231 } 2232 2233 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2234 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2235 [AZX_DRIVER_NVIDIA] = 8, 2236 [AZX_DRIVER_TERA] = 1, 2237 }; 2238 2239 static int azx_probe_continue(struct azx *chip) 2240 { 2241 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2242 struct hdac_bus *bus = azx_bus(chip); 2243 struct pci_dev *pci = chip->pci; 2244 int dev = chip->dev_index; 2245 int err; 2246 2247 to_hda_bus(bus)->bus_probing = 1; 2248 hda->probe_continued = 1; 2249 2250 /* bind with i915 if needed */ 2251 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2252 err = snd_hdac_i915_init(bus); 2253 if (err < 0) { 2254 /* if the controller is bound only with HDMI/DP 2255 * (for HSW and BDW), we need to abort the probe; 2256 * for other chips, still continue probing as other 2257 * codecs can be on the same link. 2258 */ 2259 if (CONTROLLER_IN_GPU(pci)) { 2260 dev_err(chip->card->dev, 2261 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2262 goto out_free; 2263 } else { 2264 /* don't bother any longer */ 2265 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2266 } 2267 } 2268 2269 /* HSW/BDW controllers need this power */ 2270 if (CONTROLLER_IN_GPU(pci)) 2271 hda->need_i915_power = 1; 2272 } 2273 2274 /* Request display power well for the HDA controller or codec. For 2275 * Haswell/Broadwell, both the display HDA controller and codec need 2276 * this power. For other platforms, like Baytrail/Braswell, only the 2277 * display codec needs the power and it can be released after probe. 2278 */ 2279 display_power(chip, true); 2280 2281 err = azx_first_init(chip); 2282 if (err < 0) 2283 goto out_free; 2284 2285 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2286 chip->beep_mode = beep_mode[dev]; 2287 #endif 2288 2289 /* create codec instances */ 2290 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2291 if (err < 0) 2292 goto out_free; 2293 2294 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2295 if (chip->fw) { 2296 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2297 chip->fw->data); 2298 if (err < 0) 2299 goto out_free; 2300 #ifndef CONFIG_PM 2301 release_firmware(chip->fw); /* no longer needed */ 2302 chip->fw = NULL; 2303 #endif 2304 } 2305 #endif 2306 if ((probe_only[dev] & 1) == 0) { 2307 err = azx_codec_configure(chip); 2308 if (err < 0) 2309 goto out_free; 2310 } 2311 2312 err = snd_card_register(chip->card); 2313 if (err < 0) 2314 goto out_free; 2315 2316 setup_vga_switcheroo_runtime_pm(chip); 2317 2318 chip->running = 1; 2319 azx_add_card_list(chip); 2320 2321 set_default_power_save(chip); 2322 2323 if (azx_has_pm_runtime(chip)) 2324 pm_runtime_put_autosuspend(&pci->dev); 2325 2326 out_free: 2327 if (err < 0 || !hda->need_i915_power) 2328 display_power(chip, false); 2329 if (err < 0) 2330 hda->init_failed = 1; 2331 complete_all(&hda->probe_wait); 2332 to_hda_bus(bus)->bus_probing = 0; 2333 return err; 2334 } 2335 2336 static void azx_remove(struct pci_dev *pci) 2337 { 2338 struct snd_card *card = pci_get_drvdata(pci); 2339 struct azx *chip; 2340 struct hda_intel *hda; 2341 2342 if (card) { 2343 /* cancel the pending probing work */ 2344 chip = card->private_data; 2345 hda = container_of(chip, struct hda_intel, chip); 2346 /* FIXME: below is an ugly workaround. 2347 * Both device_release_driver() and driver_probe_device() 2348 * take *both* the device's and its parent's lock before 2349 * calling the remove() and probe() callbacks. The codec 2350 * probe takes the locks of both the codec itself and its 2351 * parent, i.e. the PCI controller dev. Meanwhile, when 2352 * the PCI controller is unbound, it takes its lock, too 2353 * ==> ouch, a deadlock! 2354 * As a workaround, we unlock temporarily here the controller 2355 * device during cancel_work_sync() call. 2356 */ 2357 device_unlock(&pci->dev); 2358 cancel_work_sync(&hda->probe_work); 2359 device_lock(&pci->dev); 2360 2361 snd_card_free(card); 2362 } 2363 } 2364 2365 static void azx_shutdown(struct pci_dev *pci) 2366 { 2367 struct snd_card *card = pci_get_drvdata(pci); 2368 struct azx *chip; 2369 2370 if (!card) 2371 return; 2372 chip = card->private_data; 2373 if (chip && chip->running) 2374 azx_stop_chip(chip); 2375 } 2376 2377 /* PCI IDs */ 2378 static const struct pci_device_id azx_ids[] = { 2379 /* CPT */ 2380 { PCI_DEVICE(0x8086, 0x1c20), 2381 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2382 /* PBG */ 2383 { PCI_DEVICE(0x8086, 0x1d20), 2384 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2385 /* Panther Point */ 2386 { PCI_DEVICE(0x8086, 0x1e20), 2387 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2388 /* Lynx Point */ 2389 { PCI_DEVICE(0x8086, 0x8c20), 2390 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2391 /* 9 Series */ 2392 { PCI_DEVICE(0x8086, 0x8ca0), 2393 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2394 /* Wellsburg */ 2395 { PCI_DEVICE(0x8086, 0x8d20), 2396 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2397 { PCI_DEVICE(0x8086, 0x8d21), 2398 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2399 /* Lewisburg */ 2400 { PCI_DEVICE(0x8086, 0xa1f0), 2401 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2402 { PCI_DEVICE(0x8086, 0xa270), 2403 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2404 /* Lynx Point-LP */ 2405 { PCI_DEVICE(0x8086, 0x9c20), 2406 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2407 /* Lynx Point-LP */ 2408 { PCI_DEVICE(0x8086, 0x9c21), 2409 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2410 /* Wildcat Point-LP */ 2411 { PCI_DEVICE(0x8086, 0x9ca0), 2412 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2413 /* Sunrise Point */ 2414 { PCI_DEVICE(0x8086, 0xa170), 2415 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2416 /* Sunrise Point-LP */ 2417 { PCI_DEVICE(0x8086, 0x9d70), 2418 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2419 /* Kabylake */ 2420 { PCI_DEVICE(0x8086, 0xa171), 2421 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2422 /* Kabylake-LP */ 2423 { PCI_DEVICE(0x8086, 0x9d71), 2424 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2425 /* Kabylake-H */ 2426 { PCI_DEVICE(0x8086, 0xa2f0), 2427 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2428 /* Coffelake */ 2429 { PCI_DEVICE(0x8086, 0xa348), 2430 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2431 /* Cannonlake */ 2432 { PCI_DEVICE(0x8086, 0x9dc8), 2433 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2434 /* CometLake-LP */ 2435 { PCI_DEVICE(0x8086, 0x02C8), 2436 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2437 /* CometLake-H */ 2438 { PCI_DEVICE(0x8086, 0x06C8), 2439 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2440 /* CometLake-S */ 2441 { PCI_DEVICE(0x8086, 0xa3f0), 2442 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2443 /* Icelake */ 2444 { PCI_DEVICE(0x8086, 0x34c8), 2445 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2446 /* Jasperlake */ 2447 { PCI_DEVICE(0x8086, 0x38c8), 2448 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2449 /* Tigerlake */ 2450 { PCI_DEVICE(0x8086, 0xa0c8), 2451 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2452 /* Elkhart Lake */ 2453 { PCI_DEVICE(0x8086, 0x4b55), 2454 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2455 /* Broxton-P(Apollolake) */ 2456 { PCI_DEVICE(0x8086, 0x5a98), 2457 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2458 /* Broxton-T */ 2459 { PCI_DEVICE(0x8086, 0x1a98), 2460 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2461 /* Gemini-Lake */ 2462 { PCI_DEVICE(0x8086, 0x3198), 2463 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2464 /* Haswell */ 2465 { PCI_DEVICE(0x8086, 0x0a0c), 2466 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2467 { PCI_DEVICE(0x8086, 0x0c0c), 2468 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2469 { PCI_DEVICE(0x8086, 0x0d0c), 2470 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2471 /* Broadwell */ 2472 { PCI_DEVICE(0x8086, 0x160c), 2473 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2474 /* 5 Series/3400 */ 2475 { PCI_DEVICE(0x8086, 0x3b56), 2476 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2477 /* Poulsbo */ 2478 { PCI_DEVICE(0x8086, 0x811b), 2479 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2480 /* Oaktrail */ 2481 { PCI_DEVICE(0x8086, 0x080a), 2482 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2483 /* BayTrail */ 2484 { PCI_DEVICE(0x8086, 0x0f04), 2485 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2486 /* Braswell */ 2487 { PCI_DEVICE(0x8086, 0x2284), 2488 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2489 /* ICH6 */ 2490 { PCI_DEVICE(0x8086, 0x2668), 2491 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2492 /* ICH7 */ 2493 { PCI_DEVICE(0x8086, 0x27d8), 2494 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2495 /* ESB2 */ 2496 { PCI_DEVICE(0x8086, 0x269a), 2497 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2498 /* ICH8 */ 2499 { PCI_DEVICE(0x8086, 0x284b), 2500 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2501 /* ICH9 */ 2502 { PCI_DEVICE(0x8086, 0x293e), 2503 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2504 /* ICH9 */ 2505 { PCI_DEVICE(0x8086, 0x293f), 2506 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2507 /* ICH10 */ 2508 { PCI_DEVICE(0x8086, 0x3a3e), 2509 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2510 /* ICH10 */ 2511 { PCI_DEVICE(0x8086, 0x3a6e), 2512 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2513 /* Generic Intel */ 2514 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2515 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2516 .class_mask = 0xffffff, 2517 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2518 /* ATI SB 450/600/700/800/900 */ 2519 { PCI_DEVICE(0x1002, 0x437b), 2520 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2521 { PCI_DEVICE(0x1002, 0x4383), 2522 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2523 /* AMD Hudson */ 2524 { PCI_DEVICE(0x1022, 0x780d), 2525 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2526 /* AMD, X370 & co */ 2527 { PCI_DEVICE(0x1022, 0x1457), 2528 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2529 /* AMD, X570 & co */ 2530 { PCI_DEVICE(0x1022, 0x1487), 2531 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2532 /* AMD Stoney */ 2533 { PCI_DEVICE(0x1022, 0x157a), 2534 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2535 AZX_DCAPS_PM_RUNTIME }, 2536 /* AMD Raven */ 2537 { PCI_DEVICE(0x1022, 0x15e3), 2538 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2539 /* ATI HDMI */ 2540 { PCI_DEVICE(0x1002, 0x0002), 2541 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2542 { PCI_DEVICE(0x1002, 0x1308), 2543 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2544 { PCI_DEVICE(0x1002, 0x157a), 2545 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2546 { PCI_DEVICE(0x1002, 0x15b3), 2547 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2548 { PCI_DEVICE(0x1002, 0x793b), 2549 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2550 { PCI_DEVICE(0x1002, 0x7919), 2551 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2552 { PCI_DEVICE(0x1002, 0x960f), 2553 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2554 { PCI_DEVICE(0x1002, 0x970f), 2555 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2556 { PCI_DEVICE(0x1002, 0x9840), 2557 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2558 { PCI_DEVICE(0x1002, 0xaa00), 2559 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2560 { PCI_DEVICE(0x1002, 0xaa08), 2561 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2562 { PCI_DEVICE(0x1002, 0xaa10), 2563 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2564 { PCI_DEVICE(0x1002, 0xaa18), 2565 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2566 { PCI_DEVICE(0x1002, 0xaa20), 2567 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2568 { PCI_DEVICE(0x1002, 0xaa28), 2569 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2570 { PCI_DEVICE(0x1002, 0xaa30), 2571 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2572 { PCI_DEVICE(0x1002, 0xaa38), 2573 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2574 { PCI_DEVICE(0x1002, 0xaa40), 2575 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2576 { PCI_DEVICE(0x1002, 0xaa48), 2577 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2578 { PCI_DEVICE(0x1002, 0xaa50), 2579 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2580 { PCI_DEVICE(0x1002, 0xaa58), 2581 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2582 { PCI_DEVICE(0x1002, 0xaa60), 2583 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2584 { PCI_DEVICE(0x1002, 0xaa68), 2585 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2586 { PCI_DEVICE(0x1002, 0xaa80), 2587 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2588 { PCI_DEVICE(0x1002, 0xaa88), 2589 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2590 { PCI_DEVICE(0x1002, 0xaa90), 2591 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2592 { PCI_DEVICE(0x1002, 0xaa98), 2593 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2594 { PCI_DEVICE(0x1002, 0x9902), 2595 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2596 { PCI_DEVICE(0x1002, 0xaaa0), 2597 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2598 { PCI_DEVICE(0x1002, 0xaaa8), 2599 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2600 { PCI_DEVICE(0x1002, 0xaab0), 2601 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2602 { PCI_DEVICE(0x1002, 0xaac0), 2603 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2604 { PCI_DEVICE(0x1002, 0xaac8), 2605 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2606 { PCI_DEVICE(0x1002, 0xaad8), 2607 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2608 AZX_DCAPS_PM_RUNTIME }, 2609 { PCI_DEVICE(0x1002, 0xaae0), 2610 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2611 AZX_DCAPS_PM_RUNTIME }, 2612 { PCI_DEVICE(0x1002, 0xaae8), 2613 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2614 AZX_DCAPS_PM_RUNTIME }, 2615 { PCI_DEVICE(0x1002, 0xaaf0), 2616 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2617 AZX_DCAPS_PM_RUNTIME }, 2618 { PCI_DEVICE(0x1002, 0xaaf8), 2619 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2620 AZX_DCAPS_PM_RUNTIME }, 2621 { PCI_DEVICE(0x1002, 0xab00), 2622 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2623 AZX_DCAPS_PM_RUNTIME }, 2624 { PCI_DEVICE(0x1002, 0xab08), 2625 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2626 AZX_DCAPS_PM_RUNTIME }, 2627 { PCI_DEVICE(0x1002, 0xab10), 2628 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2629 AZX_DCAPS_PM_RUNTIME }, 2630 { PCI_DEVICE(0x1002, 0xab18), 2631 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2632 AZX_DCAPS_PM_RUNTIME }, 2633 { PCI_DEVICE(0x1002, 0xab20), 2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2635 AZX_DCAPS_PM_RUNTIME }, 2636 { PCI_DEVICE(0x1002, 0xab38), 2637 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2638 AZX_DCAPS_PM_RUNTIME }, 2639 /* VIA VT8251/VT8237A */ 2640 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2641 /* VIA GFX VT7122/VX900 */ 2642 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2643 /* VIA GFX VT6122/VX11 */ 2644 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2645 /* SIS966 */ 2646 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2647 /* ULI M5461 */ 2648 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2649 /* NVIDIA MCP */ 2650 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2651 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2652 .class_mask = 0xffffff, 2653 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2654 /* Teradici */ 2655 { PCI_DEVICE(0x6549, 0x1200), 2656 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2657 { PCI_DEVICE(0x6549, 0x2200), 2658 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2659 /* Creative X-Fi (CA0110-IBG) */ 2660 /* CTHDA chips */ 2661 { PCI_DEVICE(0x1102, 0x0010), 2662 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2663 { PCI_DEVICE(0x1102, 0x0012), 2664 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2665 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2666 /* the following entry conflicts with snd-ctxfi driver, 2667 * as ctxfi driver mutates from HD-audio to native mode with 2668 * a special command sequence. 2669 */ 2670 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2671 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2672 .class_mask = 0xffffff, 2673 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2674 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2675 #else 2676 /* this entry seems still valid -- i.e. without emu20kx chip */ 2677 { PCI_DEVICE(0x1102, 0x0009), 2678 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2679 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2680 #endif 2681 /* CM8888 */ 2682 { PCI_DEVICE(0x13f6, 0x5011), 2683 .driver_data = AZX_DRIVER_CMEDIA | 2684 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2685 /* Vortex86MX */ 2686 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2687 /* VMware HDAudio */ 2688 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2689 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2690 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2691 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2692 .class_mask = 0xffffff, 2693 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2694 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2695 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2696 .class_mask = 0xffffff, 2697 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2698 /* Zhaoxin */ 2699 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2700 { 0, } 2701 }; 2702 MODULE_DEVICE_TABLE(pci, azx_ids); 2703 2704 /* pci_driver definition */ 2705 static struct pci_driver azx_driver = { 2706 .name = KBUILD_MODNAME, 2707 .id_table = azx_ids, 2708 .probe = azx_probe, 2709 .remove = azx_remove, 2710 .shutdown = azx_shutdown, 2711 .driver = { 2712 .pm = AZX_PM_OPS, 2713 }, 2714 }; 2715 2716 module_pci_driver(azx_driver); 2717