1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/firmware.h> 54 #include <sound/hda_codec.h> 55 #include "hda_controller.h" 56 #include "hda_intel.h" 57 58 #define CREATE_TRACE_POINTS 59 #include "hda_intel_trace.h" 60 61 /* position fix mode */ 62 enum { 63 POS_FIX_AUTO, 64 POS_FIX_LPIB, 65 POS_FIX_POSBUF, 66 POS_FIX_VIACOMBO, 67 POS_FIX_COMBO, 68 POS_FIX_SKL, 69 POS_FIX_FIFO, 70 }; 71 72 /* Defines for ATI HD Audio support in SB450 south bridge */ 73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 75 76 /* Defines for Nvidia HDA support */ 77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 79 #define NVIDIA_HDA_ISTRM_COH 0x4d 80 #define NVIDIA_HDA_OSTRM_COH 0x4c 81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 82 83 /* Defines for Intel SCH HDA snoop control */ 84 #define INTEL_HDA_CGCTL 0x48 85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 86 #define INTEL_SCH_HDA_DEVC 0x78 87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 88 89 /* Define VIA HD Audio Device ID*/ 90 #define VIA_HDAC_DEVICE_ID 0x3288 91 92 /* max number of SDs */ 93 /* ICH, ATI and VIA have 4 playback and 4 capture */ 94 #define ICH6_NUM_CAPTURE 4 95 #define ICH6_NUM_PLAYBACK 4 96 97 /* ULI has 6 playback and 5 capture */ 98 #define ULI_NUM_CAPTURE 5 99 #define ULI_NUM_PLAYBACK 6 100 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 102 #define ATIHDMI_NUM_CAPTURE 0 103 #define ATIHDMI_NUM_PLAYBACK 8 104 105 /* TERA has 4 playback and 3 capture */ 106 #define TERA_NUM_CAPTURE 3 107 #define TERA_NUM_PLAYBACK 4 108 109 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 113 static char *model[SNDRV_CARDS]; 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 117 static int probe_only[SNDRV_CARDS]; 118 static int jackpoll_ms[SNDRV_CARDS]; 119 static int single_cmd = -1; 120 static int enable_msi = -1; 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER 122 static char *patch[SNDRV_CARDS]; 123 #endif 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 126 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 127 #endif 128 static bool dmic_detect = 1; 129 130 module_param_array(index, int, NULL, 0444); 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 132 module_param_array(id, charp, NULL, 0444); 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 134 module_param_array(enable, bool, NULL, 0444); 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 136 module_param_array(model, charp, NULL, 0444); 137 MODULE_PARM_DESC(model, "Use the given board model."); 138 module_param_array(position_fix, int, NULL, 0444); 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 141 module_param_array(bdl_pos_adj, int, NULL, 0644); 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 143 module_param_array(probe_mask, int, NULL, 0444); 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 145 module_param_array(probe_only, int, NULL, 0444); 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 147 module_param_array(jackpoll_ms, int, NULL, 0444); 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 149 module_param(single_cmd, bint, 0444); 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 151 "(for debugging only)."); 152 module_param(enable_msi, bint, 0444); 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER 155 module_param_array(patch, charp, NULL, 0444); 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 157 #endif 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP 159 module_param_array(beep_mode, bool, NULL, 0444); 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 161 "(0=off, 1=on) (default=1)."); 162 #endif 163 module_param(dmic_detect, bool, 0444); 164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 165 "(0=off, 1=on) (default=1); " 166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 167 168 #ifdef CONFIG_PM 169 static int param_set_xint(const char *val, const struct kernel_param *kp); 170 static const struct kernel_param_ops param_ops_xint = { 171 .set = param_set_xint, 172 .get = param_get_int, 173 }; 174 #define param_check_xint param_check_int 175 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 177 module_param(power_save, xint, 0644); 178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 179 "(in second, 0 = disable)."); 180 181 static bool pm_blacklist = true; 182 module_param(pm_blacklist, bool, 0644); 183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management blacklist"); 184 185 /* reset the HD-audio controller in power save mode. 186 * this may give more power-saving, but will take longer time to 187 * wake up. 188 */ 189 static bool power_save_controller = 1; 190 module_param(power_save_controller, bool, 0644); 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 192 #else 193 #define power_save 0 194 #endif /* CONFIG_PM */ 195 196 static int align_buffer_size = -1; 197 module_param(align_buffer_size, bint, 0644); 198 MODULE_PARM_DESC(align_buffer_size, 199 "Force buffer and period sizes to be multiple of 128 bytes."); 200 201 #ifdef CONFIG_X86 202 static int hda_snoop = -1; 203 module_param_named(snoop, hda_snoop, bint, 0444); 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 205 #else 206 #define hda_snoop true 207 #endif 208 209 210 MODULE_LICENSE("GPL"); 211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 212 "{Intel, ICH6M}," 213 "{Intel, ICH7}," 214 "{Intel, ESB2}," 215 "{Intel, ICH8}," 216 "{Intel, ICH9}," 217 "{Intel, ICH10}," 218 "{Intel, PCH}," 219 "{Intel, CPT}," 220 "{Intel, PPT}," 221 "{Intel, LPT}," 222 "{Intel, LPT_LP}," 223 "{Intel, WPT_LP}," 224 "{Intel, SPT}," 225 "{Intel, SPT_LP}," 226 "{Intel, HPT}," 227 "{Intel, PBG}," 228 "{Intel, SCH}," 229 "{ATI, SB450}," 230 "{ATI, SB600}," 231 "{ATI, RS600}," 232 "{ATI, RS690}," 233 "{ATI, RS780}," 234 "{ATI, R600}," 235 "{ATI, RV630}," 236 "{ATI, RV610}," 237 "{ATI, RV670}," 238 "{ATI, RV635}," 239 "{ATI, RV620}," 240 "{ATI, RV770}," 241 "{VIA, VT8251}," 242 "{VIA, VT8237A}," 243 "{SiS, SIS966}," 244 "{ULI, M5461}}"); 245 MODULE_DESCRIPTION("Intel HDA driver"); 246 247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 249 #define SUPPORT_VGA_SWITCHEROO 250 #endif 251 #endif 252 253 254 /* 255 */ 256 257 /* driver types */ 258 enum { 259 AZX_DRIVER_ICH, 260 AZX_DRIVER_PCH, 261 AZX_DRIVER_SCH, 262 AZX_DRIVER_SKL, 263 AZX_DRIVER_HDMI, 264 AZX_DRIVER_ATI, 265 AZX_DRIVER_ATIHDMI, 266 AZX_DRIVER_ATIHDMI_NS, 267 AZX_DRIVER_VIA, 268 AZX_DRIVER_SIS, 269 AZX_DRIVER_ULI, 270 AZX_DRIVER_NVIDIA, 271 AZX_DRIVER_TERA, 272 AZX_DRIVER_CTX, 273 AZX_DRIVER_CTHDA, 274 AZX_DRIVER_CMEDIA, 275 AZX_DRIVER_ZHAOXIN, 276 AZX_DRIVER_GENERIC, 277 AZX_NUM_DRIVERS, /* keep this as last entry */ 278 }; 279 280 #define azx_get_snoop_type(chip) \ 281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 283 284 /* quirks for old Intel chipsets */ 285 #define AZX_DCAPS_INTEL_ICH \ 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 287 288 /* quirks for Intel PCH */ 289 #define AZX_DCAPS_INTEL_PCH_BASE \ 290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 291 AZX_DCAPS_SNOOP_TYPE(SCH)) 292 293 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 294 #define AZX_DCAPS_INTEL_PCH_NOPM \ 295 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 296 297 /* PCH for HSW/BDW; with runtime PM */ 298 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 299 #define AZX_DCAPS_INTEL_PCH \ 300 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 301 302 /* HSW HDMI */ 303 #define AZX_DCAPS_INTEL_HASWELL \ 304 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 305 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 306 AZX_DCAPS_SNOOP_TYPE(SCH)) 307 308 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 309 #define AZX_DCAPS_INTEL_BROADWELL \ 310 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 311 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 312 AZX_DCAPS_SNOOP_TYPE(SCH)) 313 314 #define AZX_DCAPS_INTEL_BAYTRAIL \ 315 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 316 317 #define AZX_DCAPS_INTEL_BRASWELL \ 318 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 319 AZX_DCAPS_I915_COMPONENT) 320 321 #define AZX_DCAPS_INTEL_SKYLAKE \ 322 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 323 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 324 325 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 326 327 /* quirks for ATI SB / AMD Hudson */ 328 #define AZX_DCAPS_PRESET_ATI_SB \ 329 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 330 AZX_DCAPS_SNOOP_TYPE(ATI)) 331 332 /* quirks for ATI/AMD HDMI */ 333 #define AZX_DCAPS_PRESET_ATI_HDMI \ 334 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 335 AZX_DCAPS_NO_MSI64) 336 337 /* quirks for ATI HDMI with snoop off */ 338 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 339 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 340 341 /* quirks for AMD SB */ 342 #define AZX_DCAPS_PRESET_AMD_SB \ 343 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 344 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME) 345 346 /* quirks for Nvidia */ 347 #define AZX_DCAPS_PRESET_NVIDIA \ 348 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 349 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 350 351 #define AZX_DCAPS_PRESET_CTHDA \ 352 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 353 AZX_DCAPS_NO_64BIT |\ 354 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 355 356 /* 357 * vga_switcheroo support 358 */ 359 #ifdef SUPPORT_VGA_SWITCHEROO 360 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 361 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 362 #else 363 #define use_vga_switcheroo(chip) 0 364 #define needs_eld_notify_link(chip) false 365 #endif 366 367 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 368 ((pci)->device == 0x0c0c) || \ 369 ((pci)->device == 0x0d0c) || \ 370 ((pci)->device == 0x160c)) 371 372 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 373 374 static const char * const driver_short_names[] = { 375 [AZX_DRIVER_ICH] = "HDA Intel", 376 [AZX_DRIVER_PCH] = "HDA Intel PCH", 377 [AZX_DRIVER_SCH] = "HDA Intel MID", 378 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 379 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 380 [AZX_DRIVER_ATI] = "HDA ATI SB", 381 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 382 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 383 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 384 [AZX_DRIVER_SIS] = "HDA SIS966", 385 [AZX_DRIVER_ULI] = "HDA ULI M5461", 386 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 387 [AZX_DRIVER_TERA] = "HDA Teradici", 388 [AZX_DRIVER_CTX] = "HDA Creative", 389 [AZX_DRIVER_CTHDA] = "HDA Creative", 390 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 391 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 392 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 393 }; 394 395 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 396 static void set_default_power_save(struct azx *chip); 397 398 /* 399 * initialize the PCI registers 400 */ 401 /* update bits in a PCI register byte */ 402 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 403 unsigned char mask, unsigned char val) 404 { 405 unsigned char data; 406 407 pci_read_config_byte(pci, reg, &data); 408 data &= ~mask; 409 data |= (val & mask); 410 pci_write_config_byte(pci, reg, data); 411 } 412 413 static void azx_init_pci(struct azx *chip) 414 { 415 int snoop_type = azx_get_snoop_type(chip); 416 417 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 418 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 419 * Ensuring these bits are 0 clears playback static on some HD Audio 420 * codecs. 421 * The PCI register TCSEL is defined in the Intel manuals. 422 */ 423 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 424 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 425 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 426 } 427 428 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 429 * we need to enable snoop. 430 */ 431 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 432 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 433 azx_snoop(chip)); 434 update_pci_byte(chip->pci, 435 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 436 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 437 } 438 439 /* For NVIDIA HDA, enable snoop */ 440 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 441 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 442 azx_snoop(chip)); 443 update_pci_byte(chip->pci, 444 NVIDIA_HDA_TRANSREG_ADDR, 445 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 446 update_pci_byte(chip->pci, 447 NVIDIA_HDA_ISTRM_COH, 448 0x01, NVIDIA_HDA_ENABLE_COHBIT); 449 update_pci_byte(chip->pci, 450 NVIDIA_HDA_OSTRM_COH, 451 0x01, NVIDIA_HDA_ENABLE_COHBIT); 452 } 453 454 /* Enable SCH/PCH snoop if needed */ 455 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 456 unsigned short snoop; 457 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 458 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 459 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 460 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 461 if (!azx_snoop(chip)) 462 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 463 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 464 pci_read_config_word(chip->pci, 465 INTEL_SCH_HDA_DEVC, &snoop); 466 } 467 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 468 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 469 "Disabled" : "Enabled"); 470 } 471 } 472 473 /* 474 * In BXT-P A0, HD-Audio DMA requests is later than expected, 475 * and makes an audio stream sensitive to system latencies when 476 * 24/32 bits are playing. 477 * Adjusting threshold of DMA fifo to force the DMA request 478 * sooner to improve latency tolerance at the expense of power. 479 */ 480 static void bxt_reduce_dma_latency(struct azx *chip) 481 { 482 u32 val; 483 484 val = azx_readl(chip, VS_EM4L); 485 val &= (0x3 << 20); 486 azx_writel(chip, VS_EM4L, val); 487 } 488 489 /* 490 * ML_LCAP bits: 491 * bit 0: 6 MHz Supported 492 * bit 1: 12 MHz Supported 493 * bit 2: 24 MHz Supported 494 * bit 3: 48 MHz Supported 495 * bit 4: 96 MHz Supported 496 * bit 5: 192 MHz Supported 497 */ 498 static int intel_get_lctl_scf(struct azx *chip) 499 { 500 struct hdac_bus *bus = azx_bus(chip); 501 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 502 u32 val, t; 503 int i; 504 505 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 506 507 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 508 t = preferred_bits[i]; 509 if (val & (1 << t)) 510 return t; 511 } 512 513 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 514 return 0; 515 } 516 517 static int intel_ml_lctl_set_power(struct azx *chip, int state) 518 { 519 struct hdac_bus *bus = azx_bus(chip); 520 u32 val; 521 int timeout; 522 523 /* 524 * the codecs are sharing the first link setting by default 525 * If other links are enabled for stream, they need similar fix 526 */ 527 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 528 val &= ~AZX_MLCTL_SPA; 529 val |= state << AZX_MLCTL_SPA_SHIFT; 530 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 531 /* wait for CPA */ 532 timeout = 50; 533 while (timeout) { 534 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 535 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 536 return 0; 537 timeout--; 538 udelay(10); 539 } 540 541 return -1; 542 } 543 544 static void intel_init_lctl(struct azx *chip) 545 { 546 struct hdac_bus *bus = azx_bus(chip); 547 u32 val; 548 int ret; 549 550 /* 0. check lctl register value is correct or not */ 551 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 552 /* if SCF is already set, let's use it */ 553 if ((val & ML_LCTL_SCF_MASK) != 0) 554 return; 555 556 /* 557 * Before operating on SPA, CPA must match SPA. 558 * Any deviation may result in undefined behavior. 559 */ 560 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 561 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 562 return; 563 564 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 565 ret = intel_ml_lctl_set_power(chip, 0); 566 udelay(100); 567 if (ret) 568 goto set_spa; 569 570 /* 2. update SCF to select a properly audio clock*/ 571 val &= ~ML_LCTL_SCF_MASK; 572 val |= intel_get_lctl_scf(chip); 573 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 574 575 set_spa: 576 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 577 intel_ml_lctl_set_power(chip, 1); 578 udelay(100); 579 } 580 581 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 582 { 583 struct hdac_bus *bus = azx_bus(chip); 584 struct pci_dev *pci = chip->pci; 585 u32 val; 586 587 snd_hdac_set_codec_wakeup(bus, true); 588 if (chip->driver_type == AZX_DRIVER_SKL) { 589 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 590 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 591 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 592 } 593 azx_init_chip(chip, full_reset); 594 if (chip->driver_type == AZX_DRIVER_SKL) { 595 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 596 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 597 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 598 } 599 600 snd_hdac_set_codec_wakeup(bus, false); 601 602 /* reduce dma latency to avoid noise */ 603 if (IS_BXT(pci)) 604 bxt_reduce_dma_latency(chip); 605 606 if (bus->mlcap != NULL) 607 intel_init_lctl(chip); 608 } 609 610 /* calculate runtime delay from LPIB */ 611 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 612 unsigned int pos) 613 { 614 struct snd_pcm_substream *substream = azx_dev->core.substream; 615 int stream = substream->stream; 616 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 617 int delay; 618 619 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 620 delay = pos - lpib_pos; 621 else 622 delay = lpib_pos - pos; 623 if (delay < 0) { 624 if (delay >= azx_dev->core.delay_negative_threshold) 625 delay = 0; 626 else 627 delay += azx_dev->core.bufsize; 628 } 629 630 if (delay >= azx_dev->core.period_bytes) { 631 dev_info(chip->card->dev, 632 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 633 delay, azx_dev->core.period_bytes); 634 delay = 0; 635 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 636 chip->get_delay[stream] = NULL; 637 } 638 639 return bytes_to_frames(substream->runtime, delay); 640 } 641 642 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 643 644 /* called from IRQ */ 645 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 646 { 647 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 648 int ok; 649 650 ok = azx_position_ok(chip, azx_dev); 651 if (ok == 1) { 652 azx_dev->irq_pending = 0; 653 return ok; 654 } else if (ok == 0) { 655 /* bogus IRQ, process it later */ 656 azx_dev->irq_pending = 1; 657 schedule_work(&hda->irq_pending_work); 658 } 659 return 0; 660 } 661 662 #define display_power(chip, enable) \ 663 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 664 665 /* 666 * Check whether the current DMA position is acceptable for updating 667 * periods. Returns non-zero if it's OK. 668 * 669 * Many HD-audio controllers appear pretty inaccurate about 670 * the update-IRQ timing. The IRQ is issued before actually the 671 * data is processed. So, we need to process it afterwords in a 672 * workqueue. 673 */ 674 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 675 { 676 struct snd_pcm_substream *substream = azx_dev->core.substream; 677 int stream = substream->stream; 678 u32 wallclk; 679 unsigned int pos; 680 681 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 682 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 683 return -1; /* bogus (too early) interrupt */ 684 685 if (chip->get_position[stream]) 686 pos = chip->get_position[stream](chip, azx_dev); 687 else { /* use the position buffer as default */ 688 pos = azx_get_pos_posbuf(chip, azx_dev); 689 if (!pos || pos == (u32)-1) { 690 dev_info(chip->card->dev, 691 "Invalid position buffer, using LPIB read method instead.\n"); 692 chip->get_position[stream] = azx_get_pos_lpib; 693 if (chip->get_position[0] == azx_get_pos_lpib && 694 chip->get_position[1] == azx_get_pos_lpib) 695 azx_bus(chip)->use_posbuf = false; 696 pos = azx_get_pos_lpib(chip, azx_dev); 697 chip->get_delay[stream] = NULL; 698 } else { 699 chip->get_position[stream] = azx_get_pos_posbuf; 700 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 701 chip->get_delay[stream] = azx_get_delay_from_lpib; 702 } 703 } 704 705 if (pos >= azx_dev->core.bufsize) 706 pos = 0; 707 708 if (WARN_ONCE(!azx_dev->core.period_bytes, 709 "hda-intel: zero azx_dev->period_bytes")) 710 return -1; /* this shouldn't happen! */ 711 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 712 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 713 /* NG - it's below the first next period boundary */ 714 return chip->bdl_pos_adj ? 0 : -1; 715 azx_dev->core.start_wallclk += wallclk; 716 return 1; /* OK, it's fine */ 717 } 718 719 /* 720 * The work for pending PCM period updates. 721 */ 722 static void azx_irq_pending_work(struct work_struct *work) 723 { 724 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 725 struct azx *chip = &hda->chip; 726 struct hdac_bus *bus = azx_bus(chip); 727 struct hdac_stream *s; 728 int pending, ok; 729 730 if (!hda->irq_pending_warned) { 731 dev_info(chip->card->dev, 732 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 733 chip->card->number); 734 hda->irq_pending_warned = 1; 735 } 736 737 for (;;) { 738 pending = 0; 739 spin_lock_irq(&bus->reg_lock); 740 list_for_each_entry(s, &bus->stream_list, list) { 741 struct azx_dev *azx_dev = stream_to_azx_dev(s); 742 if (!azx_dev->irq_pending || 743 !s->substream || 744 !s->running) 745 continue; 746 ok = azx_position_ok(chip, azx_dev); 747 if (ok > 0) { 748 azx_dev->irq_pending = 0; 749 spin_unlock(&bus->reg_lock); 750 snd_pcm_period_elapsed(s->substream); 751 spin_lock(&bus->reg_lock); 752 } else if (ok < 0) { 753 pending = 0; /* too early */ 754 } else 755 pending++; 756 } 757 spin_unlock_irq(&bus->reg_lock); 758 if (!pending) 759 return; 760 msleep(1); 761 } 762 } 763 764 /* clear irq_pending flags and assure no on-going workq */ 765 static void azx_clear_irq_pending(struct azx *chip) 766 { 767 struct hdac_bus *bus = azx_bus(chip); 768 struct hdac_stream *s; 769 770 spin_lock_irq(&bus->reg_lock); 771 list_for_each_entry(s, &bus->stream_list, list) { 772 struct azx_dev *azx_dev = stream_to_azx_dev(s); 773 azx_dev->irq_pending = 0; 774 } 775 spin_unlock_irq(&bus->reg_lock); 776 } 777 778 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 779 { 780 struct hdac_bus *bus = azx_bus(chip); 781 782 if (request_irq(chip->pci->irq, azx_interrupt, 783 chip->msi ? 0 : IRQF_SHARED, 784 chip->card->irq_descr, chip)) { 785 dev_err(chip->card->dev, 786 "unable to grab IRQ %d, disabling device\n", 787 chip->pci->irq); 788 if (do_disconnect) 789 snd_card_disconnect(chip->card); 790 return -1; 791 } 792 bus->irq = chip->pci->irq; 793 chip->card->sync_irq = bus->irq; 794 pci_intx(chip->pci, !chip->msi); 795 return 0; 796 } 797 798 /* get the current DMA position with correction on VIA chips */ 799 static unsigned int azx_via_get_position(struct azx *chip, 800 struct azx_dev *azx_dev) 801 { 802 unsigned int link_pos, mini_pos, bound_pos; 803 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 804 unsigned int fifo_size; 805 806 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 807 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 808 /* Playback, no problem using link position */ 809 return link_pos; 810 } 811 812 /* Capture */ 813 /* For new chipset, 814 * use mod to get the DMA position just like old chipset 815 */ 816 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 817 mod_dma_pos %= azx_dev->core.period_bytes; 818 819 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 820 821 if (azx_dev->insufficient) { 822 /* Link position never gather than FIFO size */ 823 if (link_pos <= fifo_size) 824 return 0; 825 826 azx_dev->insufficient = 0; 827 } 828 829 if (link_pos <= fifo_size) 830 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 831 else 832 mini_pos = link_pos - fifo_size; 833 834 /* Find nearest previous boudary */ 835 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 836 mod_link_pos = link_pos % azx_dev->core.period_bytes; 837 if (mod_link_pos >= fifo_size) 838 bound_pos = link_pos - mod_link_pos; 839 else if (mod_dma_pos >= mod_mini_pos) 840 bound_pos = mini_pos - mod_mini_pos; 841 else { 842 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 843 if (bound_pos >= azx_dev->core.bufsize) 844 bound_pos = 0; 845 } 846 847 /* Calculate real DMA position we want */ 848 return bound_pos + mod_dma_pos; 849 } 850 851 #define AMD_FIFO_SIZE 32 852 853 /* get the current DMA position with FIFO size correction */ 854 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 855 { 856 struct snd_pcm_substream *substream = azx_dev->core.substream; 857 struct snd_pcm_runtime *runtime = substream->runtime; 858 unsigned int pos, delay; 859 860 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 861 if (!runtime) 862 return pos; 863 864 runtime->delay = AMD_FIFO_SIZE; 865 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 866 if (azx_dev->insufficient) { 867 if (pos < delay) { 868 delay = pos; 869 runtime->delay = bytes_to_frames(runtime, pos); 870 } else { 871 azx_dev->insufficient = 0; 872 } 873 } 874 875 /* correct the DMA position for capture stream */ 876 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 877 if (pos < delay) 878 pos += azx_dev->core.bufsize; 879 pos -= delay; 880 } 881 882 return pos; 883 } 884 885 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 886 unsigned int pos) 887 { 888 struct snd_pcm_substream *substream = azx_dev->core.substream; 889 890 /* just read back the calculated value in the above */ 891 return substream->runtime->delay; 892 } 893 894 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 895 struct azx_dev *azx_dev) 896 { 897 return _snd_hdac_chip_readl(azx_bus(chip), 898 AZX_REG_VS_SDXDPIB_XBASE + 899 (AZX_REG_VS_SDXDPIB_XINTERVAL * 900 azx_dev->core.index)); 901 } 902 903 /* get the current DMA position with correction on SKL+ chips */ 904 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 905 { 906 /* DPIB register gives a more accurate position for playback */ 907 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 908 return azx_skl_get_dpib_pos(chip, azx_dev); 909 910 /* For capture, we need to read posbuf, but it requires a delay 911 * for the possible boundary overlap; the read of DPIB fetches the 912 * actual posbuf 913 */ 914 udelay(20); 915 azx_skl_get_dpib_pos(chip, azx_dev); 916 return azx_get_pos_posbuf(chip, azx_dev); 917 } 918 919 #ifdef CONFIG_PM 920 static DEFINE_MUTEX(card_list_lock); 921 static LIST_HEAD(card_list); 922 923 static void azx_add_card_list(struct azx *chip) 924 { 925 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 926 mutex_lock(&card_list_lock); 927 list_add(&hda->list, &card_list); 928 mutex_unlock(&card_list_lock); 929 } 930 931 static void azx_del_card_list(struct azx *chip) 932 { 933 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 934 mutex_lock(&card_list_lock); 935 list_del_init(&hda->list); 936 mutex_unlock(&card_list_lock); 937 } 938 939 /* trigger power-save check at writing parameter */ 940 static int param_set_xint(const char *val, const struct kernel_param *kp) 941 { 942 struct hda_intel *hda; 943 struct azx *chip; 944 int prev = power_save; 945 int ret = param_set_int(val, kp); 946 947 if (ret || prev == power_save) 948 return ret; 949 950 mutex_lock(&card_list_lock); 951 list_for_each_entry(hda, &card_list, list) { 952 chip = &hda->chip; 953 if (!hda->probe_continued || chip->disabled) 954 continue; 955 snd_hda_set_power_save(&chip->bus, power_save * 1000); 956 } 957 mutex_unlock(&card_list_lock); 958 return 0; 959 } 960 961 /* 962 * power management 963 */ 964 static bool azx_is_pm_ready(struct snd_card *card) 965 { 966 struct azx *chip; 967 struct hda_intel *hda; 968 969 if (!card) 970 return false; 971 chip = card->private_data; 972 hda = container_of(chip, struct hda_intel, chip); 973 if (chip->disabled || hda->init_failed || !chip->running) 974 return false; 975 return true; 976 } 977 978 static void __azx_runtime_suspend(struct azx *chip) 979 { 980 azx_stop_chip(chip); 981 azx_enter_link_reset(chip); 982 azx_clear_irq_pending(chip); 983 display_power(chip, false); 984 } 985 986 static void __azx_runtime_resume(struct azx *chip, bool from_rt) 987 { 988 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 989 struct hdac_bus *bus = azx_bus(chip); 990 struct hda_codec *codec; 991 int status; 992 993 display_power(chip, true); 994 if (hda->need_i915_power) 995 snd_hdac_i915_set_bclk(bus); 996 997 /* Read STATESTS before controller reset */ 998 status = azx_readw(chip, STATESTS); 999 1000 azx_init_pci(chip); 1001 hda_intel_init_chip(chip, true); 1002 1003 if (status && from_rt) { 1004 list_for_each_codec(codec, &chip->bus) 1005 if (!codec->relaxed_resume && 1006 (status & (1 << codec->addr))) 1007 schedule_delayed_work(&codec->jackpoll_work, 1008 codec->jackpoll_interval); 1009 } 1010 1011 /* power down again for link-controlled chips */ 1012 if (!hda->need_i915_power) 1013 display_power(chip, false); 1014 } 1015 1016 #ifdef CONFIG_PM_SLEEP 1017 static int azx_suspend(struct device *dev) 1018 { 1019 struct snd_card *card = dev_get_drvdata(dev); 1020 struct azx *chip; 1021 struct hdac_bus *bus; 1022 1023 if (!azx_is_pm_ready(card)) 1024 return 0; 1025 1026 chip = card->private_data; 1027 bus = azx_bus(chip); 1028 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1029 pm_runtime_force_suspend(dev); 1030 if (bus->irq >= 0) { 1031 free_irq(bus->irq, chip); 1032 bus->irq = -1; 1033 chip->card->sync_irq = -1; 1034 } 1035 1036 if (chip->msi) 1037 pci_disable_msi(chip->pci); 1038 1039 trace_azx_suspend(chip); 1040 return 0; 1041 } 1042 1043 static int azx_resume(struct device *dev) 1044 { 1045 struct snd_card *card = dev_get_drvdata(dev); 1046 struct azx *chip; 1047 1048 if (!azx_is_pm_ready(card)) 1049 return 0; 1050 1051 chip = card->private_data; 1052 if (chip->msi) 1053 if (pci_enable_msi(chip->pci) < 0) 1054 chip->msi = 0; 1055 if (azx_acquire_irq(chip, 1) < 0) 1056 return -EIO; 1057 1058 pm_runtime_force_resume(dev); 1059 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1060 1061 trace_azx_resume(chip); 1062 return 0; 1063 } 1064 1065 /* put codec down to D3 at hibernation for Intel SKL+; 1066 * otherwise BIOS may still access the codec and screw up the driver 1067 */ 1068 static int azx_freeze_noirq(struct device *dev) 1069 { 1070 struct snd_card *card = dev_get_drvdata(dev); 1071 struct azx *chip = card->private_data; 1072 struct pci_dev *pci = to_pci_dev(dev); 1073 1074 if (!azx_is_pm_ready(card)) 1075 return 0; 1076 if (chip->driver_type == AZX_DRIVER_SKL) 1077 pci_set_power_state(pci, PCI_D3hot); 1078 1079 return 0; 1080 } 1081 1082 static int azx_thaw_noirq(struct device *dev) 1083 { 1084 struct snd_card *card = dev_get_drvdata(dev); 1085 struct azx *chip = card->private_data; 1086 struct pci_dev *pci = to_pci_dev(dev); 1087 1088 if (!azx_is_pm_ready(card)) 1089 return 0; 1090 if (chip->driver_type == AZX_DRIVER_SKL) 1091 pci_set_power_state(pci, PCI_D0); 1092 1093 return 0; 1094 } 1095 #endif /* CONFIG_PM_SLEEP */ 1096 1097 static int azx_runtime_suspend(struct device *dev) 1098 { 1099 struct snd_card *card = dev_get_drvdata(dev); 1100 struct azx *chip; 1101 1102 if (!azx_is_pm_ready(card)) 1103 return 0; 1104 chip = card->private_data; 1105 1106 /* enable controller wake up event */ 1107 if (snd_power_get_state(card) == SNDRV_CTL_POWER_D0) { 1108 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 1109 STATESTS_INT_MASK); 1110 } 1111 1112 __azx_runtime_suspend(chip); 1113 trace_azx_runtime_suspend(chip); 1114 return 0; 1115 } 1116 1117 static int azx_runtime_resume(struct device *dev) 1118 { 1119 struct snd_card *card = dev_get_drvdata(dev); 1120 struct azx *chip; 1121 bool from_rt = snd_power_get_state(card) == SNDRV_CTL_POWER_D0; 1122 1123 if (!azx_is_pm_ready(card)) 1124 return 0; 1125 chip = card->private_data; 1126 __azx_runtime_resume(chip, from_rt); 1127 1128 /* disable controller Wake Up event*/ 1129 if (from_rt) { 1130 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1131 ~STATESTS_INT_MASK); 1132 } 1133 1134 trace_azx_runtime_resume(chip); 1135 return 0; 1136 } 1137 1138 static int azx_runtime_idle(struct device *dev) 1139 { 1140 struct snd_card *card = dev_get_drvdata(dev); 1141 struct azx *chip; 1142 struct hda_intel *hda; 1143 1144 if (!card) 1145 return 0; 1146 1147 chip = card->private_data; 1148 hda = container_of(chip, struct hda_intel, chip); 1149 if (chip->disabled || hda->init_failed) 1150 return 0; 1151 1152 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1153 azx_bus(chip)->codec_powered || !chip->running) 1154 return -EBUSY; 1155 1156 /* ELD notification gets broken when HD-audio bus is off */ 1157 if (needs_eld_notify_link(chip)) 1158 return -EBUSY; 1159 1160 return 0; 1161 } 1162 1163 static const struct dev_pm_ops azx_pm = { 1164 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1165 #ifdef CONFIG_PM_SLEEP 1166 .freeze_noirq = azx_freeze_noirq, 1167 .thaw_noirq = azx_thaw_noirq, 1168 #endif 1169 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1170 }; 1171 1172 #define AZX_PM_OPS &azx_pm 1173 #else 1174 #define azx_add_card_list(chip) /* NOP */ 1175 #define azx_del_card_list(chip) /* NOP */ 1176 #define AZX_PM_OPS NULL 1177 #endif /* CONFIG_PM */ 1178 1179 1180 static int azx_probe_continue(struct azx *chip); 1181 1182 #ifdef SUPPORT_VGA_SWITCHEROO 1183 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1184 1185 static void azx_vs_set_state(struct pci_dev *pci, 1186 enum vga_switcheroo_state state) 1187 { 1188 struct snd_card *card = pci_get_drvdata(pci); 1189 struct azx *chip = card->private_data; 1190 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1191 struct hda_codec *codec; 1192 bool disabled; 1193 1194 wait_for_completion(&hda->probe_wait); 1195 if (hda->init_failed) 1196 return; 1197 1198 disabled = (state == VGA_SWITCHEROO_OFF); 1199 if (chip->disabled == disabled) 1200 return; 1201 1202 if (!hda->probe_continued) { 1203 chip->disabled = disabled; 1204 if (!disabled) { 1205 dev_info(chip->card->dev, 1206 "Start delayed initialization\n"); 1207 if (azx_probe_continue(chip) < 0) 1208 dev_err(chip->card->dev, "initialization error\n"); 1209 } 1210 } else { 1211 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1212 disabled ? "Disabling" : "Enabling"); 1213 if (disabled) { 1214 list_for_each_codec(codec, &chip->bus) { 1215 pm_runtime_suspend(hda_codec_dev(codec)); 1216 pm_runtime_disable(hda_codec_dev(codec)); 1217 } 1218 pm_runtime_suspend(card->dev); 1219 pm_runtime_disable(card->dev); 1220 /* when we get suspended by vga_switcheroo we end up in D3cold, 1221 * however we have no ACPI handle, so pci/acpi can't put us there, 1222 * put ourselves there */ 1223 pci->current_state = PCI_D3cold; 1224 chip->disabled = true; 1225 if (snd_hda_lock_devices(&chip->bus)) 1226 dev_warn(chip->card->dev, 1227 "Cannot lock devices!\n"); 1228 } else { 1229 snd_hda_unlock_devices(&chip->bus); 1230 chip->disabled = false; 1231 pm_runtime_enable(card->dev); 1232 list_for_each_codec(codec, &chip->bus) { 1233 pm_runtime_enable(hda_codec_dev(codec)); 1234 pm_runtime_resume(hda_codec_dev(codec)); 1235 } 1236 } 1237 } 1238 } 1239 1240 static bool azx_vs_can_switch(struct pci_dev *pci) 1241 { 1242 struct snd_card *card = pci_get_drvdata(pci); 1243 struct azx *chip = card->private_data; 1244 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1245 1246 wait_for_completion(&hda->probe_wait); 1247 if (hda->init_failed) 1248 return false; 1249 if (chip->disabled || !hda->probe_continued) 1250 return true; 1251 if (snd_hda_lock_devices(&chip->bus)) 1252 return false; 1253 snd_hda_unlock_devices(&chip->bus); 1254 return true; 1255 } 1256 1257 /* 1258 * The discrete GPU cannot power down unless the HDA controller runtime 1259 * suspends, so activate runtime PM on codecs even if power_save == 0. 1260 */ 1261 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1262 { 1263 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1264 struct hda_codec *codec; 1265 1266 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1267 list_for_each_codec(codec, &chip->bus) 1268 codec->auto_runtime_pm = 1; 1269 /* reset the power save setup */ 1270 if (chip->running) 1271 set_default_power_save(chip); 1272 } 1273 } 1274 1275 static void azx_vs_gpu_bound(struct pci_dev *pci, 1276 enum vga_switcheroo_client_id client_id) 1277 { 1278 struct snd_card *card = pci_get_drvdata(pci); 1279 struct azx *chip = card->private_data; 1280 1281 if (client_id == VGA_SWITCHEROO_DIS) 1282 chip->bus.keep_power = 0; 1283 setup_vga_switcheroo_runtime_pm(chip); 1284 } 1285 1286 static void init_vga_switcheroo(struct azx *chip) 1287 { 1288 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1289 struct pci_dev *p = get_bound_vga(chip->pci); 1290 struct pci_dev *parent; 1291 if (p) { 1292 dev_info(chip->card->dev, 1293 "Handle vga_switcheroo audio client\n"); 1294 hda->use_vga_switcheroo = 1; 1295 1296 /* cleared in either gpu_bound op or codec probe, or when its 1297 * upstream port has _PR3 (i.e. dGPU). 1298 */ 1299 parent = pci_upstream_bridge(p); 1300 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1301 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1302 pci_dev_put(p); 1303 } 1304 } 1305 1306 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1307 .set_gpu_state = azx_vs_set_state, 1308 .can_switch = azx_vs_can_switch, 1309 .gpu_bound = azx_vs_gpu_bound, 1310 }; 1311 1312 static int register_vga_switcheroo(struct azx *chip) 1313 { 1314 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1315 struct pci_dev *p; 1316 int err; 1317 1318 if (!hda->use_vga_switcheroo) 1319 return 0; 1320 1321 p = get_bound_vga(chip->pci); 1322 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1323 pci_dev_put(p); 1324 1325 if (err < 0) 1326 return err; 1327 hda->vga_switcheroo_registered = 1; 1328 1329 return 0; 1330 } 1331 #else 1332 #define init_vga_switcheroo(chip) /* NOP */ 1333 #define register_vga_switcheroo(chip) 0 1334 #define check_hdmi_disabled(pci) false 1335 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1336 #endif /* SUPPORT_VGA_SWITCHER */ 1337 1338 /* 1339 * destructor 1340 */ 1341 static void azx_free(struct azx *chip) 1342 { 1343 struct pci_dev *pci = chip->pci; 1344 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1345 struct hdac_bus *bus = azx_bus(chip); 1346 1347 if (hda->freed) 1348 return; 1349 1350 if (azx_has_pm_runtime(chip) && chip->running) 1351 pm_runtime_get_noresume(&pci->dev); 1352 chip->running = 0; 1353 1354 azx_del_card_list(chip); 1355 1356 hda->init_failed = 1; /* to be sure */ 1357 complete_all(&hda->probe_wait); 1358 1359 if (use_vga_switcheroo(hda)) { 1360 if (chip->disabled && hda->probe_continued) 1361 snd_hda_unlock_devices(&chip->bus); 1362 if (hda->vga_switcheroo_registered) 1363 vga_switcheroo_unregister_client(chip->pci); 1364 } 1365 1366 if (bus->chip_init) { 1367 azx_clear_irq_pending(chip); 1368 azx_stop_all_streams(chip); 1369 azx_stop_chip(chip); 1370 } 1371 1372 if (bus->irq >= 0) 1373 free_irq(bus->irq, (void*)chip); 1374 if (chip->msi) 1375 pci_disable_msi(chip->pci); 1376 iounmap(bus->remap_addr); 1377 1378 azx_free_stream_pages(chip); 1379 azx_free_streams(chip); 1380 snd_hdac_bus_exit(bus); 1381 1382 if (chip->region_requested) 1383 pci_release_regions(chip->pci); 1384 1385 pci_disable_device(chip->pci); 1386 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1387 release_firmware(chip->fw); 1388 #endif 1389 display_power(chip, false); 1390 1391 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1392 snd_hdac_i915_exit(bus); 1393 1394 hda->freed = 1; 1395 } 1396 1397 static int azx_dev_disconnect(struct snd_device *device) 1398 { 1399 struct azx *chip = device->device_data; 1400 struct hdac_bus *bus = azx_bus(chip); 1401 1402 chip->bus.shutdown = 1; 1403 cancel_work_sync(&bus->unsol_work); 1404 1405 return 0; 1406 } 1407 1408 static int azx_dev_free(struct snd_device *device) 1409 { 1410 azx_free(device->device_data); 1411 return 0; 1412 } 1413 1414 #ifdef SUPPORT_VGA_SWITCHEROO 1415 #ifdef CONFIG_ACPI 1416 /* ATPX is in the integrated GPU's namespace */ 1417 static bool atpx_present(void) 1418 { 1419 struct pci_dev *pdev = NULL; 1420 acpi_handle dhandle, atpx_handle; 1421 acpi_status status; 1422 1423 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 1424 dhandle = ACPI_HANDLE(&pdev->dev); 1425 if (dhandle) { 1426 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1427 if (!ACPI_FAILURE(status)) { 1428 pci_dev_put(pdev); 1429 return true; 1430 } 1431 } 1432 } 1433 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 1434 dhandle = ACPI_HANDLE(&pdev->dev); 1435 if (dhandle) { 1436 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1437 if (!ACPI_FAILURE(status)) { 1438 pci_dev_put(pdev); 1439 return true; 1440 } 1441 } 1442 } 1443 return false; 1444 } 1445 #else 1446 static bool atpx_present(void) 1447 { 1448 return false; 1449 } 1450 #endif 1451 1452 /* 1453 * Check of disabled HDMI controller by vga_switcheroo 1454 */ 1455 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1456 { 1457 struct pci_dev *p; 1458 1459 /* check only discrete GPU */ 1460 switch (pci->vendor) { 1461 case PCI_VENDOR_ID_ATI: 1462 case PCI_VENDOR_ID_AMD: 1463 if (pci->devfn == 1) { 1464 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1465 pci->bus->number, 0); 1466 if (p) { 1467 /* ATPX is in the integrated GPU's ACPI namespace 1468 * rather than the dGPU's namespace. However, 1469 * the dGPU is the one who is involved in 1470 * vgaswitcheroo. 1471 */ 1472 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1473 atpx_present()) 1474 return p; 1475 pci_dev_put(p); 1476 } 1477 } 1478 break; 1479 case PCI_VENDOR_ID_NVIDIA: 1480 if (pci->devfn == 1) { 1481 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1482 pci->bus->number, 0); 1483 if (p) { 1484 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1485 return p; 1486 pci_dev_put(p); 1487 } 1488 } 1489 break; 1490 } 1491 return NULL; 1492 } 1493 1494 static bool check_hdmi_disabled(struct pci_dev *pci) 1495 { 1496 bool vga_inactive = false; 1497 struct pci_dev *p = get_bound_vga(pci); 1498 1499 if (p) { 1500 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1501 vga_inactive = true; 1502 pci_dev_put(p); 1503 } 1504 return vga_inactive; 1505 } 1506 #endif /* SUPPORT_VGA_SWITCHEROO */ 1507 1508 /* 1509 * white/black-listing for position_fix 1510 */ 1511 static const struct snd_pci_quirk position_fix_list[] = { 1512 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1513 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1514 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1515 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1516 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1517 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1518 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1519 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1520 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1521 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1522 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1523 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1524 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1525 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1526 {} 1527 }; 1528 1529 static int check_position_fix(struct azx *chip, int fix) 1530 { 1531 const struct snd_pci_quirk *q; 1532 1533 switch (fix) { 1534 case POS_FIX_AUTO: 1535 case POS_FIX_LPIB: 1536 case POS_FIX_POSBUF: 1537 case POS_FIX_VIACOMBO: 1538 case POS_FIX_COMBO: 1539 case POS_FIX_SKL: 1540 case POS_FIX_FIFO: 1541 return fix; 1542 } 1543 1544 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1545 if (q) { 1546 dev_info(chip->card->dev, 1547 "position_fix set to %d for device %04x:%04x\n", 1548 q->value, q->subvendor, q->subdevice); 1549 return q->value; 1550 } 1551 1552 /* Check VIA/ATI HD Audio Controller exist */ 1553 if (chip->driver_type == AZX_DRIVER_VIA) { 1554 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1555 return POS_FIX_VIACOMBO; 1556 } 1557 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1558 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1559 return POS_FIX_FIFO; 1560 } 1561 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1562 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1563 return POS_FIX_LPIB; 1564 } 1565 if (chip->driver_type == AZX_DRIVER_SKL) { 1566 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1567 return POS_FIX_SKL; 1568 } 1569 return POS_FIX_AUTO; 1570 } 1571 1572 static void assign_position_fix(struct azx *chip, int fix) 1573 { 1574 static const azx_get_pos_callback_t callbacks[] = { 1575 [POS_FIX_AUTO] = NULL, 1576 [POS_FIX_LPIB] = azx_get_pos_lpib, 1577 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1578 [POS_FIX_VIACOMBO] = azx_via_get_position, 1579 [POS_FIX_COMBO] = azx_get_pos_lpib, 1580 [POS_FIX_SKL] = azx_get_pos_skl, 1581 [POS_FIX_FIFO] = azx_get_pos_fifo, 1582 }; 1583 1584 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1585 1586 /* combo mode uses LPIB only for playback */ 1587 if (fix == POS_FIX_COMBO) 1588 chip->get_position[1] = NULL; 1589 1590 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1591 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1592 chip->get_delay[0] = chip->get_delay[1] = 1593 azx_get_delay_from_lpib; 1594 } 1595 1596 if (fix == POS_FIX_FIFO) 1597 chip->get_delay[0] = chip->get_delay[1] = 1598 azx_get_delay_from_fifo; 1599 } 1600 1601 /* 1602 * black-lists for probe_mask 1603 */ 1604 static const struct snd_pci_quirk probe_mask_list[] = { 1605 /* Thinkpad often breaks the controller communication when accessing 1606 * to the non-working (or non-existing) modem codec slot. 1607 */ 1608 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1609 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1610 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1611 /* broken BIOS */ 1612 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1613 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1614 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1615 /* forced codec slots */ 1616 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1617 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1618 /* WinFast VP200 H (Teradici) user reported broken communication */ 1619 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1620 {} 1621 }; 1622 1623 #define AZX_FORCE_CODEC_MASK 0x100 1624 1625 static void check_probe_mask(struct azx *chip, int dev) 1626 { 1627 const struct snd_pci_quirk *q; 1628 1629 chip->codec_probe_mask = probe_mask[dev]; 1630 if (chip->codec_probe_mask == -1) { 1631 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1632 if (q) { 1633 dev_info(chip->card->dev, 1634 "probe_mask set to 0x%x for device %04x:%04x\n", 1635 q->value, q->subvendor, q->subdevice); 1636 chip->codec_probe_mask = q->value; 1637 } 1638 } 1639 1640 /* check forced option */ 1641 if (chip->codec_probe_mask != -1 && 1642 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1643 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1644 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1645 (int)azx_bus(chip)->codec_mask); 1646 } 1647 } 1648 1649 /* 1650 * white/black-list for enable_msi 1651 */ 1652 static const struct snd_pci_quirk msi_black_list[] = { 1653 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1654 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1655 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1656 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1657 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1658 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1659 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1660 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1661 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1662 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1663 {} 1664 }; 1665 1666 static void check_msi(struct azx *chip) 1667 { 1668 const struct snd_pci_quirk *q; 1669 1670 if (enable_msi >= 0) { 1671 chip->msi = !!enable_msi; 1672 return; 1673 } 1674 chip->msi = 1; /* enable MSI as default */ 1675 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1676 if (q) { 1677 dev_info(chip->card->dev, 1678 "msi for device %04x:%04x set to %d\n", 1679 q->subvendor, q->subdevice, q->value); 1680 chip->msi = q->value; 1681 return; 1682 } 1683 1684 /* NVidia chipsets seem to cause troubles with MSI */ 1685 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1686 dev_info(chip->card->dev, "Disabling MSI\n"); 1687 chip->msi = 0; 1688 } 1689 } 1690 1691 /* check the snoop mode availability */ 1692 static void azx_check_snoop_available(struct azx *chip) 1693 { 1694 int snoop = hda_snoop; 1695 1696 if (snoop >= 0) { 1697 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1698 snoop ? "snoop" : "non-snoop"); 1699 chip->snoop = snoop; 1700 chip->uc_buffer = !snoop; 1701 return; 1702 } 1703 1704 snoop = true; 1705 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1706 chip->driver_type == AZX_DRIVER_VIA) { 1707 /* force to non-snoop mode for a new VIA controller 1708 * when BIOS is set 1709 */ 1710 u8 val; 1711 pci_read_config_byte(chip->pci, 0x42, &val); 1712 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1713 chip->pci->revision == 0x20)) 1714 snoop = false; 1715 } 1716 1717 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1718 snoop = false; 1719 1720 chip->snoop = snoop; 1721 if (!snoop) { 1722 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1723 /* C-Media requires non-cached pages only for CORB/RIRB */ 1724 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1725 chip->uc_buffer = true; 1726 } 1727 } 1728 1729 static void azx_probe_work(struct work_struct *work) 1730 { 1731 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1732 azx_probe_continue(&hda->chip); 1733 } 1734 1735 static int default_bdl_pos_adj(struct azx *chip) 1736 { 1737 /* some exceptions: Atoms seem problematic with value 1 */ 1738 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1739 switch (chip->pci->device) { 1740 case 0x0f04: /* Baytrail */ 1741 case 0x2284: /* Braswell */ 1742 return 32; 1743 } 1744 } 1745 1746 switch (chip->driver_type) { 1747 case AZX_DRIVER_ICH: 1748 case AZX_DRIVER_PCH: 1749 return 1; 1750 default: 1751 return 32; 1752 } 1753 } 1754 1755 /* 1756 * constructor 1757 */ 1758 static const struct hda_controller_ops pci_hda_ops; 1759 1760 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1761 int dev, unsigned int driver_caps, 1762 struct azx **rchip) 1763 { 1764 static const struct snd_device_ops ops = { 1765 .dev_disconnect = azx_dev_disconnect, 1766 .dev_free = azx_dev_free, 1767 }; 1768 struct hda_intel *hda; 1769 struct azx *chip; 1770 int err; 1771 1772 *rchip = NULL; 1773 1774 err = pci_enable_device(pci); 1775 if (err < 0) 1776 return err; 1777 1778 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1779 if (!hda) { 1780 pci_disable_device(pci); 1781 return -ENOMEM; 1782 } 1783 1784 chip = &hda->chip; 1785 mutex_init(&chip->open_mutex); 1786 chip->card = card; 1787 chip->pci = pci; 1788 chip->ops = &pci_hda_ops; 1789 chip->driver_caps = driver_caps; 1790 chip->driver_type = driver_caps & 0xff; 1791 check_msi(chip); 1792 chip->dev_index = dev; 1793 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1794 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1795 INIT_LIST_HEAD(&chip->pcm_list); 1796 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1797 INIT_LIST_HEAD(&hda->list); 1798 init_vga_switcheroo(chip); 1799 init_completion(&hda->probe_wait); 1800 1801 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1802 1803 check_probe_mask(chip, dev); 1804 1805 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1806 chip->fallback_to_single_cmd = 1; 1807 else /* explicitly set to single_cmd or not */ 1808 chip->single_cmd = single_cmd; 1809 1810 azx_check_snoop_available(chip); 1811 1812 if (bdl_pos_adj[dev] < 0) 1813 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1814 else 1815 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1816 1817 err = azx_bus_init(chip, model[dev]); 1818 if (err < 0) { 1819 pci_disable_device(pci); 1820 return err; 1821 } 1822 1823 /* use the non-cached pages in non-snoop mode */ 1824 if (!azx_snoop(chip)) 1825 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC; 1826 1827 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1828 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1829 chip->bus.core.needs_damn_long_delay = 1; 1830 } 1831 1832 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1833 if (err < 0) { 1834 dev_err(card->dev, "Error creating device [card]!\n"); 1835 azx_free(chip); 1836 return err; 1837 } 1838 1839 /* continue probing in work context as may trigger request module */ 1840 INIT_WORK(&hda->probe_work, azx_probe_work); 1841 1842 *rchip = chip; 1843 1844 return 0; 1845 } 1846 1847 static int azx_first_init(struct azx *chip) 1848 { 1849 int dev = chip->dev_index; 1850 struct pci_dev *pci = chip->pci; 1851 struct snd_card *card = chip->card; 1852 struct hdac_bus *bus = azx_bus(chip); 1853 int err; 1854 unsigned short gcap; 1855 unsigned int dma_bits = 64; 1856 1857 #if BITS_PER_LONG != 64 1858 /* Fix up base address on ULI M5461 */ 1859 if (chip->driver_type == AZX_DRIVER_ULI) { 1860 u16 tmp3; 1861 pci_read_config_word(pci, 0x40, &tmp3); 1862 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1863 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1864 } 1865 #endif 1866 1867 err = pci_request_regions(pci, "ICH HD audio"); 1868 if (err < 0) 1869 return err; 1870 chip->region_requested = 1; 1871 1872 bus->addr = pci_resource_start(pci, 0); 1873 bus->remap_addr = pci_ioremap_bar(pci, 0); 1874 if (bus->remap_addr == NULL) { 1875 dev_err(card->dev, "ioremap error\n"); 1876 return -ENXIO; 1877 } 1878 1879 if (chip->driver_type == AZX_DRIVER_SKL) 1880 snd_hdac_bus_parse_capabilities(bus); 1881 1882 /* 1883 * Some Intel CPUs has always running timer (ART) feature and 1884 * controller may have Global time sync reporting capability, so 1885 * check both of these before declaring synchronized time reporting 1886 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1887 */ 1888 chip->gts_present = false; 1889 1890 #ifdef CONFIG_X86 1891 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1892 chip->gts_present = true; 1893 #endif 1894 1895 if (chip->msi) { 1896 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1897 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1898 pci->no_64bit_msi = true; 1899 } 1900 if (pci_enable_msi(pci) < 0) 1901 chip->msi = 0; 1902 } 1903 1904 pci_set_master(pci); 1905 1906 gcap = azx_readw(chip, GCAP); 1907 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1908 1909 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1910 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1911 dma_bits = 40; 1912 1913 /* disable SB600 64bit support for safety */ 1914 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1915 struct pci_dev *p_smbus; 1916 dma_bits = 40; 1917 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1918 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1919 NULL); 1920 if (p_smbus) { 1921 if (p_smbus->revision < 0x30) 1922 gcap &= ~AZX_GCAP_64OK; 1923 pci_dev_put(p_smbus); 1924 } 1925 } 1926 1927 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1928 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1929 dma_bits = 40; 1930 1931 /* disable 64bit DMA address on some devices */ 1932 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1933 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1934 gcap &= ~AZX_GCAP_64OK; 1935 } 1936 1937 /* disable buffer size rounding to 128-byte multiples if supported */ 1938 if (align_buffer_size >= 0) 1939 chip->align_buffer_size = !!align_buffer_size; 1940 else { 1941 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1942 chip->align_buffer_size = 0; 1943 else 1944 chip->align_buffer_size = 1; 1945 } 1946 1947 /* allow 64bit DMA address if supported by H/W */ 1948 if (!(gcap & AZX_GCAP_64OK)) 1949 dma_bits = 32; 1950 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1951 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1952 } else { 1953 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1954 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1955 } 1956 1957 /* read number of streams from GCAP register instead of using 1958 * hardcoded value 1959 */ 1960 chip->capture_streams = (gcap >> 8) & 0x0f; 1961 chip->playback_streams = (gcap >> 12) & 0x0f; 1962 if (!chip->playback_streams && !chip->capture_streams) { 1963 /* gcap didn't give any info, switching to old method */ 1964 1965 switch (chip->driver_type) { 1966 case AZX_DRIVER_ULI: 1967 chip->playback_streams = ULI_NUM_PLAYBACK; 1968 chip->capture_streams = ULI_NUM_CAPTURE; 1969 break; 1970 case AZX_DRIVER_ATIHDMI: 1971 case AZX_DRIVER_ATIHDMI_NS: 1972 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1973 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1974 break; 1975 case AZX_DRIVER_GENERIC: 1976 default: 1977 chip->playback_streams = ICH6_NUM_PLAYBACK; 1978 chip->capture_streams = ICH6_NUM_CAPTURE; 1979 break; 1980 } 1981 } 1982 chip->capture_index_offset = 0; 1983 chip->playback_index_offset = chip->capture_streams; 1984 chip->num_streams = chip->playback_streams + chip->capture_streams; 1985 1986 /* sanity check for the SDxCTL.STRM field overflow */ 1987 if (chip->num_streams > 15 && 1988 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1989 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1990 "forcing separate stream tags", chip->num_streams); 1991 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1992 } 1993 1994 /* initialize streams */ 1995 err = azx_init_streams(chip); 1996 if (err < 0) 1997 return err; 1998 1999 err = azx_alloc_stream_pages(chip); 2000 if (err < 0) 2001 return err; 2002 2003 /* initialize chip */ 2004 azx_init_pci(chip); 2005 2006 snd_hdac_i915_set_bclk(bus); 2007 2008 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2009 2010 /* codec detection */ 2011 if (!azx_bus(chip)->codec_mask) { 2012 dev_err(card->dev, "no codecs found!\n"); 2013 /* keep running the rest for the runtime PM */ 2014 } 2015 2016 if (azx_acquire_irq(chip, 0) < 0) 2017 return -EBUSY; 2018 2019 strcpy(card->driver, "HDA-Intel"); 2020 strlcpy(card->shortname, driver_short_names[chip->driver_type], 2021 sizeof(card->shortname)); 2022 snprintf(card->longname, sizeof(card->longname), 2023 "%s at 0x%lx irq %i", 2024 card->shortname, bus->addr, bus->irq); 2025 2026 return 0; 2027 } 2028 2029 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2030 /* callback from request_firmware_nowait() */ 2031 static void azx_firmware_cb(const struct firmware *fw, void *context) 2032 { 2033 struct snd_card *card = context; 2034 struct azx *chip = card->private_data; 2035 2036 if (fw) 2037 chip->fw = fw; 2038 else 2039 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2040 if (!chip->disabled) { 2041 /* continue probing */ 2042 azx_probe_continue(chip); 2043 } 2044 } 2045 #endif 2046 2047 static int disable_msi_reset_irq(struct azx *chip) 2048 { 2049 struct hdac_bus *bus = azx_bus(chip); 2050 int err; 2051 2052 free_irq(bus->irq, chip); 2053 bus->irq = -1; 2054 chip->card->sync_irq = -1; 2055 pci_disable_msi(chip->pci); 2056 chip->msi = 0; 2057 err = azx_acquire_irq(chip, 1); 2058 if (err < 0) 2059 return err; 2060 2061 return 0; 2062 } 2063 2064 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2065 struct vm_area_struct *area) 2066 { 2067 #ifdef CONFIG_X86 2068 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2069 struct azx *chip = apcm->chip; 2070 if (chip->uc_buffer) 2071 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2072 #endif 2073 } 2074 2075 /* Blacklist for skipping the whole probe: 2076 * some HD-audio PCI entries are exposed without any codecs, and such devices 2077 * should be ignored from the beginning. 2078 */ 2079 static const struct pci_device_id driver_blacklist[] = { 2080 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2081 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2082 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2083 {} 2084 }; 2085 2086 static const struct hda_controller_ops pci_hda_ops = { 2087 .disable_msi_reset_irq = disable_msi_reset_irq, 2088 .pcm_mmap_prepare = pcm_mmap_prepare, 2089 .position_check = azx_position_check, 2090 }; 2091 2092 static int azx_probe(struct pci_dev *pci, 2093 const struct pci_device_id *pci_id) 2094 { 2095 static int dev; 2096 struct snd_card *card; 2097 struct hda_intel *hda; 2098 struct azx *chip; 2099 bool schedule_probe; 2100 int err; 2101 2102 if (pci_match_id(driver_blacklist, pci)) { 2103 dev_info(&pci->dev, "Skipping the blacklisted device\n"); 2104 return -ENODEV; 2105 } 2106 2107 if (dev >= SNDRV_CARDS) 2108 return -ENODEV; 2109 if (!enable[dev]) { 2110 dev++; 2111 return -ENOENT; 2112 } 2113 2114 /* 2115 * stop probe if another Intel's DSP driver should be activated 2116 */ 2117 if (dmic_detect) { 2118 err = snd_intel_dsp_driver_probe(pci); 2119 if (err != SND_INTEL_DSP_DRIVER_ANY && 2120 err != SND_INTEL_DSP_DRIVER_LEGACY) 2121 return -ENODEV; 2122 } else { 2123 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2124 } 2125 2126 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2127 0, &card); 2128 if (err < 0) { 2129 dev_err(&pci->dev, "Error creating card!\n"); 2130 return err; 2131 } 2132 2133 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2134 if (err < 0) 2135 goto out_free; 2136 card->private_data = chip; 2137 hda = container_of(chip, struct hda_intel, chip); 2138 2139 pci_set_drvdata(pci, card); 2140 2141 err = register_vga_switcheroo(chip); 2142 if (err < 0) { 2143 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2144 goto out_free; 2145 } 2146 2147 if (check_hdmi_disabled(pci)) { 2148 dev_info(card->dev, "VGA controller is disabled\n"); 2149 dev_info(card->dev, "Delaying initialization\n"); 2150 chip->disabled = true; 2151 } 2152 2153 schedule_probe = !chip->disabled; 2154 2155 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2156 if (patch[dev] && *patch[dev]) { 2157 dev_info(card->dev, "Applying patch firmware '%s'\n", 2158 patch[dev]); 2159 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2160 &pci->dev, GFP_KERNEL, card, 2161 azx_firmware_cb); 2162 if (err < 0) 2163 goto out_free; 2164 schedule_probe = false; /* continued in azx_firmware_cb() */ 2165 } 2166 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2167 2168 #ifndef CONFIG_SND_HDA_I915 2169 if (CONTROLLER_IN_GPU(pci)) 2170 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2171 #endif 2172 2173 if (schedule_probe) 2174 schedule_work(&hda->probe_work); 2175 2176 dev++; 2177 if (chip->disabled) 2178 complete_all(&hda->probe_wait); 2179 return 0; 2180 2181 out_free: 2182 snd_card_free(card); 2183 return err; 2184 } 2185 2186 #ifdef CONFIG_PM 2187 /* On some boards setting power_save to a non 0 value leads to clicking / 2188 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2189 * figure out how to avoid these sounds, but that is not always feasible. 2190 * So we keep a list of devices where we disable powersaving as its known 2191 * to causes problems on these devices. 2192 */ 2193 static const struct snd_pci_quirk power_save_blacklist[] = { 2194 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2195 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2196 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2197 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2198 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2199 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2200 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2201 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2202 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ 2203 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), 2204 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2205 SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0), 2206 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2207 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2208 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2209 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2210 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2211 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2212 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2213 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2214 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2215 /* https://bugs.launchpad.net/bugs/1821663 */ 2216 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2217 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2218 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2219 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2220 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2221 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2222 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2223 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2224 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2225 /* https://bugs.launchpad.net/bugs/1821663 */ 2226 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2227 {} 2228 }; 2229 #endif /* CONFIG_PM */ 2230 2231 static void set_default_power_save(struct azx *chip) 2232 { 2233 int val = power_save; 2234 2235 #ifdef CONFIG_PM 2236 if (pm_blacklist) { 2237 const struct snd_pci_quirk *q; 2238 2239 q = snd_pci_quirk_lookup(chip->pci, power_save_blacklist); 2240 if (q && val) { 2241 dev_info(chip->card->dev, "device %04x:%04x is on the power_save blacklist, forcing power_save to 0\n", 2242 q->subvendor, q->subdevice); 2243 val = 0; 2244 } 2245 } 2246 #endif /* CONFIG_PM */ 2247 snd_hda_set_power_save(&chip->bus, val * 1000); 2248 } 2249 2250 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2251 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2252 [AZX_DRIVER_NVIDIA] = 8, 2253 [AZX_DRIVER_TERA] = 1, 2254 }; 2255 2256 static int azx_probe_continue(struct azx *chip) 2257 { 2258 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2259 struct hdac_bus *bus = azx_bus(chip); 2260 struct pci_dev *pci = chip->pci; 2261 int dev = chip->dev_index; 2262 int err; 2263 2264 to_hda_bus(bus)->bus_probing = 1; 2265 hda->probe_continued = 1; 2266 2267 /* bind with i915 if needed */ 2268 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2269 err = snd_hdac_i915_init(bus); 2270 if (err < 0) { 2271 /* if the controller is bound only with HDMI/DP 2272 * (for HSW and BDW), we need to abort the probe; 2273 * for other chips, still continue probing as other 2274 * codecs can be on the same link. 2275 */ 2276 if (CONTROLLER_IN_GPU(pci)) { 2277 dev_err(chip->card->dev, 2278 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2279 goto out_free; 2280 } else { 2281 /* don't bother any longer */ 2282 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2283 } 2284 } 2285 2286 /* HSW/BDW controllers need this power */ 2287 if (CONTROLLER_IN_GPU(pci)) 2288 hda->need_i915_power = 1; 2289 } 2290 2291 /* Request display power well for the HDA controller or codec. For 2292 * Haswell/Broadwell, both the display HDA controller and codec need 2293 * this power. For other platforms, like Baytrail/Braswell, only the 2294 * display codec needs the power and it can be released after probe. 2295 */ 2296 display_power(chip, true); 2297 2298 err = azx_first_init(chip); 2299 if (err < 0) 2300 goto out_free; 2301 2302 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2303 chip->beep_mode = beep_mode[dev]; 2304 #endif 2305 2306 /* create codec instances */ 2307 if (bus->codec_mask) { 2308 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2309 if (err < 0) 2310 goto out_free; 2311 } 2312 2313 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2314 if (chip->fw) { 2315 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2316 chip->fw->data); 2317 if (err < 0) 2318 goto out_free; 2319 #ifndef CONFIG_PM 2320 release_firmware(chip->fw); /* no longer needed */ 2321 chip->fw = NULL; 2322 #endif 2323 } 2324 #endif 2325 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2326 err = azx_codec_configure(chip); 2327 if (err < 0) 2328 goto out_free; 2329 } 2330 2331 err = snd_card_register(chip->card); 2332 if (err < 0) 2333 goto out_free; 2334 2335 setup_vga_switcheroo_runtime_pm(chip); 2336 2337 chip->running = 1; 2338 azx_add_card_list(chip); 2339 2340 set_default_power_save(chip); 2341 2342 if (azx_has_pm_runtime(chip)) { 2343 pm_runtime_use_autosuspend(&pci->dev); 2344 pm_runtime_allow(&pci->dev); 2345 pm_runtime_put_autosuspend(&pci->dev); 2346 } 2347 2348 out_free: 2349 if (err < 0) { 2350 azx_free(chip); 2351 return err; 2352 } 2353 2354 if (!hda->need_i915_power) 2355 display_power(chip, false); 2356 complete_all(&hda->probe_wait); 2357 to_hda_bus(bus)->bus_probing = 0; 2358 return 0; 2359 } 2360 2361 static void azx_remove(struct pci_dev *pci) 2362 { 2363 struct snd_card *card = pci_get_drvdata(pci); 2364 struct azx *chip; 2365 struct hda_intel *hda; 2366 2367 if (card) { 2368 /* cancel the pending probing work */ 2369 chip = card->private_data; 2370 hda = container_of(chip, struct hda_intel, chip); 2371 /* FIXME: below is an ugly workaround. 2372 * Both device_release_driver() and driver_probe_device() 2373 * take *both* the device's and its parent's lock before 2374 * calling the remove() and probe() callbacks. The codec 2375 * probe takes the locks of both the codec itself and its 2376 * parent, i.e. the PCI controller dev. Meanwhile, when 2377 * the PCI controller is unbound, it takes its lock, too 2378 * ==> ouch, a deadlock! 2379 * As a workaround, we unlock temporarily here the controller 2380 * device during cancel_work_sync() call. 2381 */ 2382 device_unlock(&pci->dev); 2383 cancel_work_sync(&hda->probe_work); 2384 device_lock(&pci->dev); 2385 2386 snd_card_free(card); 2387 } 2388 } 2389 2390 static void azx_shutdown(struct pci_dev *pci) 2391 { 2392 struct snd_card *card = pci_get_drvdata(pci); 2393 struct azx *chip; 2394 2395 if (!card) 2396 return; 2397 chip = card->private_data; 2398 if (chip && chip->running) 2399 azx_stop_chip(chip); 2400 } 2401 2402 /* PCI IDs */ 2403 static const struct pci_device_id azx_ids[] = { 2404 /* CPT */ 2405 { PCI_DEVICE(0x8086, 0x1c20), 2406 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2407 /* PBG */ 2408 { PCI_DEVICE(0x8086, 0x1d20), 2409 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2410 /* Panther Point */ 2411 { PCI_DEVICE(0x8086, 0x1e20), 2412 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2413 /* Lynx Point */ 2414 { PCI_DEVICE(0x8086, 0x8c20), 2415 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2416 /* 9 Series */ 2417 { PCI_DEVICE(0x8086, 0x8ca0), 2418 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2419 /* Wellsburg */ 2420 { PCI_DEVICE(0x8086, 0x8d20), 2421 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2422 { PCI_DEVICE(0x8086, 0x8d21), 2423 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2424 /* Lewisburg */ 2425 { PCI_DEVICE(0x8086, 0xa1f0), 2426 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2427 { PCI_DEVICE(0x8086, 0xa270), 2428 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2429 /* Lynx Point-LP */ 2430 { PCI_DEVICE(0x8086, 0x9c20), 2431 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2432 /* Lynx Point-LP */ 2433 { PCI_DEVICE(0x8086, 0x9c21), 2434 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2435 /* Wildcat Point-LP */ 2436 { PCI_DEVICE(0x8086, 0x9ca0), 2437 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2438 /* Sunrise Point */ 2439 { PCI_DEVICE(0x8086, 0xa170), 2440 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2441 /* Sunrise Point-LP */ 2442 { PCI_DEVICE(0x8086, 0x9d70), 2443 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2444 /* Kabylake */ 2445 { PCI_DEVICE(0x8086, 0xa171), 2446 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2447 /* Kabylake-LP */ 2448 { PCI_DEVICE(0x8086, 0x9d71), 2449 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2450 /* Kabylake-H */ 2451 { PCI_DEVICE(0x8086, 0xa2f0), 2452 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2453 /* Coffelake */ 2454 { PCI_DEVICE(0x8086, 0xa348), 2455 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2456 /* Cannonlake */ 2457 { PCI_DEVICE(0x8086, 0x9dc8), 2458 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2459 /* CometLake-LP */ 2460 { PCI_DEVICE(0x8086, 0x02C8), 2461 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2462 /* CometLake-H */ 2463 { PCI_DEVICE(0x8086, 0x06C8), 2464 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2465 /* CometLake-S */ 2466 { PCI_DEVICE(0x8086, 0xa3f0), 2467 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2468 /* Icelake */ 2469 { PCI_DEVICE(0x8086, 0x34c8), 2470 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2471 /* Jasperlake */ 2472 { PCI_DEVICE(0x8086, 0x38c8), 2473 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2474 { PCI_DEVICE(0x8086, 0x4dc8), 2475 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2476 /* Tigerlake */ 2477 { PCI_DEVICE(0x8086, 0xa0c8), 2478 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2479 /* Elkhart Lake */ 2480 { PCI_DEVICE(0x8086, 0x4b55), 2481 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2482 /* Broxton-P(Apollolake) */ 2483 { PCI_DEVICE(0x8086, 0x5a98), 2484 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2485 /* Broxton-T */ 2486 { PCI_DEVICE(0x8086, 0x1a98), 2487 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2488 /* Gemini-Lake */ 2489 { PCI_DEVICE(0x8086, 0x3198), 2490 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2491 /* Haswell */ 2492 { PCI_DEVICE(0x8086, 0x0a0c), 2493 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2494 { PCI_DEVICE(0x8086, 0x0c0c), 2495 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2496 { PCI_DEVICE(0x8086, 0x0d0c), 2497 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2498 /* Broadwell */ 2499 { PCI_DEVICE(0x8086, 0x160c), 2500 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2501 /* 5 Series/3400 */ 2502 { PCI_DEVICE(0x8086, 0x3b56), 2503 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2504 /* Poulsbo */ 2505 { PCI_DEVICE(0x8086, 0x811b), 2506 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2507 /* Oaktrail */ 2508 { PCI_DEVICE(0x8086, 0x080a), 2509 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2510 /* BayTrail */ 2511 { PCI_DEVICE(0x8086, 0x0f04), 2512 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2513 /* Braswell */ 2514 { PCI_DEVICE(0x8086, 0x2284), 2515 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2516 /* ICH6 */ 2517 { PCI_DEVICE(0x8086, 0x2668), 2518 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2519 /* ICH7 */ 2520 { PCI_DEVICE(0x8086, 0x27d8), 2521 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2522 /* ESB2 */ 2523 { PCI_DEVICE(0x8086, 0x269a), 2524 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2525 /* ICH8 */ 2526 { PCI_DEVICE(0x8086, 0x284b), 2527 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2528 /* ICH9 */ 2529 { PCI_DEVICE(0x8086, 0x293e), 2530 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2531 /* ICH9 */ 2532 { PCI_DEVICE(0x8086, 0x293f), 2533 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2534 /* ICH10 */ 2535 { PCI_DEVICE(0x8086, 0x3a3e), 2536 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2537 /* ICH10 */ 2538 { PCI_DEVICE(0x8086, 0x3a6e), 2539 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2540 /* Generic Intel */ 2541 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2542 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2543 .class_mask = 0xffffff, 2544 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2545 /* ATI SB 450/600/700/800/900 */ 2546 { PCI_DEVICE(0x1002, 0x437b), 2547 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2548 { PCI_DEVICE(0x1002, 0x4383), 2549 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2550 /* AMD Hudson */ 2551 { PCI_DEVICE(0x1022, 0x780d), 2552 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2553 /* AMD, X370 & co */ 2554 { PCI_DEVICE(0x1022, 0x1457), 2555 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2556 /* AMD, X570 & co */ 2557 { PCI_DEVICE(0x1022, 0x1487), 2558 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2559 /* AMD Stoney */ 2560 { PCI_DEVICE(0x1022, 0x157a), 2561 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2562 AZX_DCAPS_PM_RUNTIME }, 2563 /* AMD Raven */ 2564 { PCI_DEVICE(0x1022, 0x15e3), 2565 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2566 /* ATI HDMI */ 2567 { PCI_DEVICE(0x1002, 0x0002), 2568 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2569 { PCI_DEVICE(0x1002, 0x1308), 2570 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2571 { PCI_DEVICE(0x1002, 0x157a), 2572 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2573 { PCI_DEVICE(0x1002, 0x15b3), 2574 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2575 { PCI_DEVICE(0x1002, 0x793b), 2576 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2577 { PCI_DEVICE(0x1002, 0x7919), 2578 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2579 { PCI_DEVICE(0x1002, 0x960f), 2580 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2581 { PCI_DEVICE(0x1002, 0x970f), 2582 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2583 { PCI_DEVICE(0x1002, 0x9840), 2584 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2585 { PCI_DEVICE(0x1002, 0xaa00), 2586 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2587 { PCI_DEVICE(0x1002, 0xaa08), 2588 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2589 { PCI_DEVICE(0x1002, 0xaa10), 2590 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2591 { PCI_DEVICE(0x1002, 0xaa18), 2592 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2593 { PCI_DEVICE(0x1002, 0xaa20), 2594 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2595 { PCI_DEVICE(0x1002, 0xaa28), 2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2597 { PCI_DEVICE(0x1002, 0xaa30), 2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2599 { PCI_DEVICE(0x1002, 0xaa38), 2600 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2601 { PCI_DEVICE(0x1002, 0xaa40), 2602 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2603 { PCI_DEVICE(0x1002, 0xaa48), 2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2605 { PCI_DEVICE(0x1002, 0xaa50), 2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2607 { PCI_DEVICE(0x1002, 0xaa58), 2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2609 { PCI_DEVICE(0x1002, 0xaa60), 2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2611 { PCI_DEVICE(0x1002, 0xaa68), 2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2613 { PCI_DEVICE(0x1002, 0xaa80), 2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2615 { PCI_DEVICE(0x1002, 0xaa88), 2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2617 { PCI_DEVICE(0x1002, 0xaa90), 2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2619 { PCI_DEVICE(0x1002, 0xaa98), 2620 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2621 { PCI_DEVICE(0x1002, 0x9902), 2622 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2623 { PCI_DEVICE(0x1002, 0xaaa0), 2624 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2625 { PCI_DEVICE(0x1002, 0xaaa8), 2626 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2627 { PCI_DEVICE(0x1002, 0xaab0), 2628 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2629 { PCI_DEVICE(0x1002, 0xaac0), 2630 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2631 { PCI_DEVICE(0x1002, 0xaac8), 2632 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2633 { PCI_DEVICE(0x1002, 0xaad8), 2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2635 AZX_DCAPS_PM_RUNTIME }, 2636 { PCI_DEVICE(0x1002, 0xaae0), 2637 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2638 AZX_DCAPS_PM_RUNTIME }, 2639 { PCI_DEVICE(0x1002, 0xaae8), 2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2641 AZX_DCAPS_PM_RUNTIME }, 2642 { PCI_DEVICE(0x1002, 0xaaf0), 2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2644 AZX_DCAPS_PM_RUNTIME }, 2645 { PCI_DEVICE(0x1002, 0xaaf8), 2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2647 AZX_DCAPS_PM_RUNTIME }, 2648 { PCI_DEVICE(0x1002, 0xab00), 2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2650 AZX_DCAPS_PM_RUNTIME }, 2651 { PCI_DEVICE(0x1002, 0xab08), 2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2653 AZX_DCAPS_PM_RUNTIME }, 2654 { PCI_DEVICE(0x1002, 0xab10), 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2656 AZX_DCAPS_PM_RUNTIME }, 2657 { PCI_DEVICE(0x1002, 0xab18), 2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2659 AZX_DCAPS_PM_RUNTIME }, 2660 { PCI_DEVICE(0x1002, 0xab20), 2661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2662 AZX_DCAPS_PM_RUNTIME }, 2663 { PCI_DEVICE(0x1002, 0xab28), 2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2665 AZX_DCAPS_PM_RUNTIME }, 2666 { PCI_DEVICE(0x1002, 0xab38), 2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2668 AZX_DCAPS_PM_RUNTIME }, 2669 /* VIA VT8251/VT8237A */ 2670 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2671 /* VIA GFX VT7122/VX900 */ 2672 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2673 /* VIA GFX VT6122/VX11 */ 2674 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2675 /* SIS966 */ 2676 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2677 /* ULI M5461 */ 2678 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2679 /* NVIDIA MCP */ 2680 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2681 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2682 .class_mask = 0xffffff, 2683 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2684 /* Teradici */ 2685 { PCI_DEVICE(0x6549, 0x1200), 2686 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2687 { PCI_DEVICE(0x6549, 0x2200), 2688 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2689 /* Creative X-Fi (CA0110-IBG) */ 2690 /* CTHDA chips */ 2691 { PCI_DEVICE(0x1102, 0x0010), 2692 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2693 { PCI_DEVICE(0x1102, 0x0012), 2694 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2695 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2696 /* the following entry conflicts with snd-ctxfi driver, 2697 * as ctxfi driver mutates from HD-audio to native mode with 2698 * a special command sequence. 2699 */ 2700 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2701 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2702 .class_mask = 0xffffff, 2703 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2704 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2705 #else 2706 /* this entry seems still valid -- i.e. without emu20kx chip */ 2707 { PCI_DEVICE(0x1102, 0x0009), 2708 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2709 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2710 #endif 2711 /* CM8888 */ 2712 { PCI_DEVICE(0x13f6, 0x5011), 2713 .driver_data = AZX_DRIVER_CMEDIA | 2714 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2715 /* Vortex86MX */ 2716 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2717 /* VMware HDAudio */ 2718 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2719 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2720 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2721 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2722 .class_mask = 0xffffff, 2723 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2724 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2725 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2726 .class_mask = 0xffffff, 2727 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2728 /* Zhaoxin */ 2729 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2730 { 0, } 2731 }; 2732 MODULE_DEVICE_TABLE(pci, azx_ids); 2733 2734 /* pci_driver definition */ 2735 static struct pci_driver azx_driver = { 2736 .name = KBUILD_MODNAME, 2737 .id_table = azx_ids, 2738 .probe = azx_probe, 2739 .remove = azx_remove, 2740 .shutdown = azx_shutdown, 2741 .driver = { 2742 .pm = AZX_PM_OPS, 2743 }, 2744 }; 2745 2746 module_pci_driver(azx_driver); 2747