xref: /openbmc/linux/sound/pci/es1968.c (revision e868d61272caa648214046a096e5a6bfc068dc8c)
1 /*
2  *  Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
3  *  Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
4  *                   Takashi Iwai <tiwai@suse.de>
5  *
6  *  Most of the driver code comes from Zach Brown(zab@redhat.com)
7  *	Alan Cox OSS Driver
8  *  Rewritted from card-es1938.c source.
9  *
10  *  TODO:
11  *   Perhaps Synth
12  *
13  *   This program is free software; you can redistribute it and/or modify
14  *   it under the terms of the GNU General Public License as published by
15  *   the Free Software Foundation; either version 2 of the License, or
16  *   (at your option) any later version.
17  *
18  *   This program is distributed in the hope that it will be useful,
19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21  *   GNU General Public License for more details.
22  *
23  *   You should have received a copy of the GNU General Public License
24  *   along with this program; if not, write to the Free Software
25  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
26  *
27  *
28  *  Notes from Zach Brown about the driver code
29  *
30  *  Hardware Description
31  *
32  *	A working Maestro setup contains the Maestro chip wired to a
33  *	codec or 2.  In the Maestro we have the APUs, the ASSP, and the
34  *	Wavecache.  The APUs can be though of as virtual audio routing
35  *	channels.  They can take data from a number of sources and perform
36  *	basic encodings of the data.  The wavecache is a storehouse for
37  *	PCM data.  Typically it deals with PCI and interracts with the
38  *	APUs.  The ASSP is a wacky DSP like device that ESS is loth
39  *	to release docs on.  Thankfully it isn't required on the Maestro
40  *	until you start doing insane things like FM emulation and surround
41  *	encoding.  The codecs are almost always AC-97 compliant codecs,
42  *	but it appears that early Maestros may have had PT101 (an ESS
43  *	part?) wired to them.  The only real difference in the Maestro
44  *	families is external goop like docking capability, memory for
45  *	the ASSP, and initialization differences.
46  *
47  *  Driver Operation
48  *
49  *	We only drive the APU/Wavecache as typical DACs and drive the
50  *	mixers in the codecs.  There are 64 APUs.  We assign 6 to each
51  *	/dev/dsp? device.  2 channels for output, and 4 channels for
52  *	input.
53  *
54  *	Each APU can do a number of things, but we only really use
55  *	3 basic functions.  For playback we use them to convert PCM
56  *	data fetched over PCI by the wavecahche into analog data that
57  *	is handed to the codec.  One APU for mono, and a pair for stereo.
58  *	When in stereo, the combination of smarts in the APU and Wavecache
59  *	decide which wavecache gets the left or right channel.
60  *
61  *	For record we still use the old overly mono system.  For each in
62  *	coming channel the data comes in from the codec, through a 'input'
63  *	APU, through another rate converter APU, and then into memory via
64  *	the wavecache and PCI.  If its stereo, we mash it back into LRLR in
65  *	software.  The pass between the 2 APUs is supposedly what requires us
66  *	to have a 512 byte buffer sitting around in wavecache/memory.
67  *
68  *	The wavecache makes our life even more fun.  First off, it can
69  *	only address the first 28 bits of PCI address space, making it
70  *	useless on quite a few architectures.  Secondly, its insane.
71  *	It claims to fetch from 4 regions of PCI space, each 4 meg in length.
72  *	But that doesn't really work.  You can only use 1 region.  So all our
73  *	allocations have to be in 4meg of each other.  Booo.  Hiss.
74  *	So we have a module parameter, dsps_order, that is the order of
75  *	the number of dsps to provide.  All their buffer space is allocated
76  *	on open time.  The sonicvibes OSS routines we inherited really want
77  *	power of 2 buffers, so we have all those next to each other, then
78  *	512 byte regions for the recording wavecaches.  This ends up
79  *	wasting quite a bit of memory.  The only fixes I can see would be
80  *	getting a kernel allocator that could work in zones, or figuring out
81  *	just how to coerce the WP into doing what we want.
82  *
83  *	The indirection of the various registers means we have to spinlock
84  *	nearly all register accesses.  We have the main register indirection
85  *	like the wave cache, maestro registers, etc.  Then we have beasts
86  *	like the APU interface that is indirect registers gotten at through
87  *	the main maestro indirection.  Ouch.  We spinlock around the actual
88  *	ports on a per card basis.  This means spinlock activity at each IO
89  *	operation, but the only IO operation clusters are in non critical
90  *	paths and it makes the code far easier to follow.  Interrupts are
91  *	blocked while holding the locks because the int handler has to
92  *	get at some of them :(.  The mixer interface doesn't, however.
93  *	We also have an OSS state lock that is thrown around in a few
94  *	places.
95  */
96 
97 #include <sound/driver.h>
98 #include <asm/io.h>
99 #include <linux/delay.h>
100 #include <linux/interrupt.h>
101 #include <linux/init.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/slab.h>
105 #include <linux/gameport.h>
106 #include <linux/moduleparam.h>
107 #include <linux/mutex.h>
108 
109 #include <sound/core.h>
110 #include <sound/pcm.h>
111 #include <sound/mpu401.h>
112 #include <sound/ac97_codec.h>
113 #include <sound/initval.h>
114 
115 #define CARD_NAME "ESS Maestro1/2"
116 #define DRIVER_NAME "ES1968"
117 
118 MODULE_DESCRIPTION("ESS Maestro");
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
121 		"{ESS,Maestro 2},"
122 		"{ESS,Maestro 1},"
123 		"{TerraTec,DMX}}");
124 
125 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
126 #define SUPPORT_JOYSTICK 1
127 #endif
128 
129 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 1-MAX */
130 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
131 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable this card */
132 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
133 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
134 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
135 static int clock[SNDRV_CARDS];
136 static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
137 static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
138 #ifdef SUPPORT_JOYSTICK
139 static int joystick[SNDRV_CARDS];
140 #endif
141 
142 module_param_array(index, int, NULL, 0444);
143 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
144 module_param_array(id, charp, NULL, 0444);
145 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
146 module_param_array(enable, bool, NULL, 0444);
147 MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
148 module_param_array(total_bufsize, int, NULL, 0444);
149 MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
150 module_param_array(pcm_substreams_p, int, NULL, 0444);
151 MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
152 module_param_array(pcm_substreams_c, int, NULL, 0444);
153 MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
154 module_param_array(clock, int, NULL, 0444);
155 MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard.  (0 = auto-detect)");
156 module_param_array(use_pm, int, NULL, 0444);
157 MODULE_PARM_DESC(use_pm, "Toggle power-management.  (0 = off, 1 = on, 2 = auto)");
158 module_param_array(enable_mpu, int, NULL, 0444);
159 MODULE_PARM_DESC(enable_mpu, "Enable MPU401.  (0 = off, 1 = on, 2 = auto)");
160 #ifdef SUPPORT_JOYSTICK
161 module_param_array(joystick, bool, NULL, 0444);
162 MODULE_PARM_DESC(joystick, "Enable joystick.");
163 #endif
164 
165 
166 #define NR_APUS			64
167 #define NR_APU_REGS		16
168 
169 /* NEC Versas ? */
170 #define NEC_VERSA_SUBID1	0x80581033
171 #define NEC_VERSA_SUBID2	0x803c1033
172 
173 /* Mode Flags */
174 #define ESS_FMT_STEREO     	0x01
175 #define ESS_FMT_16BIT      	0x02
176 
177 #define DAC_RUNNING		1
178 #define ADC_RUNNING		2
179 
180 /* Values for the ESM_LEGACY_AUDIO_CONTROL */
181 
182 #define ESS_DISABLE_AUDIO	0x8000
183 #define ESS_ENABLE_SERIAL_IRQ	0x4000
184 #define IO_ADRESS_ALIAS		0x0020
185 #define MPU401_IRQ_ENABLE	0x0010
186 #define MPU401_IO_ENABLE	0x0008
187 #define GAME_IO_ENABLE		0x0004
188 #define FM_IO_ENABLE		0x0002
189 #define SB_IO_ENABLE		0x0001
190 
191 /* Values for the ESM_CONFIG_A */
192 
193 #define PIC_SNOOP1		0x4000
194 #define PIC_SNOOP2		0x2000
195 #define SAFEGUARD		0x0800
196 #define DMA_CLEAR		0x0700
197 #define DMA_DDMA		0x0000
198 #define DMA_TDMA		0x0100
199 #define DMA_PCPCI		0x0200
200 #define POST_WRITE		0x0080
201 #define PCI_TIMING		0x0040
202 #define SWAP_LR			0x0020
203 #define SUBTR_DECODE		0x0002
204 
205 /* Values for the ESM_CONFIG_B */
206 
207 #define SPDIF_CONFB		0x0100
208 #define HWV_CONFB		0x0080
209 #define DEBOUNCE		0x0040
210 #define GPIO_CONFB		0x0020
211 #define CHI_CONFB		0x0010
212 #define IDMA_CONFB		0x0008	/*undoc */
213 #define MIDI_FIX		0x0004	/*undoc */
214 #define IRQ_TO_ISA		0x0001	/*undoc */
215 
216 /* Values for Ring Bus Control B */
217 #define	RINGB_2CODEC_ID_MASK	0x0003
218 #define RINGB_DIS_VALIDATION	0x0008
219 #define RINGB_EN_SPDIF		0x0010
220 #define	RINGB_EN_2CODEC		0x0020
221 #define RINGB_SING_BIT_DUAL	0x0040
222 
223 /* ****Port Adresses**** */
224 
225 /*   Write & Read */
226 #define ESM_INDEX		0x02
227 #define ESM_DATA		0x00
228 
229 /*   AC97 + RingBus */
230 #define ESM_AC97_INDEX		0x30
231 #define	ESM_AC97_DATA		0x32
232 #define ESM_RING_BUS_DEST	0x34
233 #define ESM_RING_BUS_CONTR_A	0x36
234 #define ESM_RING_BUS_CONTR_B	0x38
235 #define ESM_RING_BUS_SDO	0x3A
236 
237 /*   WaveCache*/
238 #define WC_INDEX		0x10
239 #define WC_DATA			0x12
240 #define WC_CONTROL		0x14
241 
242 /*   ASSP*/
243 #define ASSP_INDEX		0x80
244 #define ASSP_MEMORY		0x82
245 #define ASSP_DATA		0x84
246 #define ASSP_CONTROL_A		0xA2
247 #define ASSP_CONTROL_B		0xA4
248 #define ASSP_CONTROL_C		0xA6
249 #define ASSP_HOSTW_INDEX	0xA8
250 #define ASSP_HOSTW_DATA		0xAA
251 #define ASSP_HOSTW_IRQ		0xAC
252 /* Midi */
253 #define ESM_MPU401_PORT		0x98
254 /* Others */
255 #define ESM_PORT_HOST_IRQ	0x18
256 
257 #define IDR0_DATA_PORT		0x00
258 #define IDR1_CRAM_POINTER	0x01
259 #define IDR2_CRAM_DATA		0x02
260 #define IDR3_WAVE_DATA		0x03
261 #define IDR4_WAVE_PTR_LOW	0x04
262 #define IDR5_WAVE_PTR_HI	0x05
263 #define IDR6_TIMER_CTRL		0x06
264 #define IDR7_WAVE_ROMRAM	0x07
265 
266 #define WRITEABLE_MAP		0xEFFFFF
267 #define READABLE_MAP		0x64003F
268 
269 /* PCI Register */
270 
271 #define ESM_LEGACY_AUDIO_CONTROL 0x40
272 #define ESM_ACPI_COMMAND	0x54
273 #define ESM_CONFIG_A		0x50
274 #define ESM_CONFIG_B		0x52
275 #define ESM_DDMA		0x60
276 
277 /* Bob Bits */
278 #define ESM_BOB_ENABLE		0x0001
279 #define ESM_BOB_START		0x0001
280 
281 /* Host IRQ Control Bits */
282 #define ESM_RESET_MAESTRO	0x8000
283 #define ESM_RESET_DIRECTSOUND   0x4000
284 #define ESM_HIRQ_ClkRun		0x0100
285 #define ESM_HIRQ_HW_VOLUME	0x0040
286 #define ESM_HIRQ_HARPO		0x0030	/* What's that? */
287 #define ESM_HIRQ_ASSP		0x0010
288 #define	ESM_HIRQ_DSIE		0x0004
289 #define ESM_HIRQ_MPU401		0x0002
290 #define ESM_HIRQ_SB		0x0001
291 
292 /* Host IRQ Status Bits */
293 #define ESM_MPU401_IRQ		0x02
294 #define ESM_SB_IRQ		0x01
295 #define ESM_SOUND_IRQ		0x04
296 #define	ESM_ASSP_IRQ		0x10
297 #define ESM_HWVOL_IRQ		0x40
298 
299 #define ESS_SYSCLK		50000000
300 #define ESM_BOB_FREQ 		200
301 #define ESM_BOB_FREQ_MAX	800
302 
303 #define ESM_FREQ_ESM1  		(49152000L / 1024L)	/* default rate 48000 */
304 #define ESM_FREQ_ESM2  		(50000000L / 1024L)
305 
306 /* APU Modes: reg 0x00, bit 4-7 */
307 #define ESM_APU_MODE_SHIFT	4
308 #define ESM_APU_MODE_MASK	(0xf << 4)
309 #define	ESM_APU_OFF		0x00
310 #define	ESM_APU_16BITLINEAR	0x01	/* 16-Bit Linear Sample Player */
311 #define	ESM_APU_16BITSTEREO	0x02	/* 16-Bit Stereo Sample Player */
312 #define	ESM_APU_8BITLINEAR	0x03	/* 8-Bit Linear Sample Player */
313 #define	ESM_APU_8BITSTEREO	0x04	/* 8-Bit Stereo Sample Player */
314 #define	ESM_APU_8BITDIFF	0x05	/* 8-Bit Differential Sample Playrer */
315 #define	ESM_APU_DIGITALDELAY	0x06	/* Digital Delay Line */
316 #define	ESM_APU_DUALTAP		0x07	/* Dual Tap Reader */
317 #define	ESM_APU_CORRELATOR	0x08	/* Correlator */
318 #define	ESM_APU_INPUTMIXER	0x09	/* Input Mixer */
319 #define	ESM_APU_WAVETABLE	0x0A	/* Wave Table Mode */
320 #define	ESM_APU_SRCONVERTOR	0x0B	/* Sample Rate Convertor */
321 #define	ESM_APU_16BITPINGPONG	0x0C	/* 16-Bit Ping-Pong Sample Player */
322 #define	ESM_APU_RESERVED1	0x0D	/* Reserved 1 */
323 #define	ESM_APU_RESERVED2	0x0E	/* Reserved 2 */
324 #define	ESM_APU_RESERVED3	0x0F	/* Reserved 3 */
325 
326 /* reg 0x00 */
327 #define ESM_APU_FILTER_Q_SHIFT		0
328 #define ESM_APU_FILTER_Q_MASK		(3 << 0)
329 /* APU Filtey Q Control */
330 #define ESM_APU_FILTER_LESSQ	0x00
331 #define ESM_APU_FILTER_MOREQ	0x03
332 
333 #define ESM_APU_FILTER_TYPE_SHIFT	2
334 #define ESM_APU_FILTER_TYPE_MASK	(3 << 2)
335 #define ESM_APU_ENV_TYPE_SHIFT		8
336 #define ESM_APU_ENV_TYPE_MASK		(3 << 8)
337 #define ESM_APU_ENV_STATE_SHIFT		10
338 #define ESM_APU_ENV_STATE_MASK		(3 << 10)
339 #define ESM_APU_END_CURVE		(1 << 12)
340 #define ESM_APU_INT_ON_LOOP		(1 << 13)
341 #define ESM_APU_DMA_ENABLE		(1 << 14)
342 
343 /* reg 0x02 */
344 #define ESM_APU_SUBMIX_GROUP_SHIRT	0
345 #define ESM_APU_SUBMIX_GROUP_MASK	(7 << 0)
346 #define ESM_APU_SUBMIX_MODE		(1 << 3)
347 #define ESM_APU_6dB			(1 << 4)
348 #define ESM_APU_DUAL_EFFECT		(1 << 5)
349 #define ESM_APU_EFFECT_CHANNELS_SHIFT	6
350 #define ESM_APU_EFFECT_CHANNELS_MASK	(3 << 6)
351 
352 /* reg 0x03 */
353 #define ESM_APU_STEP_SIZE_MASK		0x0fff
354 
355 /* reg 0x04 */
356 #define ESM_APU_PHASE_SHIFT		0
357 #define ESM_APU_PHASE_MASK		(0xff << 0)
358 #define ESM_APU_WAVE64K_PAGE_SHIFT	8	/* most 8bit of wave start offset */
359 #define ESM_APU_WAVE64K_PAGE_MASK	(0xff << 8)
360 
361 /* reg 0x05 - wave start offset */
362 /* reg 0x06 - wave end offset */
363 /* reg 0x07 - wave loop length */
364 
365 /* reg 0x08 */
366 #define ESM_APU_EFFECT_GAIN_SHIFT	0
367 #define ESM_APU_EFFECT_GAIN_MASK	(0xff << 0)
368 #define ESM_APU_TREMOLO_DEPTH_SHIFT	8
369 #define ESM_APU_TREMOLO_DEPTH_MASK	(0xf << 8)
370 #define ESM_APU_TREMOLO_RATE_SHIFT	12
371 #define ESM_APU_TREMOLO_RATE_MASK	(0xf << 12)
372 
373 /* reg 0x09 */
374 /* bit 0-7 amplitude dest? */
375 #define ESM_APU_AMPLITUDE_NOW_SHIFT	8
376 #define ESM_APU_AMPLITUDE_NOW_MASK	(0xff << 8)
377 
378 /* reg 0x0a */
379 #define ESM_APU_POLAR_PAN_SHIFT		0
380 #define ESM_APU_POLAR_PAN_MASK		(0x3f << 0)
381 /* Polar Pan Control */
382 #define	ESM_APU_PAN_CENTER_CIRCLE		0x00
383 #define	ESM_APU_PAN_MIDDLE_RADIUS		0x01
384 #define	ESM_APU_PAN_OUTSIDE_RADIUS		0x02
385 
386 #define ESM_APU_FILTER_TUNING_SHIFT	8
387 #define ESM_APU_FILTER_TUNING_MASK	(0xff << 8)
388 
389 /* reg 0x0b */
390 #define ESM_APU_DATA_SRC_A_SHIFT	0
391 #define ESM_APU_DATA_SRC_A_MASK		(0x7f << 0)
392 #define ESM_APU_INV_POL_A		(1 << 7)
393 #define ESM_APU_DATA_SRC_B_SHIFT	8
394 #define ESM_APU_DATA_SRC_B_MASK		(0x7f << 8)
395 #define ESM_APU_INV_POL_B		(1 << 15)
396 
397 #define ESM_APU_VIBRATO_RATE_SHIFT	0
398 #define ESM_APU_VIBRATO_RATE_MASK	(0xf << 0)
399 #define ESM_APU_VIBRATO_DEPTH_SHIFT	4
400 #define ESM_APU_VIBRATO_DEPTH_MASK	(0xf << 4)
401 #define ESM_APU_VIBRATO_PHASE_SHIFT	8
402 #define ESM_APU_VIBRATO_PHASE_MASK	(0xff << 8)
403 
404 /* reg 0x0c */
405 #define ESM_APU_RADIUS_SELECT		(1 << 6)
406 
407 /* APU Filter Control */
408 #define	ESM_APU_FILTER_2POLE_LOPASS	0x00
409 #define	ESM_APU_FILTER_2POLE_BANDPASS	0x01
410 #define	ESM_APU_FILTER_2POLE_HIPASS	0x02
411 #define	ESM_APU_FILTER_1POLE_LOPASS	0x03
412 #define	ESM_APU_FILTER_1POLE_HIPASS	0x04
413 #define	ESM_APU_FILTER_OFF		0x05
414 
415 /* APU ATFP Type */
416 #define	ESM_APU_ATFP_AMPLITUDE			0x00
417 #define	ESM_APU_ATFP_TREMELO			0x01
418 #define	ESM_APU_ATFP_FILTER			0x02
419 #define	ESM_APU_ATFP_PAN			0x03
420 
421 /* APU ATFP Flags */
422 #define	ESM_APU_ATFP_FLG_OFF			0x00
423 #define	ESM_APU_ATFP_FLG_WAIT			0x01
424 #define	ESM_APU_ATFP_FLG_DONE			0x02
425 #define	ESM_APU_ATFP_FLG_INPROCESS		0x03
426 
427 
428 /* capture mixing buffer size */
429 #define ESM_MEM_ALIGN		0x1000
430 #define ESM_MIXBUF_SIZE		0x400
431 
432 #define ESM_MODE_PLAY		0
433 #define ESM_MODE_CAPTURE	1
434 
435 
436 /* APU use in the driver */
437 enum snd_enum_apu_type {
438 	ESM_APU_PCM_PLAY,
439 	ESM_APU_PCM_CAPTURE,
440 	ESM_APU_PCM_RATECONV,
441 	ESM_APU_FREE
442 };
443 
444 /* chip type */
445 enum {
446 	TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
447 };
448 
449 /* DMA Hack! */
450 struct esm_memory {
451 	struct snd_dma_buffer buf;
452 	int empty;	/* status */
453 	struct list_head list;
454 };
455 
456 /* Playback Channel */
457 struct esschan {
458 	int running;
459 
460 	u8 apu[4];
461 	u8 apu_mode[4];
462 
463 	/* playback/capture pcm buffer */
464 	struct esm_memory *memory;
465 	/* capture mixer buffer */
466 	struct esm_memory *mixbuf;
467 
468 	unsigned int hwptr;	/* current hw pointer in bytes */
469 	unsigned int count;	/* sample counter in bytes */
470 	unsigned int dma_size;	/* total buffer size in bytes */
471 	unsigned int frag_size;	/* period size in bytes */
472 	unsigned int wav_shift;
473 	u16 base[4];		/* offset for ptr */
474 
475 	/* stereo/16bit flag */
476 	unsigned char fmt;
477 	int mode;	/* playback / capture */
478 
479 	int bob_freq;	/* required timer frequency */
480 
481 	struct snd_pcm_substream *substream;
482 
483 	/* linked list */
484 	struct list_head list;
485 
486 #ifdef CONFIG_PM
487 	u16 wc_map[4];
488 #endif
489 };
490 
491 struct es1968 {
492 	/* Module Config */
493 	int total_bufsize;			/* in bytes */
494 
495 	int playback_streams, capture_streams;
496 
497 	unsigned int clock;		/* clock */
498 	/* for clock measurement */
499 	unsigned int in_measurement: 1;
500 	unsigned int measure_apu;
501 	unsigned int measure_lastpos;
502 	unsigned int measure_count;
503 
504 	/* buffer */
505 	struct snd_dma_buffer dma;
506 
507 	/* Resources... */
508 	int irq;
509 	unsigned long io_port;
510 	int type;
511 	struct pci_dev *pci;
512 	struct snd_card *card;
513 	struct snd_pcm *pcm;
514 	int do_pm;		/* power-management enabled */
515 
516 	/* DMA memory block */
517 	struct list_head buf_list;
518 
519 	/* ALSA Stuff */
520 	struct snd_ac97 *ac97;
521 	struct snd_kcontrol *master_switch; /* for h/w volume control */
522 	struct snd_kcontrol *master_volume;
523 
524 	struct snd_rawmidi *rmidi;
525 
526 	spinlock_t reg_lock;
527 	spinlock_t ac97_lock;
528 	struct tasklet_struct hwvol_tq;
529 	unsigned int in_suspend;
530 
531 	/* Maestro Stuff */
532 	u16 maestro_map[32];
533 	int bobclient;		/* active timer instancs */
534 	int bob_freq;		/* timer frequency */
535 	struct mutex memory_mutex;	/* memory lock */
536 
537 	/* APU states */
538 	unsigned char apu[NR_APUS];
539 
540 	/* active substreams */
541 	struct list_head substream_list;
542 	spinlock_t substream_lock;
543 
544 #ifdef CONFIG_PM
545 	u16 apu_map[NR_APUS][NR_APU_REGS];
546 #endif
547 
548 #ifdef SUPPORT_JOYSTICK
549 	struct gameport *gameport;
550 #endif
551 };
552 
553 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id);
554 
555 static struct pci_device_id snd_es1968_ids[] = {
556 	/* Maestro 1 */
557         { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
558 	/* Maestro 2 */
559 	{ 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
560 	/* Maestro 2E */
561         { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
562 	{ 0, }
563 };
564 
565 MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
566 
567 /* *********************
568    * Low Level Funcs!  *
569    *********************/
570 
571 /* no spinlock */
572 static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
573 {
574 	outw(reg, chip->io_port + ESM_INDEX);
575 	outw(data, chip->io_port + ESM_DATA);
576 	chip->maestro_map[reg] = data;
577 }
578 
579 static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
580 {
581 	unsigned long flags;
582 	spin_lock_irqsave(&chip->reg_lock, flags);
583 	__maestro_write(chip, reg, data);
584 	spin_unlock_irqrestore(&chip->reg_lock, flags);
585 }
586 
587 /* no spinlock */
588 static u16 __maestro_read(struct es1968 *chip, u16 reg)
589 {
590 	if (READABLE_MAP & (1 << reg)) {
591 		outw(reg, chip->io_port + ESM_INDEX);
592 		chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
593 	}
594 	return chip->maestro_map[reg];
595 }
596 
597 static inline u16 maestro_read(struct es1968 *chip, u16 reg)
598 {
599 	unsigned long flags;
600 	u16 result;
601 	spin_lock_irqsave(&chip->reg_lock, flags);
602 	result = __maestro_read(chip, reg);
603 	spin_unlock_irqrestore(&chip->reg_lock, flags);
604 	return result;
605 }
606 
607 /* Wait for the codec bus to be free */
608 static int snd_es1968_ac97_wait(struct es1968 *chip)
609 {
610 	int timeout = 100000;
611 
612 	while (timeout-- > 0) {
613 		if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
614 			return 0;
615 		cond_resched();
616 	}
617 	snd_printd("es1968: ac97 timeout\n");
618 	return 1; /* timeout */
619 }
620 
621 static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
622 {
623 	struct es1968 *chip = ac97->private_data;
624 	unsigned long flags;
625 
626 	snd_es1968_ac97_wait(chip);
627 
628 	/* Write the bus */
629 	spin_lock_irqsave(&chip->ac97_lock, flags);
630 	outw(val, chip->io_port + ESM_AC97_DATA);
631 	/*msleep(1);*/
632 	outb(reg, chip->io_port + ESM_AC97_INDEX);
633 	/*msleep(1);*/
634 	spin_unlock_irqrestore(&chip->ac97_lock, flags);
635 }
636 
637 static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
638 {
639 	u16 data = 0;
640 	struct es1968 *chip = ac97->private_data;
641 	unsigned long flags;
642 
643 	snd_es1968_ac97_wait(chip);
644 
645 	spin_lock_irqsave(&chip->ac97_lock, flags);
646 	outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
647 	/*msleep(1);*/
648 
649 	if (! snd_es1968_ac97_wait(chip)) {
650 		data = inw(chip->io_port + ESM_AC97_DATA);
651 		/*msleep(1);*/
652 	}
653 	spin_unlock_irqrestore(&chip->ac97_lock, flags);
654 
655 	return data;
656 }
657 
658 /* no spinlock */
659 static void apu_index_set(struct es1968 *chip, u16 index)
660 {
661 	int i;
662 	__maestro_write(chip, IDR1_CRAM_POINTER, index);
663 	for (i = 0; i < 1000; i++)
664 		if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
665 			return;
666 	snd_printd("es1968: APU register select failed. (Timeout)\n");
667 }
668 
669 /* no spinlock */
670 static void apu_data_set(struct es1968 *chip, u16 data)
671 {
672 	int i;
673 	for (i = 0; i < 1000; i++) {
674 		if (__maestro_read(chip, IDR0_DATA_PORT) == data)
675 			return;
676 		__maestro_write(chip, IDR0_DATA_PORT, data);
677 	}
678 	snd_printd("es1968: APU register set probably failed (Timeout)!\n");
679 }
680 
681 /* no spinlock */
682 static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
683 {
684 	snd_assert(channel < NR_APUS, return);
685 #ifdef CONFIG_PM
686 	chip->apu_map[channel][reg] = data;
687 #endif
688 	reg |= (channel << 4);
689 	apu_index_set(chip, reg);
690 	apu_data_set(chip, data);
691 }
692 
693 static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
694 {
695 	unsigned long flags;
696 	spin_lock_irqsave(&chip->reg_lock, flags);
697 	__apu_set_register(chip, channel, reg, data);
698 	spin_unlock_irqrestore(&chip->reg_lock, flags);
699 }
700 
701 static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
702 {
703 	snd_assert(channel < NR_APUS, return 0);
704 	reg |= (channel << 4);
705 	apu_index_set(chip, reg);
706 	return __maestro_read(chip, IDR0_DATA_PORT);
707 }
708 
709 static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
710 {
711 	unsigned long flags;
712 	u16 v;
713 	spin_lock_irqsave(&chip->reg_lock, flags);
714 	v = __apu_get_register(chip, channel, reg);
715 	spin_unlock_irqrestore(&chip->reg_lock, flags);
716 	return v;
717 }
718 
719 #if 0 /* ASSP is not supported */
720 
721 static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
722 {
723 	unsigned long flags;
724 
725 	spin_lock_irqsave(&chip->reg_lock, flags);
726 	outl(reg, chip->io_port + ASSP_INDEX);
727 	outl(value, chip->io_port + ASSP_DATA);
728 	spin_unlock_irqrestore(&chip->reg_lock, flags);
729 }
730 
731 static u32 assp_get_register(struct es1968 *chip, u32 reg)
732 {
733 	unsigned long flags;
734 	u32 value;
735 
736 	spin_lock_irqsave(&chip->reg_lock, flags);
737 	outl(reg, chip->io_port + ASSP_INDEX);
738 	value = inl(chip->io_port + ASSP_DATA);
739 	spin_unlock_irqrestore(&chip->reg_lock, flags);
740 
741 	return value;
742 }
743 
744 #endif
745 
746 static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
747 {
748 	unsigned long flags;
749 
750 	spin_lock_irqsave(&chip->reg_lock, flags);
751 	outw(reg, chip->io_port + WC_INDEX);
752 	outw(value, chip->io_port + WC_DATA);
753 	spin_unlock_irqrestore(&chip->reg_lock, flags);
754 }
755 
756 static u16 wave_get_register(struct es1968 *chip, u16 reg)
757 {
758 	unsigned long flags;
759 	u16 value;
760 
761 	spin_lock_irqsave(&chip->reg_lock, flags);
762 	outw(reg, chip->io_port + WC_INDEX);
763 	value = inw(chip->io_port + WC_DATA);
764 	spin_unlock_irqrestore(&chip->reg_lock, flags);
765 
766 	return value;
767 }
768 
769 /* *******************
770    * Bob the Timer!  *
771    *******************/
772 
773 static void snd_es1968_bob_stop(struct es1968 *chip)
774 {
775 	u16 reg;
776 
777 	reg = __maestro_read(chip, 0x11);
778 	reg &= ~ESM_BOB_ENABLE;
779 	__maestro_write(chip, 0x11, reg);
780 	reg = __maestro_read(chip, 0x17);
781 	reg &= ~ESM_BOB_START;
782 	__maestro_write(chip, 0x17, reg);
783 }
784 
785 static void snd_es1968_bob_start(struct es1968 *chip)
786 {
787 	int prescale;
788 	int divide;
789 
790 	/* compute ideal interrupt frequency for buffer size & play rate */
791 	/* first, find best prescaler value to match freq */
792 	for (prescale = 5; prescale < 12; prescale++)
793 		if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
794 			break;
795 
796 	/* next, back off prescaler whilst getting divider into optimum range */
797 	divide = 1;
798 	while ((prescale > 5) && (divide < 32)) {
799 		prescale--;
800 		divide <<= 1;
801 	}
802 	divide >>= 1;
803 
804 	/* now fine-tune the divider for best match */
805 	for (; divide < 31; divide++)
806 		if (chip->bob_freq >
807 		    ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
808 
809 	/* divide = 0 is illegal, but don't let prescale = 4! */
810 	if (divide == 0) {
811 		divide++;
812 		if (prescale > 5)
813 			prescale--;
814 	} else if (divide > 1)
815 		divide--;
816 
817 	__maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide);	/* set reg */
818 
819 	/* Now set IDR 11/17 */
820 	__maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
821 	__maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
822 }
823 
824 /* call with substream spinlock */
825 static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
826 {
827 	chip->bobclient++;
828 	if (chip->bobclient == 1) {
829 		chip->bob_freq = freq;
830 		snd_es1968_bob_start(chip);
831 	} else if (chip->bob_freq < freq) {
832 		snd_es1968_bob_stop(chip);
833 		chip->bob_freq = freq;
834 		snd_es1968_bob_start(chip);
835 	}
836 }
837 
838 /* call with substream spinlock */
839 static void snd_es1968_bob_dec(struct es1968 *chip)
840 {
841 	chip->bobclient--;
842 	if (chip->bobclient <= 0)
843 		snd_es1968_bob_stop(chip);
844 	else if (chip->bob_freq > ESM_BOB_FREQ) {
845 		/* check reduction of timer frequency */
846 		struct list_head *p;
847 		int max_freq = ESM_BOB_FREQ;
848 		list_for_each(p, &chip->substream_list) {
849 			struct esschan *es = list_entry(p, struct esschan, list);
850 			if (max_freq < es->bob_freq)
851 				max_freq = es->bob_freq;
852 		}
853 		if (max_freq != chip->bob_freq) {
854 			snd_es1968_bob_stop(chip);
855 			chip->bob_freq = max_freq;
856 			snd_es1968_bob_start(chip);
857 		}
858 	}
859 }
860 
861 static int
862 snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
863 			 struct snd_pcm_runtime *runtime)
864 {
865 	/* we acquire 4 interrupts per period for precise control.. */
866 	int freq = runtime->rate * 4;
867 	if (es->fmt & ESS_FMT_STEREO)
868 		freq <<= 1;
869 	if (es->fmt & ESS_FMT_16BIT)
870 		freq <<= 1;
871 	freq /= es->frag_size;
872 	if (freq < ESM_BOB_FREQ)
873 		freq = ESM_BOB_FREQ;
874 	else if (freq > ESM_BOB_FREQ_MAX)
875 		freq = ESM_BOB_FREQ_MAX;
876 	return freq;
877 }
878 
879 
880 /*************
881  *  PCM Part *
882  *************/
883 
884 static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
885 {
886 	u32 rate = (freq << 16) / chip->clock;
887 #if 0 /* XXX: do we need this? */
888 	if (rate > 0x10000)
889 		rate = 0x10000;
890 #endif
891 	return rate;
892 }
893 
894 /* get current pointer */
895 static inline unsigned int
896 snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
897 {
898 	unsigned int offset;
899 
900 	offset = apu_get_register(chip, es->apu[0], 5);
901 
902 	offset -= es->base[0];
903 
904 	return (offset & 0xFFFE);	/* hardware is in words */
905 }
906 
907 static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
908 {
909 	apu_set_register(chip, apu, 2,
910 			   (apu_get_register(chip, apu, 2) & 0x00FF) |
911 			   ((freq & 0xff) << 8) | 0x10);
912 	apu_set_register(chip, apu, 3, freq >> 8);
913 }
914 
915 /* spin lock held */
916 static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
917 {
918 	/* set the APU mode */
919 	__apu_set_register(esm, apu, 0,
920 			   (__apu_get_register(esm, apu, 0) & 0xff0f) |
921 			   (mode << 4));
922 }
923 
924 static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
925 {
926 	spin_lock(&chip->reg_lock);
927 	__apu_set_register(chip, es->apu[0], 5, es->base[0]);
928 	snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
929 	if (es->mode == ESM_MODE_CAPTURE) {
930 		__apu_set_register(chip, es->apu[2], 5, es->base[2]);
931 		snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
932 	}
933 	if (es->fmt & ESS_FMT_STEREO) {
934 		__apu_set_register(chip, es->apu[1], 5, es->base[1]);
935 		snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
936 		if (es->mode == ESM_MODE_CAPTURE) {
937 			__apu_set_register(chip, es->apu[3], 5, es->base[3]);
938 			snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
939 		}
940 	}
941 	spin_unlock(&chip->reg_lock);
942 }
943 
944 static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
945 {
946 	spin_lock(&chip->reg_lock);
947 	snd_es1968_trigger_apu(chip, es->apu[0], 0);
948 	snd_es1968_trigger_apu(chip, es->apu[1], 0);
949 	if (es->mode == ESM_MODE_CAPTURE) {
950 		snd_es1968_trigger_apu(chip, es->apu[2], 0);
951 		snd_es1968_trigger_apu(chip, es->apu[3], 0);
952 	}
953 	spin_unlock(&chip->reg_lock);
954 }
955 
956 /* set the wavecache control reg */
957 static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
958 					 int channel, u32 addr, int capture)
959 {
960 	u32 tmpval = (addr - 0x10) & 0xFFF8;
961 
962 	if (! capture) {
963 		if (!(es->fmt & ESS_FMT_16BIT))
964 			tmpval |= 4;	/* 8bit */
965 		if (es->fmt & ESS_FMT_STEREO)
966 			tmpval |= 2;	/* stereo */
967 	}
968 
969 	/* set the wavecache control reg */
970 	wave_set_register(chip, es->apu[channel] << 3, tmpval);
971 
972 #ifdef CONFIG_PM
973 	es->wc_map[channel] = tmpval;
974 #endif
975 }
976 
977 
978 static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
979 				      struct snd_pcm_runtime *runtime)
980 {
981 	u32 pa;
982 	int high_apu = 0;
983 	int channel, apu;
984 	int i, size;
985 	unsigned long flags;
986 	u32 freq;
987 
988 	size = es->dma_size >> es->wav_shift;
989 
990 	if (es->fmt & ESS_FMT_STEREO)
991 		high_apu++;
992 
993 	for (channel = 0; channel <= high_apu; channel++) {
994 		apu = es->apu[channel];
995 
996 		snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
997 
998 		/* Offset to PCMBAR */
999 		pa = es->memory->buf.addr;
1000 		pa -= chip->dma.addr;
1001 		pa >>= 1;	/* words */
1002 
1003 		pa |= 0x00400000;	/* System RAM (Bit 22) */
1004 
1005 		if (es->fmt & ESS_FMT_STEREO) {
1006 			/* Enable stereo */
1007 			if (channel)
1008 				pa |= 0x00800000;	/* (Bit 23) */
1009 			if (es->fmt & ESS_FMT_16BIT)
1010 				pa >>= 1;
1011 		}
1012 
1013 		/* base offset of dma calcs when reading the pointer
1014 		   on this left one */
1015 		es->base[channel] = pa & 0xFFFF;
1016 
1017 		for (i = 0; i < 16; i++)
1018 			apu_set_register(chip, apu, i, 0x0000);
1019 
1020 		/* Load the buffer into the wave engine */
1021 		apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1022 		apu_set_register(chip, apu, 5, pa & 0xFFFF);
1023 		apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1024 		/* setting loop == sample len */
1025 		apu_set_register(chip, apu, 7, size);
1026 
1027 		/* clear effects/env.. */
1028 		apu_set_register(chip, apu, 8, 0x0000);
1029 		/* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1030 		apu_set_register(chip, apu, 9, 0xD000);
1031 
1032 		/* clear routing stuff */
1033 		apu_set_register(chip, apu, 11, 0x0000);
1034 		/* dma on, no envelopes, filter to all 1s) */
1035 		apu_set_register(chip, apu, 0, 0x400F);
1036 
1037 		if (es->fmt & ESS_FMT_16BIT)
1038 			es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1039 		else
1040 			es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1041 
1042 		if (es->fmt & ESS_FMT_STEREO) {
1043 			/* set panning: left or right */
1044 			/* Check: different panning. On my Canyon 3D Chipset the
1045 			   Channels are swapped. I don't know, about the output
1046 			   to the SPDif Link. Perhaps you have to change this
1047 			   and not the APU Regs 4-5. */
1048 			apu_set_register(chip, apu, 10,
1049 					 0x8F00 | (channel ? 0 : 0x10));
1050 			es->apu_mode[channel] += 1;	/* stereo */
1051 		} else
1052 			apu_set_register(chip, apu, 10, 0x8F08);
1053 	}
1054 
1055 	spin_lock_irqsave(&chip->reg_lock, flags);
1056 	/* clear WP interrupts */
1057 	outw(1, chip->io_port + 0x04);
1058 	/* enable WP ints */
1059 	outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1060 	spin_unlock_irqrestore(&chip->reg_lock, flags);
1061 
1062 	freq = runtime->rate;
1063 	/* set frequency */
1064 	if (freq > 48000)
1065 		freq = 48000;
1066 	if (freq < 4000)
1067 		freq = 4000;
1068 
1069 	/* hmmm.. */
1070 	if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1071 		freq >>= 1;
1072 
1073 	freq = snd_es1968_compute_rate(chip, freq);
1074 
1075 	/* Load the frequency, turn on 6dB */
1076 	snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1077 	snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1078 }
1079 
1080 
1081 static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
1082 			     unsigned int pa, unsigned int bsize,
1083 			     int mode, int route)
1084 {
1085 	int i, apu = es->apu[channel];
1086 
1087 	es->apu_mode[channel] = mode;
1088 
1089 	/* set the wavecache control reg */
1090 	snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1091 
1092 	/* Offset to PCMBAR */
1093 	pa -= chip->dma.addr;
1094 	pa >>= 1;	/* words */
1095 
1096 	/* base offset of dma calcs when reading the pointer
1097 	   on this left one */
1098 	es->base[channel] = pa & 0xFFFF;
1099 	pa |= 0x00400000;	/* bit 22 -> System RAM */
1100 
1101 	/* Begin loading the APU */
1102 	for (i = 0; i < 16; i++)
1103 		apu_set_register(chip, apu, i, 0x0000);
1104 
1105 	/* need to enable subgroups.. and we should probably
1106 	   have different groups for different /dev/dsps..  */
1107 	apu_set_register(chip, apu, 2, 0x8);
1108 
1109 	/* Load the buffer into the wave engine */
1110 	apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1111 	apu_set_register(chip, apu, 5, pa & 0xFFFF);
1112 	apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1113 	apu_set_register(chip, apu, 7, bsize);
1114 	/* clear effects/env.. */
1115 	apu_set_register(chip, apu, 8, 0x00F0);
1116 	/* amplitude now?  sure.  why not.  */
1117 	apu_set_register(chip, apu, 9, 0x0000);
1118 	/* set filter tune, radius, polar pan */
1119 	apu_set_register(chip, apu, 10, 0x8F08);
1120 	/* route input */
1121 	apu_set_register(chip, apu, 11, route);
1122 	/* dma on, no envelopes, filter to all 1s) */
1123 	apu_set_register(chip, apu, 0, 0x400F);
1124 }
1125 
1126 static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
1127 				     struct snd_pcm_runtime *runtime)
1128 {
1129 	int size;
1130 	u32 freq;
1131 	unsigned long flags;
1132 
1133 	size = es->dma_size >> es->wav_shift;
1134 
1135 	/* APU assignments:
1136 	   0 = mono/left SRC
1137 	   1 = right SRC
1138 	   2 = mono/left Input Mixer
1139 	   3 = right Input Mixer
1140 	*/
1141 	/* data seems to flow from the codec, through an apu into
1142 	   the 'mixbuf' bit of page, then through the SRC apu
1143 	   and out to the real 'buffer'.  ok.  sure.  */
1144 
1145 	/* input mixer (left/mono) */
1146 	/* parallel in crap, see maestro reg 0xC [8-11] */
1147 	init_capture_apu(chip, es, 2,
1148 			 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1149 			 ESM_APU_INPUTMIXER, 0x14);
1150 	/* SRC (left/mono); get input from inputing apu */
1151 	init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1152 			 ESM_APU_SRCONVERTOR, es->apu[2]);
1153 	if (es->fmt & ESS_FMT_STEREO) {
1154 		/* input mixer (right) */
1155 		init_capture_apu(chip, es, 3,
1156 				 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1157 				 ESM_MIXBUF_SIZE/4, /* in words */
1158 				 ESM_APU_INPUTMIXER, 0x15);
1159 		/* SRC (right) */
1160 		init_capture_apu(chip, es, 1,
1161 				 es->memory->buf.addr + size*2, size,
1162 				 ESM_APU_SRCONVERTOR, es->apu[3]);
1163 	}
1164 
1165 	freq = runtime->rate;
1166 	/* Sample Rate conversion APUs don't like 0x10000 for their rate */
1167 	if (freq > 47999)
1168 		freq = 47999;
1169 	if (freq < 4000)
1170 		freq = 4000;
1171 
1172 	freq = snd_es1968_compute_rate(chip, freq);
1173 
1174 	/* Load the frequency, turn on 6dB */
1175 	snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1176 	snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1177 
1178 	/* fix mixer rate at 48khz.  and its _must_ be 0x10000. */
1179 	freq = 0x10000;
1180 	snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1181 	snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1182 
1183 	spin_lock_irqsave(&chip->reg_lock, flags);
1184 	/* clear WP interrupts */
1185 	outw(1, chip->io_port + 0x04);
1186 	/* enable WP ints */
1187 	outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1188 	spin_unlock_irqrestore(&chip->reg_lock, flags);
1189 }
1190 
1191 /*******************
1192  *  ALSA Interface *
1193  *******************/
1194 
1195 static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
1196 {
1197 	struct es1968 *chip = snd_pcm_substream_chip(substream);
1198 	struct snd_pcm_runtime *runtime = substream->runtime;
1199 	struct esschan *es = runtime->private_data;
1200 
1201 	es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1202 	es->frag_size = snd_pcm_lib_period_bytes(substream);
1203 
1204 	es->wav_shift = 1; /* maestro handles always 16bit */
1205 	es->fmt = 0;
1206 	if (snd_pcm_format_width(runtime->format) == 16)
1207 		es->fmt |= ESS_FMT_16BIT;
1208 	if (runtime->channels > 1) {
1209 		es->fmt |= ESS_FMT_STEREO;
1210 		if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1211 			es->wav_shift++;
1212 	}
1213 	es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1214 
1215 	switch (es->mode) {
1216 	case ESM_MODE_PLAY:
1217 		snd_es1968_playback_setup(chip, es, runtime);
1218 		break;
1219 	case ESM_MODE_CAPTURE:
1220 		snd_es1968_capture_setup(chip, es, runtime);
1221 		break;
1222 	}
1223 
1224 	return 0;
1225 }
1226 
1227 static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1228 {
1229 	struct es1968 *chip = snd_pcm_substream_chip(substream);
1230 	struct esschan *es = substream->runtime->private_data;
1231 
1232 	spin_lock(&chip->substream_lock);
1233 	switch (cmd) {
1234 	case SNDRV_PCM_TRIGGER_START:
1235 	case SNDRV_PCM_TRIGGER_RESUME:
1236 		if (es->running)
1237 			break;
1238 		snd_es1968_bob_inc(chip, es->bob_freq);
1239 		es->count = 0;
1240 		es->hwptr = 0;
1241 		snd_es1968_pcm_start(chip, es);
1242 		es->running = 1;
1243 		break;
1244 	case SNDRV_PCM_TRIGGER_STOP:
1245 	case SNDRV_PCM_TRIGGER_SUSPEND:
1246 		if (! es->running)
1247 			break;
1248 		snd_es1968_pcm_stop(chip, es);
1249 		es->running = 0;
1250 		snd_es1968_bob_dec(chip);
1251 		break;
1252 	}
1253 	spin_unlock(&chip->substream_lock);
1254 	return 0;
1255 }
1256 
1257 static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
1258 {
1259 	struct es1968 *chip = snd_pcm_substream_chip(substream);
1260 	struct esschan *es = substream->runtime->private_data;
1261 	unsigned int ptr;
1262 
1263 	ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1264 
1265 	return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1266 }
1267 
1268 static struct snd_pcm_hardware snd_es1968_playback = {
1269 	.info =			(SNDRV_PCM_INFO_MMAP |
1270                		         SNDRV_PCM_INFO_MMAP_VALID |
1271 				 SNDRV_PCM_INFO_INTERLEAVED |
1272 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1273 				 /*SNDRV_PCM_INFO_PAUSE |*/
1274 				 SNDRV_PCM_INFO_RESUME),
1275 	.formats =		SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1276 	.rates =		SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1277 	.rate_min =		4000,
1278 	.rate_max =		48000,
1279 	.channels_min =		1,
1280 	.channels_max =		2,
1281 	.buffer_bytes_max =	65536,
1282 	.period_bytes_min =	256,
1283 	.period_bytes_max =	65536,
1284 	.periods_min =		1,
1285 	.periods_max =		1024,
1286 	.fifo_size =		0,
1287 };
1288 
1289 static struct snd_pcm_hardware snd_es1968_capture = {
1290 	.info =			(SNDRV_PCM_INFO_NONINTERLEAVED |
1291 				 SNDRV_PCM_INFO_MMAP |
1292 				 SNDRV_PCM_INFO_MMAP_VALID |
1293 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1294 				 /*SNDRV_PCM_INFO_PAUSE |*/
1295 				 SNDRV_PCM_INFO_RESUME),
1296 	.formats =		/*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1297 	.rates =		SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1298 	.rate_min =		4000,
1299 	.rate_max =		48000,
1300 	.channels_min =		1,
1301 	.channels_max =		2,
1302 	.buffer_bytes_max =	65536,
1303 	.period_bytes_min =	256,
1304 	.period_bytes_max =	65536,
1305 	.periods_min =		1,
1306 	.periods_max =		1024,
1307 	.fifo_size =		0,
1308 };
1309 
1310 /* *************************
1311    * DMA memory management *
1312    *************************/
1313 
1314 /* Because the Maestro can only take addresses relative to the PCM base address
1315    register :( */
1316 
1317 static int calc_available_memory_size(struct es1968 *chip)
1318 {
1319 	struct list_head *p;
1320 	int max_size = 0;
1321 
1322 	mutex_lock(&chip->memory_mutex);
1323 	list_for_each(p, &chip->buf_list) {
1324 		struct esm_memory *buf = list_entry(p, struct esm_memory, list);
1325 		if (buf->empty && buf->buf.bytes > max_size)
1326 			max_size = buf->buf.bytes;
1327 	}
1328 	mutex_unlock(&chip->memory_mutex);
1329 	if (max_size >= 128*1024)
1330 		max_size = 127*1024;
1331 	return max_size;
1332 }
1333 
1334 /* allocate a new memory chunk with the specified size */
1335 static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
1336 {
1337 	struct esm_memory *buf;
1338 	struct list_head *p;
1339 
1340 	size = ALIGN(size, ESM_MEM_ALIGN);
1341 	mutex_lock(&chip->memory_mutex);
1342 	list_for_each(p, &chip->buf_list) {
1343 		buf = list_entry(p, struct esm_memory, list);
1344 		if (buf->empty && buf->buf.bytes >= size)
1345 			goto __found;
1346 	}
1347 	mutex_unlock(&chip->memory_mutex);
1348 	return NULL;
1349 
1350 __found:
1351 	if (buf->buf.bytes > size) {
1352 		struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1353 		if (chunk == NULL) {
1354 			mutex_unlock(&chip->memory_mutex);
1355 			return NULL;
1356 		}
1357 		chunk->buf = buf->buf;
1358 		chunk->buf.bytes -= size;
1359 		chunk->buf.area += size;
1360 		chunk->buf.addr += size;
1361 		chunk->empty = 1;
1362 		buf->buf.bytes = size;
1363 		list_add(&chunk->list, &buf->list);
1364 	}
1365 	buf->empty = 0;
1366 	mutex_unlock(&chip->memory_mutex);
1367 	return buf;
1368 }
1369 
1370 /* free a memory chunk */
1371 static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
1372 {
1373 	struct esm_memory *chunk;
1374 
1375 	mutex_lock(&chip->memory_mutex);
1376 	buf->empty = 1;
1377 	if (buf->list.prev != &chip->buf_list) {
1378 		chunk = list_entry(buf->list.prev, struct esm_memory, list);
1379 		if (chunk->empty) {
1380 			chunk->buf.bytes += buf->buf.bytes;
1381 			list_del(&buf->list);
1382 			kfree(buf);
1383 			buf = chunk;
1384 		}
1385 	}
1386 	if (buf->list.next != &chip->buf_list) {
1387 		chunk = list_entry(buf->list.next, struct esm_memory, list);
1388 		if (chunk->empty) {
1389 			buf->buf.bytes += chunk->buf.bytes;
1390 			list_del(&chunk->list);
1391 			kfree(chunk);
1392 		}
1393 	}
1394 	mutex_unlock(&chip->memory_mutex);
1395 }
1396 
1397 static void snd_es1968_free_dmabuf(struct es1968 *chip)
1398 {
1399 	struct list_head *p;
1400 
1401 	if (! chip->dma.area)
1402 		return;
1403 	snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci));
1404 	while ((p = chip->buf_list.next) != &chip->buf_list) {
1405 		struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
1406 		list_del(p);
1407 		kfree(chunk);
1408 	}
1409 }
1410 
1411 static int __devinit
1412 snd_es1968_init_dmabuf(struct es1968 *chip)
1413 {
1414 	int err;
1415 	struct esm_memory *chunk;
1416 
1417 	chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
1418 	chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
1419 	if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) {
1420 		err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1421 						   snd_dma_pci_data(chip->pci),
1422 						   chip->total_bufsize, &chip->dma);
1423 		if (err < 0 || ! chip->dma.area) {
1424 			snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n",
1425 				   chip->total_bufsize);
1426 			return -ENOMEM;
1427 		}
1428 		if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1429 			snd_dma_free_pages(&chip->dma);
1430 			snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n");
1431 			return -ENOMEM;
1432 		}
1433 	}
1434 
1435 	INIT_LIST_HEAD(&chip->buf_list);
1436 	/* allocate an empty chunk */
1437 	chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1438 	if (chunk == NULL) {
1439 		snd_es1968_free_dmabuf(chip);
1440 		return -ENOMEM;
1441 	}
1442 	memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1443 	chunk->buf = chip->dma;
1444 	chunk->buf.area += ESM_MEM_ALIGN;
1445 	chunk->buf.addr += ESM_MEM_ALIGN;
1446 	chunk->buf.bytes -= ESM_MEM_ALIGN;
1447 	chunk->empty = 1;
1448 	list_add(&chunk->list, &chip->buf_list);
1449 
1450 	return 0;
1451 }
1452 
1453 /* setup the dma_areas */
1454 /* buffer is extracted from the pre-allocated memory chunk */
1455 static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
1456 				struct snd_pcm_hw_params *hw_params)
1457 {
1458 	struct es1968 *chip = snd_pcm_substream_chip(substream);
1459 	struct snd_pcm_runtime *runtime = substream->runtime;
1460 	struct esschan *chan = runtime->private_data;
1461 	int size = params_buffer_bytes(hw_params);
1462 
1463 	if (chan->memory) {
1464 		if (chan->memory->buf.bytes >= size) {
1465 			runtime->dma_bytes = size;
1466 			return 0;
1467 		}
1468 		snd_es1968_free_memory(chip, chan->memory);
1469 	}
1470 	chan->memory = snd_es1968_new_memory(chip, size);
1471 	if (chan->memory == NULL) {
1472 		// snd_printd("cannot allocate dma buffer: size = %d\n", size);
1473 		return -ENOMEM;
1474 	}
1475 	snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1476 	return 1; /* area was changed */
1477 }
1478 
1479 /* remove dma areas if allocated */
1480 static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
1481 {
1482 	struct es1968 *chip = snd_pcm_substream_chip(substream);
1483 	struct snd_pcm_runtime *runtime = substream->runtime;
1484 	struct esschan *chan;
1485 
1486 	if (runtime->private_data == NULL)
1487 		return 0;
1488 	chan = runtime->private_data;
1489 	if (chan->memory) {
1490 		snd_es1968_free_memory(chip, chan->memory);
1491 		chan->memory = NULL;
1492 	}
1493 	return 0;
1494 }
1495 
1496 
1497 /*
1498  * allocate APU pair
1499  */
1500 static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
1501 {
1502 	int apu;
1503 
1504 	for (apu = 0; apu < NR_APUS; apu += 2) {
1505 		if (chip->apu[apu] == ESM_APU_FREE &&
1506 		    chip->apu[apu + 1] == ESM_APU_FREE) {
1507 			chip->apu[apu] = chip->apu[apu + 1] = type;
1508 			return apu;
1509 		}
1510 	}
1511 	return -EBUSY;
1512 }
1513 
1514 /*
1515  * release APU pair
1516  */
1517 static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
1518 {
1519 	chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1520 }
1521 
1522 
1523 /******************
1524  * PCM open/close *
1525  ******************/
1526 
1527 static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
1528 {
1529 	struct es1968 *chip = snd_pcm_substream_chip(substream);
1530 	struct snd_pcm_runtime *runtime = substream->runtime;
1531 	struct esschan *es;
1532 	int apu1;
1533 
1534 	/* search 2 APUs */
1535 	apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1536 	if (apu1 < 0)
1537 		return apu1;
1538 
1539 	es = kzalloc(sizeof(*es), GFP_KERNEL);
1540 	if (!es) {
1541 		snd_es1968_free_apu_pair(chip, apu1);
1542 		return -ENOMEM;
1543 	}
1544 
1545 	es->apu[0] = apu1;
1546 	es->apu[1] = apu1 + 1;
1547 	es->apu_mode[0] = 0;
1548 	es->apu_mode[1] = 0;
1549 	es->running = 0;
1550 	es->substream = substream;
1551 	es->mode = ESM_MODE_PLAY;
1552 
1553 	runtime->private_data = es;
1554 	runtime->hw = snd_es1968_playback;
1555 	runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1556 		calc_available_memory_size(chip);
1557 
1558 	spin_lock_irq(&chip->substream_lock);
1559 	list_add(&es->list, &chip->substream_list);
1560 	spin_unlock_irq(&chip->substream_lock);
1561 
1562 	return 0;
1563 }
1564 
1565 static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
1566 {
1567 	struct snd_pcm_runtime *runtime = substream->runtime;
1568 	struct es1968 *chip = snd_pcm_substream_chip(substream);
1569 	struct esschan *es;
1570 	int apu1, apu2;
1571 
1572 	apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1573 	if (apu1 < 0)
1574 		return apu1;
1575 	apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1576 	if (apu2 < 0) {
1577 		snd_es1968_free_apu_pair(chip, apu1);
1578 		return apu2;
1579 	}
1580 
1581 	es = kzalloc(sizeof(*es), GFP_KERNEL);
1582 	if (!es) {
1583 		snd_es1968_free_apu_pair(chip, apu1);
1584 		snd_es1968_free_apu_pair(chip, apu2);
1585 		return -ENOMEM;
1586 	}
1587 
1588 	es->apu[0] = apu1;
1589 	es->apu[1] = apu1 + 1;
1590 	es->apu[2] = apu2;
1591 	es->apu[3] = apu2 + 1;
1592 	es->apu_mode[0] = 0;
1593 	es->apu_mode[1] = 0;
1594 	es->apu_mode[2] = 0;
1595 	es->apu_mode[3] = 0;
1596 	es->running = 0;
1597 	es->substream = substream;
1598 	es->mode = ESM_MODE_CAPTURE;
1599 
1600 	/* get mixbuffer */
1601 	if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1602 		snd_es1968_free_apu_pair(chip, apu1);
1603 		snd_es1968_free_apu_pair(chip, apu2);
1604 		kfree(es);
1605                 return -ENOMEM;
1606         }
1607 	memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1608 
1609 	runtime->private_data = es;
1610 	runtime->hw = snd_es1968_capture;
1611 	runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1612 		calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1613 	snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
1614 
1615 	spin_lock_irq(&chip->substream_lock);
1616 	list_add(&es->list, &chip->substream_list);
1617 	spin_unlock_irq(&chip->substream_lock);
1618 
1619 	return 0;
1620 }
1621 
1622 static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
1623 {
1624 	struct es1968 *chip = snd_pcm_substream_chip(substream);
1625 	struct esschan *es;
1626 
1627 	if (substream->runtime->private_data == NULL)
1628 		return 0;
1629 	es = substream->runtime->private_data;
1630 	spin_lock_irq(&chip->substream_lock);
1631 	list_del(&es->list);
1632 	spin_unlock_irq(&chip->substream_lock);
1633 	snd_es1968_free_apu_pair(chip, es->apu[0]);
1634 	kfree(es);
1635 
1636 	return 0;
1637 }
1638 
1639 static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
1640 {
1641 	struct es1968 *chip = snd_pcm_substream_chip(substream);
1642 	struct esschan *es;
1643 
1644 	if (substream->runtime->private_data == NULL)
1645 		return 0;
1646 	es = substream->runtime->private_data;
1647 	spin_lock_irq(&chip->substream_lock);
1648 	list_del(&es->list);
1649 	spin_unlock_irq(&chip->substream_lock);
1650 	snd_es1968_free_memory(chip, es->mixbuf);
1651 	snd_es1968_free_apu_pair(chip, es->apu[0]);
1652 	snd_es1968_free_apu_pair(chip, es->apu[2]);
1653 	kfree(es);
1654 
1655 	return 0;
1656 }
1657 
1658 static struct snd_pcm_ops snd_es1968_playback_ops = {
1659 	.open =		snd_es1968_playback_open,
1660 	.close =	snd_es1968_playback_close,
1661 	.ioctl =	snd_pcm_lib_ioctl,
1662 	.hw_params =	snd_es1968_hw_params,
1663 	.hw_free =	snd_es1968_hw_free,
1664 	.prepare =	snd_es1968_pcm_prepare,
1665 	.trigger =	snd_es1968_pcm_trigger,
1666 	.pointer =	snd_es1968_pcm_pointer,
1667 };
1668 
1669 static struct snd_pcm_ops snd_es1968_capture_ops = {
1670 	.open =		snd_es1968_capture_open,
1671 	.close =	snd_es1968_capture_close,
1672 	.ioctl =	snd_pcm_lib_ioctl,
1673 	.hw_params =	snd_es1968_hw_params,
1674 	.hw_free =	snd_es1968_hw_free,
1675 	.prepare =	snd_es1968_pcm_prepare,
1676 	.trigger =	snd_es1968_pcm_trigger,
1677 	.pointer =	snd_es1968_pcm_pointer,
1678 };
1679 
1680 
1681 /*
1682  * measure clock
1683  */
1684 #define CLOCK_MEASURE_BUFSIZE	16768	/* enough large for a single shot */
1685 
1686 static void __devinit es1968_measure_clock(struct es1968 *chip)
1687 {
1688 	int i, apu;
1689 	unsigned int pa, offset, t;
1690 	struct esm_memory *memory;
1691 	struct timeval start_time, stop_time;
1692 
1693 	if (chip->clock == 0)
1694 		chip->clock = 48000; /* default clock value */
1695 
1696 	/* search 2 APUs (although one apu is enough) */
1697 	if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
1698 		snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n");
1699 		return;
1700 	}
1701 	if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
1702 		snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock);
1703 		snd_es1968_free_apu_pair(chip, apu);
1704 		return;
1705 	}
1706 
1707 	memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1708 
1709 	wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1710 
1711 	pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1712 	pa |= 0x00400000;	/* System RAM (Bit 22) */
1713 
1714 	/* initialize apu */
1715 	for (i = 0; i < 16; i++)
1716 		apu_set_register(chip, apu, i, 0x0000);
1717 
1718 	apu_set_register(chip, apu, 0, 0x400f);
1719 	apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1720 	apu_set_register(chip, apu, 5, pa & 0xffff);
1721 	apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1722 	apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1723 	apu_set_register(chip, apu, 8, 0x0000);
1724 	apu_set_register(chip, apu, 9, 0xD000);
1725 	apu_set_register(chip, apu, 10, 0x8F08);
1726 	apu_set_register(chip, apu, 11, 0x0000);
1727 	spin_lock_irq(&chip->reg_lock);
1728 	outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1729 	outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1730 	spin_unlock_irq(&chip->reg_lock);
1731 
1732 	snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1733 
1734 	chip->in_measurement = 1;
1735 	chip->measure_apu = apu;
1736 	spin_lock_irq(&chip->reg_lock);
1737 	snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1738 	__apu_set_register(chip, apu, 5, pa & 0xffff);
1739 	snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1740 	do_gettimeofday(&start_time);
1741 	spin_unlock_irq(&chip->reg_lock);
1742 	msleep(50);
1743 	spin_lock_irq(&chip->reg_lock);
1744 	offset = __apu_get_register(chip, apu, 5);
1745 	do_gettimeofday(&stop_time);
1746 	snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1747 	snd_es1968_bob_dec(chip);
1748 	chip->in_measurement = 0;
1749 	spin_unlock_irq(&chip->reg_lock);
1750 
1751 	/* check the current position */
1752 	offset -= (pa & 0xffff);
1753 	offset &= 0xfffe;
1754 	offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1755 
1756 	t = stop_time.tv_sec - start_time.tv_sec;
1757 	t *= 1000000;
1758 	if (stop_time.tv_usec < start_time.tv_usec)
1759 		t -= start_time.tv_usec - stop_time.tv_usec;
1760 	else
1761 		t += stop_time.tv_usec - start_time.tv_usec;
1762 	if (t == 0) {
1763 		snd_printk(KERN_ERR "?? calculation error..\n");
1764 	} else {
1765 		offset *= 1000;
1766 		offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1767 		if (offset < 47500 || offset > 48500) {
1768 			if (offset >= 40000 && offset <= 50000)
1769 				chip->clock = (chip->clock * offset) / 48000;
1770 		}
1771 		printk(KERN_INFO "es1968: clocking to %d\n", chip->clock);
1772 	}
1773 	snd_es1968_free_memory(chip, memory);
1774 	snd_es1968_free_apu_pair(chip, apu);
1775 }
1776 
1777 
1778 /*
1779  */
1780 
1781 static void snd_es1968_pcm_free(struct snd_pcm *pcm)
1782 {
1783 	struct es1968 *esm = pcm->private_data;
1784 	snd_es1968_free_dmabuf(esm);
1785 	esm->pcm = NULL;
1786 }
1787 
1788 static int __devinit
1789 snd_es1968_pcm(struct es1968 *chip, int device)
1790 {
1791 	struct snd_pcm *pcm;
1792 	int err;
1793 
1794 	/* get DMA buffer */
1795 	if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1796 		return err;
1797 
1798 	/* set PCMBAR */
1799 	wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1800 	wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1801 	wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1802 	wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1803 
1804 	if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1805 			       chip->playback_streams,
1806 			       chip->capture_streams, &pcm)) < 0)
1807 		return err;
1808 
1809 	pcm->private_data = chip;
1810 	pcm->private_free = snd_es1968_pcm_free;
1811 
1812 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1813 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1814 
1815 	pcm->info_flags = 0;
1816 
1817 	strcpy(pcm->name, "ESS Maestro");
1818 
1819 	chip->pcm = pcm;
1820 
1821 	return 0;
1822 }
1823 
1824 /*
1825  * update pointer
1826  */
1827 static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
1828 {
1829 	unsigned int hwptr;
1830 	unsigned int diff;
1831 	struct snd_pcm_substream *subs = es->substream;
1832 
1833 	if (subs == NULL || !es->running)
1834 		return;
1835 
1836 	hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1837 	hwptr %= es->dma_size;
1838 
1839 	diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1840 
1841 	es->hwptr = hwptr;
1842 	es->count += diff;
1843 
1844 	if (es->count > es->frag_size) {
1845 		spin_unlock(&chip->substream_lock);
1846 		snd_pcm_period_elapsed(subs);
1847 		spin_lock(&chip->substream_lock);
1848 		es->count %= es->frag_size;
1849 	}
1850 }
1851 
1852 /*
1853  */
1854 static void es1968_update_hw_volume(unsigned long private_data)
1855 {
1856 	struct es1968 *chip = (struct es1968 *) private_data;
1857 	int x, val;
1858 	unsigned long flags;
1859 
1860 	/* Figure out which volume control button was pushed,
1861 	   based on differences from the default register
1862 	   values. */
1863 	x = inb(chip->io_port + 0x1c) & 0xee;
1864 	/* Reset the volume control registers. */
1865 	outb(0x88, chip->io_port + 0x1c);
1866 	outb(0x88, chip->io_port + 0x1d);
1867 	outb(0x88, chip->io_port + 0x1e);
1868 	outb(0x88, chip->io_port + 0x1f);
1869 
1870 	if (chip->in_suspend)
1871 		return;
1872 
1873 	if (! chip->master_switch || ! chip->master_volume)
1874 		return;
1875 
1876 	/* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1877 	spin_lock_irqsave(&chip->ac97_lock, flags);
1878 	val = chip->ac97->regs[AC97_MASTER];
1879 	switch (x) {
1880 	case 0x88:
1881 		/* mute */
1882 		val ^= 0x8000;
1883 		chip->ac97->regs[AC97_MASTER] = val;
1884 		outw(val, chip->io_port + ESM_AC97_DATA);
1885 		outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1886 		snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1887 			       &chip->master_switch->id);
1888 		break;
1889 	case 0xaa:
1890 		/* volume up */
1891 		if ((val & 0x7f) > 0)
1892 			val--;
1893 		if ((val & 0x7f00) > 0)
1894 			val -= 0x0100;
1895 		chip->ac97->regs[AC97_MASTER] = val;
1896 		outw(val, chip->io_port + ESM_AC97_DATA);
1897 		outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1898 		snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1899 			       &chip->master_volume->id);
1900 		break;
1901 	case 0x66:
1902 		/* volume down */
1903 		if ((val & 0x7f) < 0x1f)
1904 			val++;
1905 		if ((val & 0x7f00) < 0x1f00)
1906 			val += 0x0100;
1907 		chip->ac97->regs[AC97_MASTER] = val;
1908 		outw(val, chip->io_port + ESM_AC97_DATA);
1909 		outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1910 		snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1911 			       &chip->master_volume->id);
1912 		break;
1913 	}
1914 	spin_unlock_irqrestore(&chip->ac97_lock, flags);
1915 }
1916 
1917 /*
1918  * interrupt handler
1919  */
1920 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id)
1921 {
1922 	struct es1968 *chip = dev_id;
1923 	u32 event;
1924 
1925 	if (!(event = inb(chip->io_port + 0x1A)))
1926 		return IRQ_NONE;
1927 
1928 	outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1929 
1930 	if (event & ESM_HWVOL_IRQ)
1931 		tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */
1932 
1933 	/* else ack 'em all, i imagine */
1934 	outb(0xFF, chip->io_port + 0x1A);
1935 
1936 	if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
1937 		snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1938 	}
1939 
1940 	if (event & ESM_SOUND_IRQ) {
1941 		struct list_head *p;
1942 		spin_lock(&chip->substream_lock);
1943 		list_for_each(p, &chip->substream_list) {
1944 			struct esschan *es = list_entry(p, struct esschan, list);
1945 			if (es->running)
1946 				snd_es1968_update_pcm(chip, es);
1947 		}
1948 		spin_unlock(&chip->substream_lock);
1949 		if (chip->in_measurement) {
1950 			unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
1951 			if (curp < chip->measure_lastpos)
1952 				chip->measure_count++;
1953 			chip->measure_lastpos = curp;
1954 		}
1955 	}
1956 
1957 	return IRQ_HANDLED;
1958 }
1959 
1960 /*
1961  *  Mixer stuff
1962  */
1963 
1964 static int __devinit
1965 snd_es1968_mixer(struct es1968 *chip)
1966 {
1967 	struct snd_ac97_bus *pbus;
1968 	struct snd_ac97_template ac97;
1969 	struct snd_ctl_elem_id id;
1970 	int err;
1971 	static struct snd_ac97_bus_ops ops = {
1972 		.write = snd_es1968_ac97_write,
1973 		.read = snd_es1968_ac97_read,
1974 	};
1975 
1976 	if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
1977 		return err;
1978 	pbus->no_vra = 1; /* ES1968 doesn't need VRA */
1979 
1980 	memset(&ac97, 0, sizeof(ac97));
1981 	ac97.private_data = chip;
1982 	if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
1983 		return err;
1984 
1985 	/* attach master switch / volumes for h/w volume control */
1986 	memset(&id, 0, sizeof(id));
1987 	id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1988 	strcpy(id.name, "Master Playback Switch");
1989 	chip->master_switch = snd_ctl_find_id(chip->card, &id);
1990 	memset(&id, 0, sizeof(id));
1991 	id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1992 	strcpy(id.name, "Master Playback Volume");
1993 	chip->master_volume = snd_ctl_find_id(chip->card, &id);
1994 
1995 	return 0;
1996 }
1997 
1998 /*
1999  * reset ac97 codec
2000  */
2001 
2002 static void snd_es1968_ac97_reset(struct es1968 *chip)
2003 {
2004 	unsigned long ioaddr = chip->io_port;
2005 
2006 	unsigned short save_ringbus_a;
2007 	unsigned short save_68;
2008 	unsigned short w;
2009 	unsigned int vend;
2010 
2011 	/* save configuration */
2012 	save_ringbus_a = inw(ioaddr + 0x36);
2013 
2014 	//outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2015 	/* set command/status address i/o to 1st codec */
2016 	outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2017 	outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2018 
2019 	/* disable ac link */
2020 	outw(0x0000, ioaddr + 0x36);
2021 	save_68 = inw(ioaddr + 0x68);
2022 	pci_read_config_word(chip->pci, 0x58, &w);	/* something magical with gpio and bus arb. */
2023 	pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2024 	if (w & 1)
2025 		save_68 |= 0x10;
2026 	outw(0xfffe, ioaddr + 0x64);	/* unmask gpio 0 */
2027 	outw(0x0001, ioaddr + 0x68);	/* gpio write */
2028 	outw(0x0000, ioaddr + 0x60);	/* write 0 to gpio 0 */
2029 	udelay(20);
2030 	outw(0x0001, ioaddr + 0x60);	/* write 1 to gpio 1 */
2031 	msleep(20);
2032 
2033 	outw(save_68 | 0x1, ioaddr + 0x68);	/* now restore .. */
2034 	outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2035 	outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2036 	outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2037 
2038 	/* now the second codec */
2039 	/* disable ac link */
2040 	outw(0x0000, ioaddr + 0x36);
2041 	outw(0xfff7, ioaddr + 0x64);	/* unmask gpio 3 */
2042 	save_68 = inw(ioaddr + 0x68);
2043 	outw(0x0009, ioaddr + 0x68);	/* gpio write 0 & 3 ?? */
2044 	outw(0x0001, ioaddr + 0x60);	/* write 1 to gpio */
2045 	udelay(20);
2046 	outw(0x0009, ioaddr + 0x60);	/* write 9 to gpio */
2047 	msleep(500);
2048 	//outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2049 	outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2050 	outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2051 
2052 #if 0				/* the loop here needs to be much better if we want it.. */
2053 	snd_printk(KERN_INFO "trying software reset\n");
2054 	/* try and do a software reset */
2055 	outb(0x80 | 0x7c, ioaddr + 0x30);
2056 	for (w = 0;; w++) {
2057 		if ((inw(ioaddr + 0x30) & 1) == 0) {
2058 			if (inb(ioaddr + 0x32) != 0)
2059 				break;
2060 
2061 			outb(0x80 | 0x7d, ioaddr + 0x30);
2062 			if (((inw(ioaddr + 0x30) & 1) == 0)
2063 			    && (inb(ioaddr + 0x32) != 0))
2064 				break;
2065 			outb(0x80 | 0x7f, ioaddr + 0x30);
2066 			if (((inw(ioaddr + 0x30) & 1) == 0)
2067 			    && (inb(ioaddr + 0x32) != 0))
2068 				break;
2069 		}
2070 
2071 		if (w > 10000) {
2072 			outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37);	/* do a software reset */
2073 			msleep(500);	/* oh my.. */
2074 			outb(inb(ioaddr + 0x37) & ~0x08,
2075 				ioaddr + 0x37);
2076 			udelay(1);
2077 			outw(0x80, ioaddr + 0x30);
2078 			for (w = 0; w < 10000; w++) {
2079 				if ((inw(ioaddr + 0x30) & 1) == 0)
2080 					break;
2081 			}
2082 		}
2083 	}
2084 #endif
2085 	if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2086 		/* turn on external amp? */
2087 		outw(0xf9ff, ioaddr + 0x64);
2088 		outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2089 		outw(0x0209, ioaddr + 0x60);
2090 	}
2091 
2092 	/* restore.. */
2093 	outw(save_ringbus_a, ioaddr + 0x36);
2094 
2095 	/* Turn on the 978 docking chip.
2096 	   First frob the "master output enable" bit,
2097 	   then set most of the playback volume control registers to max. */
2098 	outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2099 	outb(0xff, ioaddr+0xc3);
2100 	outb(0xff, ioaddr+0xc4);
2101 	outb(0xff, ioaddr+0xc6);
2102 	outb(0xff, ioaddr+0xc8);
2103 	outb(0x3f, ioaddr+0xcf);
2104 	outb(0x3f, ioaddr+0xd0);
2105 }
2106 
2107 static void snd_es1968_reset(struct es1968 *chip)
2108 {
2109 	/* Reset */
2110 	outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2111 	     chip->io_port + ESM_PORT_HOST_IRQ);
2112 	udelay(10);
2113 	outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2114 	udelay(10);
2115 }
2116 
2117 /*
2118  * initialize maestro chip
2119  */
2120 static void snd_es1968_chip_init(struct es1968 *chip)
2121 {
2122 	struct pci_dev *pci = chip->pci;
2123 	int i;
2124 	unsigned long iobase  = chip->io_port;
2125 	u16 w;
2126 	u32 n;
2127 
2128 	/* We used to muck around with pci config space that
2129 	 * we had no business messing with.  We don't know enough
2130 	 * about the machine to know which DMA mode is appropriate,
2131 	 * etc.  We were guessing wrong on some machines and making
2132 	 * them unhappy.  We now trust in the BIOS to do things right,
2133 	 * which almost certainly means a new host of problems will
2134 	 * arise with broken BIOS implementations.  screw 'em.
2135 	 * We're already intolerant of machines that don't assign
2136 	 * IRQs.
2137 	 */
2138 
2139 	/* Config Reg A */
2140 	pci_read_config_word(pci, ESM_CONFIG_A, &w);
2141 
2142 	w &= ~DMA_CLEAR;	/* Clear DMA bits */
2143 	w &= ~(PIC_SNOOP1 | PIC_SNOOP2);	/* Clear Pic Snoop Mode Bits */
2144 	w &= ~SAFEGUARD;	/* Safeguard off */
2145 	w |= POST_WRITE;	/* Posted write */
2146 	w |= PCI_TIMING;	/* PCI timing on */
2147 	/* XXX huh?  claims to be reserved.. */
2148 	w &= ~SWAP_LR;		/* swap left/right
2149 				   seems to only have effect on SB
2150 				   Emulation */
2151 	w &= ~SUBTR_DECODE;	/* Subtractive decode off */
2152 
2153 	pci_write_config_word(pci, ESM_CONFIG_A, w);
2154 
2155 	/* Config Reg B */
2156 
2157 	pci_read_config_word(pci, ESM_CONFIG_B, &w);
2158 
2159 	w &= ~(1 << 15);	/* Turn off internal clock multiplier */
2160 	/* XXX how do we know which to use? */
2161 	w &= ~(1 << 14);	/* External clock */
2162 
2163 	w &= ~SPDIF_CONFB;	/* disable S/PDIF output */
2164 	w |= HWV_CONFB;		/* HWV on */
2165 	w |= DEBOUNCE;		/* Debounce off: easier to push the HW buttons */
2166 	w &= ~GPIO_CONFB;	/* GPIO 4:5 */
2167 	w |= CHI_CONFB;		/* Disconnect from the CHI.  Enabling this made a dell 7500 work. */
2168 	w &= ~IDMA_CONFB;	/* IDMA off (undocumented) */
2169 	w &= ~MIDI_FIX;		/* MIDI fix off (undoc) */
2170 	w &= ~(1 << 1);		/* reserved, always write 0 */
2171 	w &= ~IRQ_TO_ISA;	/* IRQ to ISA off (undoc) */
2172 
2173 	pci_write_config_word(pci, ESM_CONFIG_B, w);
2174 
2175 	/* DDMA off */
2176 
2177 	pci_read_config_word(pci, ESM_DDMA, &w);
2178 	w &= ~(1 << 0);
2179 	pci_write_config_word(pci, ESM_DDMA, w);
2180 
2181 	/*
2182 	 *	Legacy mode
2183 	 */
2184 
2185 	pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2186 
2187 	w |= ESS_DISABLE_AUDIO;	/* Disable Legacy Audio */
2188 	w &= ~ESS_ENABLE_SERIAL_IRQ;	/* Disable SIRQ */
2189 	w &= ~(0x1f);		/* disable mpu irq/io, game port, fm, SB */
2190 
2191 	pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2192 
2193 	/* Set up 978 docking control chip. */
2194 	pci_read_config_word(pci, 0x58, &w);
2195 	w|=1<<2;	/* Enable 978. */
2196 	w|=1<<3;	/* Turn on 978 hardware volume control. */
2197 	w&=~(1<<11);	/* Turn on 978 mixer volume control. */
2198 	pci_write_config_word(pci, 0x58, w);
2199 
2200 	/* Sound Reset */
2201 
2202 	snd_es1968_reset(chip);
2203 
2204 	/*
2205 	 *	Ring Bus Setup
2206 	 */
2207 
2208 	/* setup usual 0x34 stuff.. 0x36 may be chip specific */
2209 	outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2210 	udelay(20);
2211 	outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2212 	udelay(20);
2213 
2214 	/*
2215 	 *	Reset the CODEC
2216 	 */
2217 
2218 	snd_es1968_ac97_reset(chip);
2219 
2220 	/* Ring Bus Control B */
2221 
2222 	n = inl(iobase + ESM_RING_BUS_CONTR_B);
2223 	n &= ~RINGB_EN_SPDIF;	/* SPDIF off */
2224 	//w |= RINGB_EN_2CODEC;	/* enable 2nd codec */
2225 	outl(n, iobase + ESM_RING_BUS_CONTR_B);
2226 
2227 	/* Set hardware volume control registers to midpoints.
2228 	   We can tell which button was pushed based on how they change. */
2229 	outb(0x88, iobase+0x1c);
2230 	outb(0x88, iobase+0x1d);
2231 	outb(0x88, iobase+0x1e);
2232 	outb(0x88, iobase+0x1f);
2233 
2234 	/* it appears some maestros (dell 7500) only work if these are set,
2235 	   regardless of wether we use the assp or not. */
2236 
2237 	outb(0, iobase + ASSP_CONTROL_B);
2238 	outb(3, iobase + ASSP_CONTROL_A);	/* M: Reserved bits... */
2239 	outb(0, iobase + ASSP_CONTROL_C);	/* M: Disable ASSP, ASSP IRQ's and FM Port */
2240 
2241 	/*
2242 	 * set up wavecache
2243 	 */
2244 	for (i = 0; i < 16; i++) {
2245 		/* Write 0 into the buffer area 0x1E0->1EF */
2246 		outw(0x01E0 + i, iobase + WC_INDEX);
2247 		outw(0x0000, iobase + WC_DATA);
2248 
2249 		/* The 1.10 test program seem to write 0 into the buffer area
2250 		 * 0x1D0-0x1DF too.*/
2251 		outw(0x01D0 + i, iobase + WC_INDEX);
2252 		outw(0x0000, iobase + WC_DATA);
2253 	}
2254 	wave_set_register(chip, IDR7_WAVE_ROMRAM,
2255 			  (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2256 	wave_set_register(chip, IDR7_WAVE_ROMRAM,
2257 			  wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2258 	wave_set_register(chip, IDR7_WAVE_ROMRAM,
2259 			  wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2260 	wave_set_register(chip, IDR7_WAVE_ROMRAM,
2261 			  wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2262 
2263 
2264 	maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2265 	/* Now back to the DirectSound stuff */
2266 	/* audio serial configuration.. ? */
2267 	maestro_write(chip, 0x08, 0xB004);
2268 	maestro_write(chip, 0x09, 0x001B);
2269 	maestro_write(chip, 0x0A, 0x8000);
2270 	maestro_write(chip, 0x0B, 0x3F37);
2271 	maestro_write(chip, 0x0C, 0x0098);
2272 
2273 	/* parallel in, has something to do with recording :) */
2274 	maestro_write(chip, 0x0C,
2275 		      (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2276 	/* parallel out */
2277 	maestro_write(chip, 0x0C,
2278 		      (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2279 
2280 	maestro_write(chip, 0x0D, 0x7632);
2281 
2282 	/* Wave cache control on - test off, sg off,
2283 	   enable, enable extra chans 1Mb */
2284 
2285 	w = inw(iobase + WC_CONTROL);
2286 
2287 	w &= ~0xFA00;		/* Seems to be reserved? I don't know */
2288 	w |= 0xA000;		/* reserved... I don't know */
2289 	w &= ~0x0200;		/* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2290 				   Seems to crash the Computer if enabled... */
2291 	w |= 0x0100;		/* Wave Cache Operation Enabled */
2292 	w |= 0x0080;		/* Channels 60/61 as Placback/Record enabled */
2293 	w &= ~0x0060;		/* Clear Wavtable Size */
2294 	w |= 0x0020;		/* Wavetable Size : 1MB */
2295 	/* Bit 4 is reserved */
2296 	w &= ~0x000C;		/* DMA Stuff? I don't understand what the datasheet means */
2297 	/* Bit 1 is reserved */
2298 	w &= ~0x0001;		/* Test Mode off */
2299 
2300 	outw(w, iobase + WC_CONTROL);
2301 
2302 	/* Now clear the APU control ram */
2303 	for (i = 0; i < NR_APUS; i++) {
2304 		for (w = 0; w < NR_APU_REGS; w++)
2305 			apu_set_register(chip, i, w, 0);
2306 
2307 	}
2308 }
2309 
2310 /* Enable IRQ's */
2311 static void snd_es1968_start_irq(struct es1968 *chip)
2312 {
2313 	unsigned short w;
2314 	w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2315 	if (chip->rmidi)
2316 		w |= ESM_HIRQ_MPU401;
2317 	outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2318 }
2319 
2320 #ifdef CONFIG_PM
2321 /*
2322  * PM support
2323  */
2324 static int es1968_suspend(struct pci_dev *pci, pm_message_t state)
2325 {
2326 	struct snd_card *card = pci_get_drvdata(pci);
2327 	struct es1968 *chip = card->private_data;
2328 
2329 	if (! chip->do_pm)
2330 		return 0;
2331 
2332 	chip->in_suspend = 1;
2333 	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2334 	snd_pcm_suspend_all(chip->pcm);
2335 	snd_ac97_suspend(chip->ac97);
2336 	snd_es1968_bob_stop(chip);
2337 
2338 	pci_disable_device(pci);
2339 	pci_save_state(pci);
2340 	pci_set_power_state(pci, pci_choose_state(pci, state));
2341 	return 0;
2342 }
2343 
2344 static int es1968_resume(struct pci_dev *pci)
2345 {
2346 	struct snd_card *card = pci_get_drvdata(pci);
2347 	struct es1968 *chip = card->private_data;
2348 	struct list_head *p;
2349 
2350 	if (! chip->do_pm)
2351 		return 0;
2352 
2353 	/* restore all our config */
2354 	pci_set_power_state(pci, PCI_D0);
2355 	pci_restore_state(pci);
2356 	if (pci_enable_device(pci) < 0) {
2357 		printk(KERN_ERR "es1968: pci_enable_device failed, "
2358 		       "disabling device\n");
2359 		snd_card_disconnect(card);
2360 		return -EIO;
2361 	}
2362 	pci_set_master(pci);
2363 
2364 	snd_es1968_chip_init(chip);
2365 
2366 	/* need to restore the base pointers.. */
2367 	if (chip->dma.addr) {
2368 		/* set PCMBAR */
2369 		wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2370 	}
2371 
2372 	snd_es1968_start_irq(chip);
2373 
2374 	/* restore ac97 state */
2375 	snd_ac97_resume(chip->ac97);
2376 
2377 	list_for_each(p, &chip->substream_list) {
2378 		struct esschan *es = list_entry(p, struct esschan, list);
2379 		switch (es->mode) {
2380 		case ESM_MODE_PLAY:
2381 			snd_es1968_playback_setup(chip, es, es->substream->runtime);
2382 			break;
2383 		case ESM_MODE_CAPTURE:
2384 			snd_es1968_capture_setup(chip, es, es->substream->runtime);
2385 			break;
2386 		}
2387 	}
2388 
2389 	/* start timer again */
2390 	if (chip->bobclient)
2391 		snd_es1968_bob_start(chip);
2392 
2393 	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2394 	chip->in_suspend = 0;
2395 	return 0;
2396 }
2397 #endif /* CONFIG_PM */
2398 
2399 #ifdef SUPPORT_JOYSTICK
2400 #define JOYSTICK_ADDR	0x200
2401 static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev)
2402 {
2403 	struct gameport *gp;
2404 	struct resource *r;
2405 	u16 val;
2406 
2407 	if (!joystick[dev])
2408 		return -ENODEV;
2409 
2410 	r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2411 	if (!r)
2412 		return -EBUSY;
2413 
2414 	chip->gameport = gp = gameport_allocate_port();
2415 	if (!gp) {
2416 		printk(KERN_ERR "es1968: cannot allocate memory for gameport\n");
2417 		release_and_free_resource(r);
2418 		return -ENOMEM;
2419 	}
2420 
2421 	pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2422 	pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2423 
2424 	gameport_set_name(gp, "ES1968 Gameport");
2425 	gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2426 	gameport_set_dev_parent(gp, &chip->pci->dev);
2427 	gp->io = JOYSTICK_ADDR;
2428 	gameport_set_port_data(gp, r);
2429 
2430 	gameport_register_port(gp);
2431 
2432 	return 0;
2433 }
2434 
2435 static void snd_es1968_free_gameport(struct es1968 *chip)
2436 {
2437 	if (chip->gameport) {
2438 		struct resource *r = gameport_get_port_data(chip->gameport);
2439 
2440 		gameport_unregister_port(chip->gameport);
2441 		chip->gameport = NULL;
2442 
2443 		release_and_free_resource(r);
2444 	}
2445 }
2446 #else
2447 static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
2448 static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
2449 #endif
2450 
2451 static int snd_es1968_free(struct es1968 *chip)
2452 {
2453 	if (chip->io_port) {
2454 		synchronize_irq(chip->irq);
2455 		outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2456 		outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2457 	}
2458 
2459 	if (chip->irq >= 0)
2460 		free_irq(chip->irq, chip);
2461 	snd_es1968_free_gameport(chip);
2462 	chip->master_switch = NULL;
2463 	chip->master_volume = NULL;
2464 	pci_release_regions(chip->pci);
2465 	pci_disable_device(chip->pci);
2466 	kfree(chip);
2467 	return 0;
2468 }
2469 
2470 static int snd_es1968_dev_free(struct snd_device *device)
2471 {
2472 	struct es1968 *chip = device->device_data;
2473 	return snd_es1968_free(chip);
2474 }
2475 
2476 struct ess_device_list {
2477 	unsigned short type;	/* chip type */
2478 	unsigned short vendor;	/* subsystem vendor id */
2479 };
2480 
2481 static struct ess_device_list pm_whitelist[] __devinitdata = {
2482 	{ TYPE_MAESTRO2E, 0x0e11 },	/* Compaq Armada */
2483 	{ TYPE_MAESTRO2E, 0x1028 },
2484 	{ TYPE_MAESTRO2E, 0x103c },
2485 	{ TYPE_MAESTRO2E, 0x1179 },
2486 	{ TYPE_MAESTRO2E, 0x14c0 },	/* HP omnibook 4150 */
2487 	{ TYPE_MAESTRO2E, 0x1558 },
2488 };
2489 
2490 static struct ess_device_list mpu_blacklist[] __devinitdata = {
2491 	{ TYPE_MAESTRO2, 0x125d },
2492 };
2493 
2494 static int __devinit snd_es1968_create(struct snd_card *card,
2495 				       struct pci_dev *pci,
2496 				       int total_bufsize,
2497 				       int play_streams,
2498 				       int capt_streams,
2499 				       int chip_type,
2500 				       int do_pm,
2501 				       struct es1968 **chip_ret)
2502 {
2503 	static struct snd_device_ops ops = {
2504 		.dev_free =	snd_es1968_dev_free,
2505 	};
2506 	struct es1968 *chip;
2507 	int i, err;
2508 
2509 	*chip_ret = NULL;
2510 
2511 	/* enable PCI device */
2512 	if ((err = pci_enable_device(pci)) < 0)
2513 		return err;
2514 	/* check, if we can restrict PCI DMA transfers to 28 bits */
2515 	if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2516 	    pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2517 		snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2518 		pci_disable_device(pci);
2519 		return -ENXIO;
2520 	}
2521 
2522 	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2523 	if (! chip) {
2524 		pci_disable_device(pci);
2525 		return -ENOMEM;
2526 	}
2527 
2528 	/* Set Vars */
2529 	chip->type = chip_type;
2530 	spin_lock_init(&chip->reg_lock);
2531 	spin_lock_init(&chip->substream_lock);
2532 	INIT_LIST_HEAD(&chip->buf_list);
2533 	INIT_LIST_HEAD(&chip->substream_list);
2534 	spin_lock_init(&chip->ac97_lock);
2535 	mutex_init(&chip->memory_mutex);
2536 	tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip);
2537 	chip->card = card;
2538 	chip->pci = pci;
2539 	chip->irq = -1;
2540 	chip->total_bufsize = total_bufsize;	/* in bytes */
2541 	chip->playback_streams = play_streams;
2542 	chip->capture_streams = capt_streams;
2543 
2544 	if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2545 		kfree(chip);
2546 		pci_disable_device(pci);
2547 		return err;
2548 	}
2549 	chip->io_port = pci_resource_start(pci, 0);
2550 	if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED,
2551 			"ESS Maestro", chip)) {
2552 		snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2553 		snd_es1968_free(chip);
2554 		return -EBUSY;
2555 	}
2556 	chip->irq = pci->irq;
2557 
2558 	/* Clear Maestro_map */
2559 	for (i = 0; i < 32; i++)
2560 		chip->maestro_map[i] = 0;
2561 
2562 	/* Clear Apu Map */
2563 	for (i = 0; i < NR_APUS; i++)
2564 		chip->apu[i] = ESM_APU_FREE;
2565 
2566 	/* just to be sure */
2567 	pci_set_master(pci);
2568 
2569 	if (do_pm > 1) {
2570 		/* disable power-management if not on the whitelist */
2571 		unsigned short vend;
2572 		pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2573 		for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
2574 			if (chip->type == pm_whitelist[i].type &&
2575 			    vend == pm_whitelist[i].vendor) {
2576 				do_pm = 1;
2577 				break;
2578 			}
2579 		}
2580 		if (do_pm > 1) {
2581 			/* not matched; disabling pm */
2582 			printk(KERN_INFO "es1968: not attempting power management.\n");
2583 			do_pm = 0;
2584 		}
2585 	}
2586 	chip->do_pm = do_pm;
2587 
2588 	snd_es1968_chip_init(chip);
2589 
2590 	if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2591 		snd_es1968_free(chip);
2592 		return err;
2593 	}
2594 
2595 	snd_card_set_dev(card, &pci->dev);
2596 
2597 	*chip_ret = chip;
2598 
2599 	return 0;
2600 }
2601 
2602 
2603 /*
2604  */
2605 static int __devinit snd_es1968_probe(struct pci_dev *pci,
2606 				      const struct pci_device_id *pci_id)
2607 {
2608 	static int dev;
2609 	struct snd_card *card;
2610 	struct es1968 *chip;
2611 	unsigned int i;
2612 	int err;
2613 
2614 	if (dev >= SNDRV_CARDS)
2615 		return -ENODEV;
2616 	if (!enable[dev]) {
2617 		dev++;
2618 		return -ENOENT;
2619 	}
2620 
2621 	card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2622 	if (!card)
2623 		return -ENOMEM;
2624 
2625 	if (total_bufsize[dev] < 128)
2626 		total_bufsize[dev] = 128;
2627 	if (total_bufsize[dev] > 4096)
2628 		total_bufsize[dev] = 4096;
2629 	if ((err = snd_es1968_create(card, pci,
2630 				     total_bufsize[dev] * 1024, /* in bytes */
2631 				     pcm_substreams_p[dev],
2632 				     pcm_substreams_c[dev],
2633 				     pci_id->driver_data,
2634 				     use_pm[dev],
2635 				     &chip)) < 0) {
2636 		snd_card_free(card);
2637 		return err;
2638 	}
2639 	card->private_data = chip;
2640 
2641 	switch (chip->type) {
2642 	case TYPE_MAESTRO2E:
2643 		strcpy(card->driver, "ES1978");
2644 		strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2645 		break;
2646 	case TYPE_MAESTRO2:
2647 		strcpy(card->driver, "ES1968");
2648 		strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2649 		break;
2650 	case TYPE_MAESTRO:
2651 		strcpy(card->driver, "ESM1");
2652 		strcpy(card->shortname, "ESS Maestro 1");
2653 		break;
2654 	}
2655 
2656 	if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2657 		snd_card_free(card);
2658 		return err;
2659 	}
2660 
2661 	if ((err = snd_es1968_mixer(chip)) < 0) {
2662 		snd_card_free(card);
2663 		return err;
2664 	}
2665 
2666 	if (enable_mpu[dev] == 2) {
2667 		/* check the black list */
2668 		unsigned short vend;
2669 		pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2670 		for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
2671 			if (chip->type == mpu_blacklist[i].type &&
2672 			    vend == mpu_blacklist[i].vendor) {
2673 				enable_mpu[dev] = 0;
2674 				break;
2675 			}
2676 		}
2677 	}
2678 	if (enable_mpu[dev]) {
2679 		if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2680 					       chip->io_port + ESM_MPU401_PORT,
2681 					       MPU401_INFO_INTEGRATED,
2682 					       chip->irq, 0, &chip->rmidi)) < 0) {
2683 			printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n");
2684 		}
2685 	}
2686 
2687 	snd_es1968_create_gameport(chip, dev);
2688 
2689 	snd_es1968_start_irq(chip);
2690 
2691 	chip->clock = clock[dev];
2692 	if (! chip->clock)
2693 		es1968_measure_clock(chip);
2694 
2695 	sprintf(card->longname, "%s at 0x%lx, irq %i",
2696 		card->shortname, chip->io_port, chip->irq);
2697 
2698 	if ((err = snd_card_register(card)) < 0) {
2699 		snd_card_free(card);
2700 		return err;
2701 	}
2702 	pci_set_drvdata(pci, card);
2703 	dev++;
2704 	return 0;
2705 }
2706 
2707 static void __devexit snd_es1968_remove(struct pci_dev *pci)
2708 {
2709 	snd_card_free(pci_get_drvdata(pci));
2710 	pci_set_drvdata(pci, NULL);
2711 }
2712 
2713 static struct pci_driver driver = {
2714 	.name = "ES1968 (ESS Maestro)",
2715 	.id_table = snd_es1968_ids,
2716 	.probe = snd_es1968_probe,
2717 	.remove = __devexit_p(snd_es1968_remove),
2718 #ifdef CONFIG_PM
2719 	.suspend = es1968_suspend,
2720 	.resume = es1968_resume,
2721 #endif
2722 };
2723 
2724 static int __init alsa_card_es1968_init(void)
2725 {
2726 	return pci_register_driver(&driver);
2727 }
2728 
2729 static void __exit alsa_card_es1968_exit(void)
2730 {
2731 	pci_unregister_driver(&driver);
2732 }
2733 
2734 module_init(alsa_card_es1968_init)
2735 module_exit(alsa_card_es1968_exit)
2736