xref: /openbmc/linux/sound/pci/ens1370.c (revision d5cb9783536a41df9f9cba5b0a1d78047ed787f7)
1 /*
2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4  *		     Thomas Sailer <sailer@ife.ee.ethz.ch>
5  *
6  *   This program is free software; you can redistribute it and/or modify
7  *   it under the terms of the GNU General Public License as published by
8  *   the Free Software Foundation; either version 2 of the License, or
9  *   (at your option) any later version.
10  *
11  *   This program is distributed in the hope that it will be useful,
12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  *   GNU General Public License for more details.
15  *
16  *   You should have received a copy of the GNU General Public License
17  *   along with this program; if not, write to the Free Software
18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
19  *
20  */
21 
22 #include <sound/driver.h>
23 #include <asm/io.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/gameport.h>
30 #include <linux/moduleparam.h>
31 #include <sound/core.h>
32 #include <sound/control.h>
33 #include <sound/pcm.h>
34 #include <sound/rawmidi.h>
35 #ifdef CHIP1371
36 #include <sound/ac97_codec.h>
37 #else
38 #include <sound/ak4531_codec.h>
39 #endif
40 #include <sound/initval.h>
41 #include <sound/asoundef.h>
42 
43 #ifndef CHIP1371
44 #undef CHIP1370
45 #define CHIP1370
46 #endif
47 
48 #ifdef CHIP1370
49 #define DRIVER_NAME "ENS1370"
50 #else
51 #define DRIVER_NAME "ENS1371"
52 #endif
53 
54 
55 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
56 MODULE_LICENSE("GPL");
57 #ifdef CHIP1370
58 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
59 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
60 	        "{Creative Labs,SB PCI64/128 (ES1370)}}");
61 #endif
62 #ifdef CHIP1371
63 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
64 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
65 		"{Ensoniq,AudioPCI ES1373},"
66 		"{Creative Labs,Ectiva EV1938},"
67 		"{Creative Labs,SB PCI64/128 (ES1371/73)},"
68 		"{Creative Labs,Vibra PCI128},"
69 		"{Ectiva,EV1938}}");
70 #endif
71 
72 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
73 #define SUPPORT_JOYSTICK
74 #endif
75 
76 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
77 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
78 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable switches */
79 #ifdef SUPPORT_JOYSTICK
80 #ifdef CHIP1371
81 static int joystick_port[SNDRV_CARDS];
82 #else
83 static int joystick[SNDRV_CARDS];
84 #endif
85 #endif
86 
87 module_param_array(index, int, NULL, 0444);
88 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
89 module_param_array(id, charp, NULL, 0444);
90 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
91 module_param_array(enable, bool, NULL, 0444);
92 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
93 #ifdef SUPPORT_JOYSTICK
94 #ifdef CHIP1371
95 module_param_array(joystick_port, int, NULL, 0444);
96 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
97 #else
98 module_param_array(joystick, bool, NULL, 0444);
99 MODULE_PARM_DESC(joystick, "Enable joystick.");
100 #endif
101 #endif /* SUPPORT_JOYSTICK */
102 
103 /* ES1371 chip ID */
104 /* This is a little confusing because all ES1371 compatible chips have the
105    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
106    This is only significant if you want to enable features on the later parts.
107    Yes, I know it's stupid and why didn't we use the sub IDs?
108 */
109 #define ES1371REV_ES1373_A  0x04
110 #define ES1371REV_ES1373_B  0x06
111 #define ES1371REV_CT5880_A  0x07
112 #define CT5880REV_CT5880_C  0x02
113 #define CT5880REV_CT5880_D  0x03	/* ??? -jk */
114 #define CT5880REV_CT5880_E  0x04	/* mw */
115 #define ES1371REV_ES1371_B  0x09
116 #define EV1938REV_EV1938_A  0x00
117 #define ES1371REV_ES1373_8  0x08
118 
119 /*
120  * Direct registers
121  */
122 
123 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
124 
125 #define ES_REG_CONTROL	0x00	/* R/W: Interrupt/Chip select control register */
126 #define   ES_1370_ADC_STOP	(1<<31)		/* disable capture buffer transfers */
127 #define   ES_1370_XCTL1 	(1<<30)		/* general purpose output bit */
128 #define   ES_1373_BYPASS_P1	(1<<31)		/* bypass SRC for PB1 */
129 #define   ES_1373_BYPASS_P2	(1<<30)		/* bypass SRC for PB2 */
130 #define   ES_1373_BYPASS_R	(1<<29)		/* bypass SRC for REC */
131 #define   ES_1373_TEST_BIT	(1<<28)		/* should be set to 0 for normal operation */
132 #define   ES_1373_RECEN_B	(1<<27)		/* mix record with playback for I2S/SPDIF out */
133 #define   ES_1373_SPDIF_THRU	(1<<26)		/* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
134 #define   ES_1371_JOY_ASEL(o)	(((o)&0x03)<<24)/* joystick port mapping */
135 #define   ES_1371_JOY_ASELM	(0x03<<24)	/* mask for above */
136 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
137 #define   ES_1371_GPIO_IN(i)	(((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
138 #define   ES_1370_PCLKDIVO(o)	(((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
139 #define   ES_1370_PCLKDIVM	((0x1fff)<<16)	/* mask for above */
140 #define   ES_1370_PCLKDIVI(i)	(((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
141 #define   ES_1371_GPIO_OUT(o)	(((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
142 #define   ES_1371_GPIO_OUTM     (0x0f<<16)	/* mask for above */
143 #define   ES_MSFMTSEL		(1<<15)		/* MPEG serial data format; 0 = SONY, 1 = I2S */
144 #define   ES_1370_M_SBB		(1<<14)		/* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
145 #define   ES_1371_SYNC_RES	(1<<14)		/* Warm AC97 reset */
146 #define   ES_1370_WTSRSEL(o)	(((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
147 #define   ES_1370_WTSRSELM	(0x03<<12)	/* mask for above */
148 #define   ES_1371_ADC_STOP	(1<<13)		/* disable CCB transfer capture information */
149 #define   ES_1371_PWR_INTRM	(1<<12)		/* power level change interrupts enable */
150 #define   ES_1370_DAC_SYNC	(1<<11)		/* DAC's are synchronous */
151 #define   ES_1371_M_CB		(1<<11)		/* capture clock source; 0 = AC'97 ADC; 1 = I2S */
152 #define   ES_CCB_INTRM		(1<<10)		/* CCB voice interrupts enable */
153 #define   ES_1370_M_CB		(1<<9)		/* capture clock source; 0 = ADC; 1 = MPEG */
154 #define   ES_1370_XCTL0		(1<<8)		/* generap purpose output bit */
155 #define   ES_1371_PDLEV(o)	(((o)&0x03)<<8)	/* current power down level */
156 #define   ES_1371_PDLEVM	(0x03<<8)	/* mask for above */
157 #define   ES_BREQ		(1<<7)		/* memory bus request enable */
158 #define   ES_DAC1_EN		(1<<6)		/* DAC1 playback channel enable */
159 #define   ES_DAC2_EN		(1<<5)		/* DAC2 playback channel enable */
160 #define   ES_ADC_EN		(1<<4)		/* ADC capture channel enable */
161 #define   ES_UART_EN		(1<<3)		/* UART enable */
162 #define   ES_JYSTK_EN		(1<<2)		/* Joystick module enable */
163 #define   ES_1370_CDC_EN	(1<<1)		/* Codec interface enable */
164 #define   ES_1371_XTALCKDIS	(1<<1)		/* Xtal clock disable */
165 #define   ES_1370_SERR_DISABLE	(1<<0)		/* PCI serr signal disable */
166 #define   ES_1371_PCICLKDIS     (1<<0)		/* PCI clock disable */
167 #define ES_REG_STATUS	0x04	/* R/O: Interrupt/Chip select status register */
168 #define   ES_INTR               (1<<31)		/* Interrupt is pending */
169 #define   ES_1371_ST_AC97_RST	(1<<29)		/* CT5880 AC'97 Reset bit */
170 #define   ES_1373_REAR_BIT27	(1<<27)		/* rear bits: 000 - front, 010 - mirror, 101 - separate */
171 #define   ES_1373_REAR_BIT26	(1<<26)
172 #define   ES_1373_REAR_BIT24	(1<<24)
173 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
174 #define   ES_1373_SPDIF_EN	(1<<18)		/* SPDIF enable */
175 #define   ES_1373_SPDIF_TEST	(1<<17)		/* SPDIF test */
176 #define   ES_1371_TEST          (1<<16)		/* test ASIC */
177 #define   ES_1373_GPIO_INT(i)	(((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
178 #define   ES_1370_CSTAT		(1<<10)		/* CODEC is busy or register write in progress */
179 #define   ES_1370_CBUSY         (1<<9)		/* CODEC is busy */
180 #define   ES_1370_CWRIP		(1<<8)		/* CODEC register write in progress */
181 #define   ES_1371_SYNC_ERR	(1<<8)		/* CODEC synchronization error occurred */
182 #define   ES_1371_VC(i)         (((i)>>6)&0x03)	/* voice code from CCB module */
183 #define   ES_1370_VC(i)		(((i)>>5)&0x03)	/* voice code from CCB module */
184 #define   ES_1371_MPWR          (1<<5)		/* power level interrupt pending */
185 #define   ES_MCCB		(1<<4)		/* CCB interrupt pending */
186 #define   ES_UART		(1<<3)		/* UART interrupt pending */
187 #define   ES_DAC1		(1<<2)		/* DAC1 channel interrupt pending */
188 #define   ES_DAC2		(1<<1)		/* DAC2 channel interrupt pending */
189 #define   ES_ADC		(1<<0)		/* ADC channel interrupt pending */
190 #define ES_REG_UART_DATA 0x08	/* R/W: UART data register */
191 #define ES_REG_UART_STATUS 0x09	/* R/O: UART status register */
192 #define   ES_RXINT		(1<<7)		/* RX interrupt occurred */
193 #define   ES_TXINT		(1<<2)		/* TX interrupt occurred */
194 #define   ES_TXRDY		(1<<1)		/* transmitter ready */
195 #define   ES_RXRDY		(1<<0)		/* receiver ready */
196 #define ES_REG_UART_CONTROL 0x09	/* W/O: UART control register */
197 #define   ES_RXINTEN		(1<<7)		/* RX interrupt enable */
198 #define   ES_TXINTENO(o)	(((o)&0x03)<<5)	/* TX interrupt enable */
199 #define   ES_TXINTENM		(0x03<<5)	/* mask for above */
200 #define   ES_TXINTENI(i)	(((i)>>5)&0x03)
201 #define   ES_CNTRL(o)		(((o)&0x03)<<0)	/* control */
202 #define   ES_CNTRLM		(0x03<<0)	/* mask for above */
203 #define ES_REG_UART_RES	0x0a	/* R/W: UART reserver register */
204 #define   ES_TEST_MODE		(1<<0)		/* test mode enabled */
205 #define ES_REG_MEM_PAGE	0x0c	/* R/W: Memory page register */
206 #define   ES_MEM_PAGEO(o)	(((o)&0x0f)<<0)	/* memory page select - out */
207 #define   ES_MEM_PAGEM		(0x0f<<0)	/* mask for above */
208 #define   ES_MEM_PAGEI(i)	(((i)>>0)&0x0f) /* memory page select - in */
209 #define ES_REG_1370_CODEC 0x10	/* W/O: Codec write register address */
210 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
211 #define ES_REG_1371_CODEC 0x14	/* W/R: Codec Read/Write register address */
212 #define   ES_1371_CODEC_RDY	   (1<<31)	/* codec ready */
213 #define   ES_1371_CODEC_WIP	   (1<<30)	/* codec register access in progress */
214 #define   ES_1371_CODEC_PIRD	   (1<<23)	/* codec read/write select register */
215 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
216 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
217 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
218 
219 #define ES_REG_1371_SMPRATE 0x10	/* W/R: Codec rate converter interface register */
220 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
221 #define   ES_1371_SRC_RAM_ADDRM	   (0x7f<<25)	/* mask for above */
222 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
223 #define   ES_1371_SRC_RAM_WE	   (1<<24)	/* R/W: read/write control for sample rate converter */
224 #define   ES_1371_SRC_RAM_BUSY     (1<<23)	/* R/O: sample rate memory is busy */
225 #define   ES_1371_SRC_DISABLE      (1<<22)	/* sample rate converter disable */
226 #define   ES_1371_DIS_P1	   (1<<21)	/* playback channel 1 accumulator update disable */
227 #define   ES_1371_DIS_P2	   (1<<20)	/* playback channel 1 accumulator update disable */
228 #define   ES_1371_DIS_R1	   (1<<19)	/* capture channel accumulator update disable */
229 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
230 #define   ES_1371_SRC_RAM_DATAM	   (0xffff<<0)	/* mask for above */
231 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
232 
233 #define ES_REG_1371_LEGACY 0x18	/* W/R: Legacy control/status register */
234 #define   ES_1371_JFAST		(1<<31)		/* fast joystick timing */
235 #define   ES_1371_HIB		(1<<30)		/* host interrupt blocking enable */
236 #define   ES_1371_VSB		(1<<29)		/* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
237 #define   ES_1371_VMPUO(o)	(((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
238 #define   ES_1371_VMPUM		(0x03<<27)	/* mask for above */
239 #define   ES_1371_VMPUI(i)	(((i)>>27)&0x03)/* base register address */
240 #define   ES_1371_VCDCO(o)	(((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
241 #define   ES_1371_VCDCM		(0x03<<25)	/* mask for above */
242 #define   ES_1371_VCDCI(i)	(((i)>>25)&0x03)/* CODEC address */
243 #define   ES_1371_FIRQ		(1<<24)		/* force an interrupt */
244 #define   ES_1371_SDMACAP	(1<<23)		/* enable event capture for slave DMA controller */
245 #define   ES_1371_SPICAP	(1<<22)		/* enable event capture for slave IRQ controller */
246 #define   ES_1371_MDMACAP	(1<<21)		/* enable event capture for master DMA controller */
247 #define   ES_1371_MPICAP	(1<<20)		/* enable event capture for master IRQ controller */
248 #define   ES_1371_ADCAP		(1<<19)		/* enable event capture for ADLIB register; 0x388xH */
249 #define   ES_1371_SVCAP		(1<<18)		/* enable event capture for SB registers */
250 #define   ES_1371_CDCCAP	(1<<17)		/* enable event capture for CODEC registers */
251 #define   ES_1371_BACAP		(1<<16)		/* enable event capture for SoundScape base address */
252 #define   ES_1371_EXI(i)	(((i)>>8)&0x07)	/* event number */
253 #define   ES_1371_AI(i)		(((i)>>3)&0x1f)	/* event significant I/O address */
254 #define   ES_1371_WR		(1<<2)	/* event capture; 0 = read; 1 = write */
255 #define   ES_1371_LEGINT	(1<<0)	/* interrupt for legacy events; 0 = interrupt did occur */
256 
257 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
258 
259 #define ES_REG_SERIAL	0x20	/* R/W: Serial interface control register */
260 #define   ES_1371_DAC_TEST	(1<<22)		/* DAC test mode enable */
261 #define   ES_P2_END_INCO(o)	(((o)&0x07)<<19)/* binary offset value to increment / loop end */
262 #define   ES_P2_END_INCM	(0x07<<19)	/* mask for above */
263 #define   ES_P2_END_INCI(i)	(((i)>>16)&0x07)/* binary offset value to increment / loop end */
264 #define   ES_P2_ST_INCO(o)	(((o)&0x07)<<16)/* binary offset value to increment / start */
265 #define   ES_P2_ST_INCM		(0x07<<16)	/* mask for above */
266 #define   ES_P2_ST_INCI(i)	(((i)<<16)&0x07)/* binary offset value to increment / start */
267 #define   ES_R1_LOOP_SEL	(1<<15)		/* ADC; 0 - loop mode; 1 = stop mode */
268 #define   ES_P2_LOOP_SEL	(1<<14)		/* DAC2; 0 - loop mode; 1 = stop mode */
269 #define   ES_P1_LOOP_SEL	(1<<13)		/* DAC1; 0 - loop mode; 1 = stop mode */
270 #define   ES_P2_PAUSE		(1<<12)		/* DAC2; 0 - play mode; 1 = pause mode */
271 #define   ES_P1_PAUSE		(1<<11)		/* DAC1; 0 - play mode; 1 = pause mode */
272 #define   ES_R1_INT_EN		(1<<10)		/* ADC interrupt enable */
273 #define   ES_P2_INT_EN		(1<<9)		/* DAC2 interrupt enable */
274 #define   ES_P1_INT_EN		(1<<8)		/* DAC1 interrupt enable */
275 #define   ES_P1_SCT_RLD		(1<<7)		/* force sample counter reload for DAC1 */
276 #define   ES_P2_DAC_SEN		(1<<6)		/* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
277 #define   ES_R1_MODEO(o)	(((o)&0x03)<<4)	/* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
278 #define   ES_R1_MODEM		(0x03<<4)	/* mask for above */
279 #define   ES_R1_MODEI(i)	(((i)>>4)&0x03)
280 #define   ES_P2_MODEO(o)	(((o)&0x03)<<2)	/* DAC2 mode; -- '' -- */
281 #define   ES_P2_MODEM		(0x03<<2)	/* mask for above */
282 #define   ES_P2_MODEI(i)	(((i)>>2)&0x03)
283 #define   ES_P1_MODEO(o)	(((o)&0x03)<<0)	/* DAC1 mode; -- '' -- */
284 #define   ES_P1_MODEM		(0x03<<0)	/* mask for above */
285 #define   ES_P1_MODEI(i)	(((i)>>0)&0x03)
286 
287 #define ES_REG_DAC1_COUNT 0x24	/* R/W: DAC1 sample count register */
288 #define ES_REG_DAC2_COUNT 0x28	/* R/W: DAC2 sample count register */
289 #define ES_REG_ADC_COUNT  0x2c	/* R/W: ADC sample count register */
290 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
291 #define   ES_REG_COUNTO(o)	(((o)&0xffff)<<0)
292 #define   ES_REG_COUNTM		(0xffff<<0)
293 #define   ES_REG_COUNTI(i)	(((i)>>0)&0xffff)
294 
295 #define ES_REG_DAC1_FRAME 0x30	/* R/W: PAGE 0x0c; DAC1 frame address */
296 #define ES_REG_DAC1_SIZE  0x34	/* R/W: PAGE 0x0c; DAC1 frame size */
297 #define ES_REG_DAC2_FRAME 0x38	/* R/W: PAGE 0x0c; DAC2 frame address */
298 #define ES_REG_DAC2_SIZE  0x3c	/* R/W: PAGE 0x0c; DAC2 frame size */
299 #define ES_REG_ADC_FRAME  0x30	/* R/W: PAGE 0x0d; ADC frame address */
300 #define ES_REG_ADC_SIZE	  0x34	/* R/W: PAGE 0x0d; ADC frame size */
301 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
302 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
303 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
304 #define   ES_REG_FSIZEO(o)	 (((o)&0xffff)<<0)
305 #define   ES_REG_FSIZEM		 (0xffff<<0)
306 #define   ES_REG_FSIZEI(i)	 (((i)>>0)&0xffff)
307 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
308 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
309 
310 #define ES_REG_UART_FIFO  0x30	/* R/W: PAGE 0x0e; UART FIFO register */
311 #define   ES_REG_UF_VALID	 (1<<8)
312 #define   ES_REG_UF_BYTEO(o)	 (((o)&0xff)<<0)
313 #define   ES_REG_UF_BYTEM	 (0xff<<0)
314 #define   ES_REG_UF_BYTEI(i)	 (((i)>>0)&0xff)
315 
316 
317 /*
318  *  Pages
319  */
320 
321 #define ES_PAGE_DAC	0x0c
322 #define ES_PAGE_ADC	0x0d
323 #define ES_PAGE_UART	0x0e
324 #define ES_PAGE_UART1	0x0f
325 
326 /*
327  *  Sample rate converter addresses
328  */
329 
330 #define ES_SMPREG_DAC1		0x70
331 #define ES_SMPREG_DAC2		0x74
332 #define ES_SMPREG_ADC		0x78
333 #define ES_SMPREG_VOL_ADC	0x6c
334 #define ES_SMPREG_VOL_DAC1	0x7c
335 #define ES_SMPREG_VOL_DAC2	0x7e
336 #define ES_SMPREG_TRUNC_N	0x00
337 #define ES_SMPREG_INT_REGS	0x01
338 #define ES_SMPREG_ACCUM_FRAC	0x02
339 #define ES_SMPREG_VFREQ_FRAC	0x03
340 
341 /*
342  *  Some contants
343  */
344 
345 #define ES_1370_SRCLOCK	   1411200
346 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
347 
348 /*
349  *  Open modes
350  */
351 
352 #define ES_MODE_PLAY1	0x0001
353 #define ES_MODE_PLAY2	0x0002
354 #define ES_MODE_CAPTURE	0x0004
355 
356 #define ES_MODE_OUTPUT	0x0001	/* for MIDI */
357 #define ES_MODE_INPUT	0x0002	/* for MIDI */
358 
359 /*
360 
361  */
362 
363 typedef struct _snd_ensoniq ensoniq_t;
364 
365 struct _snd_ensoniq {
366 	spinlock_t reg_lock;
367 	struct semaphore src_mutex;
368 
369 	int irq;
370 
371 	unsigned long playback1size;
372 	unsigned long playback2size;
373 	unsigned long capture3size;
374 
375 	unsigned long port;
376 	unsigned int mode;
377 	unsigned int uartm;	/* UART mode */
378 
379 	unsigned int ctrl;	/* control register */
380 	unsigned int sctrl;	/* serial control register */
381 	unsigned int cssr;	/* control status register */
382 	unsigned int uartc;	/* uart control register */
383 	unsigned int rev;	/* chip revision */
384 
385 	union {
386 #ifdef CHIP1371
387 		struct {
388 			ac97_t *ac97;
389 		} es1371;
390 #else
391 		struct {
392 			int pclkdiv_lock;
393 			ak4531_t *ak4531;
394 		} es1370;
395 #endif
396 	} u;
397 
398 	struct pci_dev *pci;
399 	unsigned short subsystem_vendor_id;
400 	unsigned short subsystem_device_id;
401 	snd_card_t *card;
402 	snd_pcm_t *pcm1;	/* DAC1/ADC PCM */
403 	snd_pcm_t *pcm2;	/* DAC2 PCM */
404 	snd_pcm_substream_t *playback1_substream;
405 	snd_pcm_substream_t *playback2_substream;
406 	snd_pcm_substream_t *capture_substream;
407 	unsigned int p1_dma_size;
408 	unsigned int p2_dma_size;
409 	unsigned int c_dma_size;
410 	unsigned int p1_period_size;
411 	unsigned int p2_period_size;
412 	unsigned int c_period_size;
413 	snd_rawmidi_t *rmidi;
414 	snd_rawmidi_substream_t *midi_input;
415 	snd_rawmidi_substream_t *midi_output;
416 
417 	unsigned int spdif;
418 	unsigned int spdif_default;
419 	unsigned int spdif_stream;
420 
421 #ifdef CHIP1370
422 	struct snd_dma_buffer dma_bug;
423 #endif
424 
425 #ifdef SUPPORT_JOYSTICK
426 	struct gameport *gameport;
427 #endif
428 };
429 
430 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
431 
432 static struct pci_device_id snd_audiopci_ids[] = {
433 #ifdef CHIP1370
434 	{ 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },	/* ES1370 */
435 #endif
436 #ifdef CHIP1371
437 	{ 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },	/* ES1371 */
438 	{ 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },	/* ES1373 - CT5880 */
439 	{ 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },	/* Ectiva EV1938 */
440 #endif
441 	{ 0, }
442 };
443 
444 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
445 
446 /*
447  *  constants
448  */
449 
450 #define POLL_COUNT	0xa000
451 
452 #ifdef CHIP1370
453 static unsigned int snd_es1370_fixed_rates[] =
454 	{5512, 11025, 22050, 44100};
455 static snd_pcm_hw_constraint_list_t snd_es1370_hw_constraints_rates = {
456 	.count = 4,
457 	.list = snd_es1370_fixed_rates,
458 	.mask = 0,
459 };
460 static ratnum_t es1370_clock = {
461 	.num = ES_1370_SRCLOCK,
462 	.den_min = 29,
463 	.den_max = 353,
464 	.den_step = 1,
465 };
466 static snd_pcm_hw_constraint_ratnums_t snd_es1370_hw_constraints_clock = {
467 	.nrats = 1,
468 	.rats = &es1370_clock,
469 };
470 #else
471 static ratden_t es1371_dac_clock = {
472 	.num_min = 3000 * (1 << 15),
473 	.num_max = 48000 * (1 << 15),
474 	.num_step = 3000,
475 	.den = 1 << 15,
476 };
477 static snd_pcm_hw_constraint_ratdens_t snd_es1371_hw_constraints_dac_clock = {
478 	.nrats = 1,
479 	.rats = &es1371_dac_clock,
480 };
481 static ratnum_t es1371_adc_clock = {
482 	.num = 48000 << 15,
483 	.den_min = 32768,
484 	.den_max = 393216,
485 	.den_step = 1,
486 };
487 static snd_pcm_hw_constraint_ratnums_t snd_es1371_hw_constraints_adc_clock = {
488 	.nrats = 1,
489 	.rats = &es1371_adc_clock,
490 };
491 #endif
492 static const unsigned int snd_ensoniq_sample_shift[] =
493 	{0, 1, 1, 2};
494 
495 /*
496  *  common I/O routines
497  */
498 
499 #ifdef CHIP1371
500 
501 static unsigned int snd_es1371_wait_src_ready(ensoniq_t * ensoniq)
502 {
503 	unsigned int t, r = 0;
504 
505 	for (t = 0; t < POLL_COUNT; t++) {
506 		r = inl(ES_REG(ensoniq, 1371_SMPRATE));
507 		if ((r & ES_1371_SRC_RAM_BUSY) == 0)
508 			return r;
509 		cond_resched();
510 	}
511 	snd_printk("wait source ready timeout 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_SMPRATE), r);
512 	return 0;
513 }
514 
515 static unsigned int snd_es1371_src_read(ensoniq_t * ensoniq, unsigned short reg)
516 {
517 	unsigned int temp, i, orig, r;
518 
519 	/* wait for ready */
520 	temp = orig = snd_es1371_wait_src_ready(ensoniq);
521 
522 	/* expose the SRC state bits */
523 	r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
524 		    ES_1371_DIS_P2 | ES_1371_DIS_R1);
525 	r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
526 	outl(r, ES_REG(ensoniq, 1371_SMPRATE));
527 
528 	/* now, wait for busy and the correct time to read */
529 	temp = snd_es1371_wait_src_ready(ensoniq);
530 
531 	if ((temp & 0x00870000) != 0x00010000) {
532 		/* wait for the right state */
533 		for (i = 0; i < POLL_COUNT; i++) {
534 			temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
535 			if ((temp & 0x00870000) == 0x00010000)
536 				break;
537 		}
538 	}
539 
540 	/* hide the state bits */
541 	r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
542 		   ES_1371_DIS_P2 | ES_1371_DIS_R1);
543 	r |= ES_1371_SRC_RAM_ADDRO(reg);
544 	outl(r, ES_REG(ensoniq, 1371_SMPRATE));
545 
546 	return temp;
547 }
548 
549 static void snd_es1371_src_write(ensoniq_t * ensoniq,
550 				 unsigned short reg, unsigned short data)
551 {
552 	unsigned int r;
553 
554 	r = snd_es1371_wait_src_ready(ensoniq) &
555 	    (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
556 	     ES_1371_DIS_P2 | ES_1371_DIS_R1);
557 	r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
558 	outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
559 }
560 
561 #endif /* CHIP1371 */
562 
563 #ifdef CHIP1370
564 
565 static void snd_es1370_codec_write(ak4531_t *ak4531,
566 				   unsigned short reg, unsigned short val)
567 {
568 	ensoniq_t *ensoniq = ak4531->private_data;
569 	unsigned long end_time = jiffies + HZ / 10;
570 
571 #if 0
572 	printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
573 #endif
574 	do {
575 		if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
576 			outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
577 			return;
578 		}
579 		set_current_state(TASK_UNINTERRUPTIBLE);
580 		schedule_timeout(1);
581 	} while (time_after(end_time, jiffies));
582 	snd_printk("codec write timeout, status = 0x%x\n", inl(ES_REG(ensoniq, STATUS)));
583 }
584 
585 #endif /* CHIP1370 */
586 
587 #ifdef CHIP1371
588 
589 static void snd_es1371_codec_write(ac97_t *ac97,
590 				   unsigned short reg, unsigned short val)
591 {
592 	ensoniq_t *ensoniq = ac97->private_data;
593 	unsigned int t, x;
594 
595 	down(&ensoniq->src_mutex);
596 	for (t = 0; t < POLL_COUNT; t++) {
597 		if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
598 			/* save the current state for latter */
599 			x = snd_es1371_wait_src_ready(ensoniq);
600 			outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
601 			           ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
602 			     ES_REG(ensoniq, 1371_SMPRATE));
603 			/* wait for not busy (state 0) first to avoid
604 			   transition states */
605 			for (t = 0; t < POLL_COUNT; t++) {
606 				if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
607 					break;
608 			}
609 			/* wait for a SAFE time to write addr/data and then do it, dammit */
610 			for (t = 0; t < POLL_COUNT; t++) {
611 				if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
612 					break;
613 			}
614 			outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
615 			/* restore SRC reg */
616 			snd_es1371_wait_src_ready(ensoniq);
617 			outl(x, ES_REG(ensoniq, 1371_SMPRATE));
618 			up(&ensoniq->src_mutex);
619 			return;
620 		}
621 	}
622 	up(&ensoniq->src_mutex);
623 	snd_printk("codec write timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
624 }
625 
626 static unsigned short snd_es1371_codec_read(ac97_t *ac97,
627 					    unsigned short reg)
628 {
629 	ensoniq_t *ensoniq = ac97->private_data;
630 	unsigned int t, x, fail = 0;
631 
632       __again:
633 	down(&ensoniq->src_mutex);
634 	for (t = 0; t < POLL_COUNT; t++) {
635 		if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
636 			/* save the current state for latter */
637 			x = snd_es1371_wait_src_ready(ensoniq);
638 			outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
639 			           ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
640 			     ES_REG(ensoniq, 1371_SMPRATE));
641 			/* wait for not busy (state 0) first to avoid
642 			   transition states */
643 			for (t = 0; t < POLL_COUNT; t++) {
644 				if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000)
645 					break;
646 			}
647 			/* wait for a SAFE time to write addr/data and then do it, dammit */
648 			for (t = 0; t < POLL_COUNT; t++) {
649 				if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000)
650 					break;
651 			}
652 			outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
653 			/* restore SRC reg */
654 			snd_es1371_wait_src_ready(ensoniq);
655 			outl(x, ES_REG(ensoniq, 1371_SMPRATE));
656 			/* wait for WIP again */
657 			for (t = 0; t < POLL_COUNT; t++) {
658 				if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
659 					break;
660 			}
661 			/* now wait for the stinkin' data (RDY) */
662 			for (t = 0; t < POLL_COUNT; t++) {
663 				if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
664 					up(&ensoniq->src_mutex);
665 					return ES_1371_CODEC_READ(x);
666 				}
667 			}
668 			up(&ensoniq->src_mutex);
669 			if (++fail > 10) {
670 				snd_printk("codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), reg, inl(ES_REG(ensoniq, 1371_CODEC)));
671 				return 0;
672 			}
673 			goto __again;
674 		}
675 	}
676 	up(&ensoniq->src_mutex);
677 	snd_printk("es1371: codec read timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
678 	return 0;
679 }
680 
681 static void snd_es1371_codec_wait(ac97_t *ac97)
682 {
683 	msleep(750);
684 	snd_es1371_codec_read(ac97, AC97_RESET);
685 	snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
686 	snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
687 	msleep(50);
688 }
689 
690 static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate)
691 {
692 	unsigned int n, truncm, freq, result;
693 
694 	down(&ensoniq->src_mutex);
695 	n = rate / 3000;
696 	if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
697 		n--;
698 	truncm = (21 * n - 1) | 1;
699 	freq = ((48000UL << 15) / rate) * n;
700 	result = (48000UL << 15) / (freq / n);
701 	if (rate >= 24000) {
702 		if (truncm > 239)
703 			truncm = 239;
704 		snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
705 				(((239 - truncm) >> 1) << 9) | (n << 4));
706 	} else {
707 		if (truncm > 119)
708 			truncm = 119;
709 		snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
710 				0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
711 	}
712 	snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
713 			     (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 0x00ff) |
714 				     ((freq >> 5) & 0xfc00));
715 	snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
716 	snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
717 	snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
718 	up(&ensoniq->src_mutex);
719 }
720 
721 static void snd_es1371_dac1_rate(ensoniq_t * ensoniq, unsigned int rate)
722 {
723 	unsigned int freq, r;
724 
725 	down(&ensoniq->src_mutex);
726 	freq = ((rate << 15) + 1500) / 3000;
727 	r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | ES_1371_DIS_P1;
728 	outl(r, ES_REG(ensoniq, 1371_SMPRATE));
729 	snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
730 			     (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS) & 0x00ff) |
731 			     ((freq >> 5) & 0xfc00));
732 	snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
733 	r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1));
734 	outl(r, ES_REG(ensoniq, 1371_SMPRATE));
735 	up(&ensoniq->src_mutex);
736 }
737 
738 static void snd_es1371_dac2_rate(ensoniq_t * ensoniq, unsigned int rate)
739 {
740 	unsigned int freq, r;
741 
742 	down(&ensoniq->src_mutex);
743 	freq = ((rate << 15) + 1500) / 3000;
744 	r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1)) | ES_1371_DIS_P2;
745 	outl(r, ES_REG(ensoniq, 1371_SMPRATE));
746 	snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
747 			     (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS) & 0x00ff) |
748 			     ((freq >> 5) & 0xfc00));
749 	snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
750 	r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1));
751 	outl(r, ES_REG(ensoniq, 1371_SMPRATE));
752 	up(&ensoniq->src_mutex);
753 }
754 
755 #endif /* CHIP1371 */
756 
757 static int snd_ensoniq_trigger(snd_pcm_substream_t *substream, int cmd)
758 {
759 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
760 	switch (cmd) {
761 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
762 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
763 	{
764 		unsigned int what = 0;
765 		struct list_head *pos;
766 		snd_pcm_substream_t *s;
767 		snd_pcm_group_for_each(pos, substream) {
768 			s = snd_pcm_group_substream_entry(pos);
769 			if (s == ensoniq->playback1_substream) {
770 				what |= ES_P1_PAUSE;
771 				snd_pcm_trigger_done(s, substream);
772 			} else if (s == ensoniq->playback2_substream) {
773 				what |= ES_P2_PAUSE;
774 				snd_pcm_trigger_done(s, substream);
775 			} else if (s == ensoniq->capture_substream)
776 				return -EINVAL;
777 		}
778 		spin_lock(&ensoniq->reg_lock);
779 		if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
780 			ensoniq->sctrl |= what;
781 		else
782 			ensoniq->sctrl &= ~what;
783 		outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
784 		spin_unlock(&ensoniq->reg_lock);
785 		break;
786 	}
787 	case SNDRV_PCM_TRIGGER_START:
788 	case SNDRV_PCM_TRIGGER_STOP:
789 	{
790 		unsigned int what = 0;
791 		struct list_head *pos;
792 		snd_pcm_substream_t *s;
793 		snd_pcm_group_for_each(pos, substream) {
794 			s = snd_pcm_group_substream_entry(pos);
795 			if (s == ensoniq->playback1_substream) {
796 				what |= ES_DAC1_EN;
797 				snd_pcm_trigger_done(s, substream);
798 			} else if (s == ensoniq->playback2_substream) {
799 				what |= ES_DAC2_EN;
800 				snd_pcm_trigger_done(s, substream);
801 			} else if (s == ensoniq->capture_substream) {
802 				what |= ES_ADC_EN;
803 				snd_pcm_trigger_done(s, substream);
804 			}
805 		}
806 		spin_lock(&ensoniq->reg_lock);
807 		if (cmd == SNDRV_PCM_TRIGGER_START)
808 			ensoniq->ctrl |= what;
809 		else
810 			ensoniq->ctrl &= ~what;
811 		outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
812 		spin_unlock(&ensoniq->reg_lock);
813 		break;
814 	}
815 	default:
816 		return -EINVAL;
817 	}
818 	return 0;
819 }
820 
821 /*
822  *  PCM part
823  */
824 
825 static int snd_ensoniq_hw_params(snd_pcm_substream_t * substream,
826 				 snd_pcm_hw_params_t * hw_params)
827 {
828 	return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
829 }
830 
831 static int snd_ensoniq_hw_free(snd_pcm_substream_t * substream)
832 {
833 	return snd_pcm_lib_free_pages(substream);
834 }
835 
836 static int snd_ensoniq_playback1_prepare(snd_pcm_substream_t * substream)
837 {
838 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
839 	snd_pcm_runtime_t *runtime = substream->runtime;
840 	unsigned int mode = 0;
841 
842 	ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
843 	ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
844 	if (snd_pcm_format_width(runtime->format) == 16)
845 		mode |= 0x02;
846 	if (runtime->channels > 1)
847 		mode |= 0x01;
848 	spin_lock_irq(&ensoniq->reg_lock);
849 	ensoniq->ctrl &= ~ES_DAC1_EN;
850 #ifdef CHIP1371
851 	/* 48k doesn't need SRC (it breaks AC3-passthru) */
852 	if (runtime->rate == 48000)
853 		ensoniq->ctrl |= ES_1373_BYPASS_P1;
854 	else
855 		ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
856 #endif
857 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
858 	outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
859 	outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
860 	outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
861 	ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
862 	ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
863 	outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
864 	outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC1_COUNT));
865 #ifdef CHIP1370
866 	ensoniq->ctrl &= ~ES_1370_WTSRSELM;
867 	switch (runtime->rate) {
868 	case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
869 	case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
870 	case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
871 	case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
872 	default: snd_BUG();
873 	}
874 #endif
875 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
876 	spin_unlock_irq(&ensoniq->reg_lock);
877 #ifndef CHIP1370
878 	snd_es1371_dac1_rate(ensoniq, runtime->rate);
879 #endif
880 	return 0;
881 }
882 
883 static int snd_ensoniq_playback2_prepare(snd_pcm_substream_t * substream)
884 {
885 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
886 	snd_pcm_runtime_t *runtime = substream->runtime;
887 	unsigned int mode = 0;
888 
889 	ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
890 	ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
891 	if (snd_pcm_format_width(runtime->format) == 16)
892 		mode |= 0x02;
893 	if (runtime->channels > 1)
894 		mode |= 0x01;
895 	spin_lock_irq(&ensoniq->reg_lock);
896 	ensoniq->ctrl &= ~ES_DAC2_EN;
897 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
898 	outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
899 	outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
900 	outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
901 	ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
902 			    ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
903 	ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
904 			  ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
905 	outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
906 	outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC2_COUNT));
907 #ifdef CHIP1370
908 	if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
909 		ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
910 		ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
911 		ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
912 	}
913 #endif
914 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
915 	spin_unlock_irq(&ensoniq->reg_lock);
916 #ifndef CHIP1370
917 	snd_es1371_dac2_rate(ensoniq, runtime->rate);
918 #endif
919 	return 0;
920 }
921 
922 static int snd_ensoniq_capture_prepare(snd_pcm_substream_t * substream)
923 {
924 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
925 	snd_pcm_runtime_t *runtime = substream->runtime;
926 	unsigned int mode = 0;
927 
928 	ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
929 	ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
930 	if (snd_pcm_format_width(runtime->format) == 16)
931 		mode |= 0x02;
932 	if (runtime->channels > 1)
933 		mode |= 0x01;
934 	spin_lock_irq(&ensoniq->reg_lock);
935 	ensoniq->ctrl &= ~ES_ADC_EN;
936 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
937 	outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
938 	outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
939 	outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
940 	ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
941 	ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
942 	outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
943 	outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, ADC_COUNT));
944 #ifdef CHIP1370
945 	if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
946 		ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
947 		ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
948 		ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
949 	}
950 #endif
951 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
952 	spin_unlock_irq(&ensoniq->reg_lock);
953 #ifndef CHIP1370
954 	snd_es1371_adc_rate(ensoniq, runtime->rate);
955 #endif
956 	return 0;
957 }
958 
959 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(snd_pcm_substream_t * substream)
960 {
961 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
962 	size_t ptr;
963 
964 	spin_lock(&ensoniq->reg_lock);
965 	if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
966 		outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
967 		ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
968 		ptr = bytes_to_frames(substream->runtime, ptr);
969 	} else {
970 		ptr = 0;
971 	}
972 	spin_unlock(&ensoniq->reg_lock);
973 	return ptr;
974 }
975 
976 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(snd_pcm_substream_t * substream)
977 {
978 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
979 	size_t ptr;
980 
981 	spin_lock(&ensoniq->reg_lock);
982 	if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
983 		outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
984 		ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
985 		ptr = bytes_to_frames(substream->runtime, ptr);
986 	} else {
987 		ptr = 0;
988 	}
989 	spin_unlock(&ensoniq->reg_lock);
990 	return ptr;
991 }
992 
993 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(snd_pcm_substream_t * substream)
994 {
995 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
996 	size_t ptr;
997 
998 	spin_lock(&ensoniq->reg_lock);
999 	if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1000 		outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1001 		ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1002 		ptr = bytes_to_frames(substream->runtime, ptr);
1003 	} else {
1004 		ptr = 0;
1005 	}
1006 	spin_unlock(&ensoniq->reg_lock);
1007 	return ptr;
1008 }
1009 
1010 static snd_pcm_hardware_t snd_ensoniq_playback1 =
1011 {
1012 	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1013 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1014 				 SNDRV_PCM_INFO_MMAP_VALID |
1015 				 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1016 	.formats =		SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1017 	.rates =
1018 #ifndef CHIP1370
1019 				SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1020 #else
1021 				(SNDRV_PCM_RATE_KNOT | 	/* 5512Hz rate */
1022 				 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1023 				 SNDRV_PCM_RATE_44100),
1024 #endif
1025 	.rate_min =		4000,
1026 	.rate_max =		48000,
1027 	.channels_min =		1,
1028 	.channels_max =		2,
1029 	.buffer_bytes_max =	(128*1024),
1030 	.period_bytes_min =	64,
1031 	.period_bytes_max =	(128*1024),
1032 	.periods_min =		1,
1033 	.periods_max =		1024,
1034 	.fifo_size =		0,
1035 };
1036 
1037 static snd_pcm_hardware_t snd_ensoniq_playback2 =
1038 {
1039 	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1040 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1041 				 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1042 				 SNDRV_PCM_INFO_SYNC_START),
1043 	.formats =		SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1044 	.rates =		SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1045 	.rate_min =		4000,
1046 	.rate_max =		48000,
1047 	.channels_min =		1,
1048 	.channels_max =		2,
1049 	.buffer_bytes_max =	(128*1024),
1050 	.period_bytes_min =	64,
1051 	.period_bytes_max =	(128*1024),
1052 	.periods_min =		1,
1053 	.periods_max =		1024,
1054 	.fifo_size =		0,
1055 };
1056 
1057 static snd_pcm_hardware_t snd_ensoniq_capture =
1058 {
1059 	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1060 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1061 				 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1062 	.formats =		SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1063 	.rates =		SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1064 	.rate_min =		4000,
1065 	.rate_max =		48000,
1066 	.channels_min =		1,
1067 	.channels_max =		2,
1068 	.buffer_bytes_max =	(128*1024),
1069 	.period_bytes_min =	64,
1070 	.period_bytes_max =	(128*1024),
1071 	.periods_min =		1,
1072 	.periods_max =		1024,
1073 	.fifo_size =		0,
1074 };
1075 
1076 static int snd_ensoniq_playback1_open(snd_pcm_substream_t * substream)
1077 {
1078 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1079 	snd_pcm_runtime_t *runtime = substream->runtime;
1080 
1081 	ensoniq->mode |= ES_MODE_PLAY1;
1082 	ensoniq->playback1_substream = substream;
1083 	runtime->hw = snd_ensoniq_playback1;
1084 	snd_pcm_set_sync(substream);
1085 	spin_lock_irq(&ensoniq->reg_lock);
1086 	if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1087 		ensoniq->spdif_stream = ensoniq->spdif_default;
1088 	spin_unlock_irq(&ensoniq->reg_lock);
1089 #ifdef CHIP1370
1090 	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1091 				   &snd_es1370_hw_constraints_rates);
1092 #else
1093 	snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1094 				      &snd_es1371_hw_constraints_dac_clock);
1095 #endif
1096 	return 0;
1097 }
1098 
1099 static int snd_ensoniq_playback2_open(snd_pcm_substream_t * substream)
1100 {
1101 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1102 	snd_pcm_runtime_t *runtime = substream->runtime;
1103 
1104 	ensoniq->mode |= ES_MODE_PLAY2;
1105 	ensoniq->playback2_substream = substream;
1106 	runtime->hw = snd_ensoniq_playback2;
1107 	snd_pcm_set_sync(substream);
1108 	spin_lock_irq(&ensoniq->reg_lock);
1109 	if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1110 		ensoniq->spdif_stream = ensoniq->spdif_default;
1111 	spin_unlock_irq(&ensoniq->reg_lock);
1112 #ifdef CHIP1370
1113 	snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1114 				      &snd_es1370_hw_constraints_clock);
1115 #else
1116 	snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1117 				      &snd_es1371_hw_constraints_dac_clock);
1118 #endif
1119 	return 0;
1120 }
1121 
1122 static int snd_ensoniq_capture_open(snd_pcm_substream_t * substream)
1123 {
1124 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1125 	snd_pcm_runtime_t *runtime = substream->runtime;
1126 
1127 	ensoniq->mode |= ES_MODE_CAPTURE;
1128 	ensoniq->capture_substream = substream;
1129 	runtime->hw = snd_ensoniq_capture;
1130 	snd_pcm_set_sync(substream);
1131 #ifdef CHIP1370
1132 	snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1133 				      &snd_es1370_hw_constraints_clock);
1134 #else
1135 	snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1136 				      &snd_es1371_hw_constraints_adc_clock);
1137 #endif
1138 	return 0;
1139 }
1140 
1141 static int snd_ensoniq_playback1_close(snd_pcm_substream_t * substream)
1142 {
1143 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1144 
1145 	ensoniq->playback1_substream = NULL;
1146 	ensoniq->mode &= ~ES_MODE_PLAY1;
1147 	return 0;
1148 }
1149 
1150 static int snd_ensoniq_playback2_close(snd_pcm_substream_t * substream)
1151 {
1152 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1153 
1154 	ensoniq->playback2_substream = NULL;
1155 	spin_lock_irq(&ensoniq->reg_lock);
1156 #ifdef CHIP1370
1157 	ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1158 #endif
1159 	ensoniq->mode &= ~ES_MODE_PLAY2;
1160 	spin_unlock_irq(&ensoniq->reg_lock);
1161 	return 0;
1162 }
1163 
1164 static int snd_ensoniq_capture_close(snd_pcm_substream_t * substream)
1165 {
1166 	ensoniq_t *ensoniq = snd_pcm_substream_chip(substream);
1167 
1168 	ensoniq->capture_substream = NULL;
1169 	spin_lock_irq(&ensoniq->reg_lock);
1170 #ifdef CHIP1370
1171 	ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1172 #endif
1173 	ensoniq->mode &= ~ES_MODE_CAPTURE;
1174 	spin_unlock_irq(&ensoniq->reg_lock);
1175 	return 0;
1176 }
1177 
1178 static snd_pcm_ops_t snd_ensoniq_playback1_ops = {
1179 	.open =		snd_ensoniq_playback1_open,
1180 	.close =	snd_ensoniq_playback1_close,
1181 	.ioctl =	snd_pcm_lib_ioctl,
1182 	.hw_params =	snd_ensoniq_hw_params,
1183 	.hw_free =	snd_ensoniq_hw_free,
1184 	.prepare =	snd_ensoniq_playback1_prepare,
1185 	.trigger =	snd_ensoniq_trigger,
1186 	.pointer =	snd_ensoniq_playback1_pointer,
1187 };
1188 
1189 static snd_pcm_ops_t snd_ensoniq_playback2_ops = {
1190 	.open =		snd_ensoniq_playback2_open,
1191 	.close =	snd_ensoniq_playback2_close,
1192 	.ioctl =	snd_pcm_lib_ioctl,
1193 	.hw_params =	snd_ensoniq_hw_params,
1194 	.hw_free =	snd_ensoniq_hw_free,
1195 	.prepare =	snd_ensoniq_playback2_prepare,
1196 	.trigger =	snd_ensoniq_trigger,
1197 	.pointer =	snd_ensoniq_playback2_pointer,
1198 };
1199 
1200 static snd_pcm_ops_t snd_ensoniq_capture_ops = {
1201 	.open =		snd_ensoniq_capture_open,
1202 	.close =	snd_ensoniq_capture_close,
1203 	.ioctl =	snd_pcm_lib_ioctl,
1204 	.hw_params =	snd_ensoniq_hw_params,
1205 	.hw_free =	snd_ensoniq_hw_free,
1206 	.prepare =	snd_ensoniq_capture_prepare,
1207 	.trigger =	snd_ensoniq_trigger,
1208 	.pointer =	snd_ensoniq_capture_pointer,
1209 };
1210 
1211 static void snd_ensoniq_pcm_free(snd_pcm_t *pcm)
1212 {
1213 	ensoniq_t *ensoniq = pcm->private_data;
1214 	ensoniq->pcm1 = NULL;
1215 	snd_pcm_lib_preallocate_free_for_all(pcm);
1216 }
1217 
1218 static int __devinit snd_ensoniq_pcm(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1219 {
1220 	snd_pcm_t *pcm;
1221 	int err;
1222 
1223 	if (rpcm)
1224 		*rpcm = NULL;
1225 #ifdef CHIP1370
1226 	err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1227 #else
1228 	err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1229 #endif
1230 	if (err < 0)
1231 		return err;
1232 
1233 #ifdef CHIP1370
1234 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1235 #else
1236 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1237 #endif
1238 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1239 
1240 	pcm->private_data = ensoniq;
1241 	pcm->private_free = snd_ensoniq_pcm_free;
1242 	pcm->info_flags = 0;
1243 #ifdef CHIP1370
1244 	strcpy(pcm->name, "ES1370 DAC2/ADC");
1245 #else
1246 	strcpy(pcm->name, "ES1371 DAC2/ADC");
1247 #endif
1248 	ensoniq->pcm1 = pcm;
1249 
1250 	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1251 					      snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1252 
1253 	if (rpcm)
1254 		*rpcm = pcm;
1255 	return 0;
1256 }
1257 
1258 static void snd_ensoniq_pcm_free2(snd_pcm_t *pcm)
1259 {
1260 	ensoniq_t *ensoniq = pcm->private_data;
1261 	ensoniq->pcm2 = NULL;
1262 	snd_pcm_lib_preallocate_free_for_all(pcm);
1263 }
1264 
1265 static int __devinit snd_ensoniq_pcm2(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm)
1266 {
1267 	snd_pcm_t *pcm;
1268 	int err;
1269 
1270 	if (rpcm)
1271 		*rpcm = NULL;
1272 #ifdef CHIP1370
1273 	err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1274 #else
1275 	err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1276 #endif
1277 	if (err < 0)
1278 		return err;
1279 
1280 #ifdef CHIP1370
1281 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1282 #else
1283 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1284 #endif
1285 	pcm->private_data = ensoniq;
1286 	pcm->private_free = snd_ensoniq_pcm_free2;
1287 	pcm->info_flags = 0;
1288 #ifdef CHIP1370
1289 	strcpy(pcm->name, "ES1370 DAC1");
1290 #else
1291 	strcpy(pcm->name, "ES1371 DAC1");
1292 #endif
1293 	ensoniq->pcm2 = pcm;
1294 
1295 	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1296 					      snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1297 
1298 	if (rpcm)
1299 		*rpcm = pcm;
1300 	return 0;
1301 }
1302 
1303 /*
1304  *  Mixer section
1305  */
1306 
1307 /*
1308  * ENS1371 mixer (including SPDIF interface)
1309  */
1310 #ifdef CHIP1371
1311 static int snd_ens1373_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
1312 {
1313 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1314 	uinfo->count = 1;
1315 	return 0;
1316 }
1317 
1318 static int snd_ens1373_spdif_default_get(snd_kcontrol_t * kcontrol,
1319                                          snd_ctl_elem_value_t * ucontrol)
1320 {
1321 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1322 	spin_lock_irq(&ensoniq->reg_lock);
1323 	ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1324 	ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1325 	ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1326 	ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1327 	spin_unlock_irq(&ensoniq->reg_lock);
1328 	return 0;
1329 }
1330 
1331 static int snd_ens1373_spdif_default_put(snd_kcontrol_t * kcontrol,
1332                                          snd_ctl_elem_value_t * ucontrol)
1333 {
1334 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1335 	unsigned int val;
1336 	int change;
1337 
1338 	val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1339 	      ((u32)ucontrol->value.iec958.status[1] << 8) |
1340 	      ((u32)ucontrol->value.iec958.status[2] << 16) |
1341 	      ((u32)ucontrol->value.iec958.status[3] << 24);
1342 	spin_lock_irq(&ensoniq->reg_lock);
1343 	change = ensoniq->spdif_default != val;
1344 	ensoniq->spdif_default = val;
1345 	if (change && ensoniq->playback1_substream == NULL && ensoniq->playback2_substream == NULL)
1346 		outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1347 	spin_unlock_irq(&ensoniq->reg_lock);
1348 	return change;
1349 }
1350 
1351 static int snd_ens1373_spdif_mask_get(snd_kcontrol_t * kcontrol,
1352                                          snd_ctl_elem_value_t * ucontrol)
1353 {
1354 	ucontrol->value.iec958.status[0] = 0xff;
1355 	ucontrol->value.iec958.status[1] = 0xff;
1356 	ucontrol->value.iec958.status[2] = 0xff;
1357 	ucontrol->value.iec958.status[3] = 0xff;
1358 	return 0;
1359 }
1360 
1361 static int snd_ens1373_spdif_stream_get(snd_kcontrol_t * kcontrol,
1362                                          snd_ctl_elem_value_t * ucontrol)
1363 {
1364 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1365 	spin_lock_irq(&ensoniq->reg_lock);
1366 	ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1367 	ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1368 	ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1369 	ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1370 	spin_unlock_irq(&ensoniq->reg_lock);
1371 	return 0;
1372 }
1373 
1374 static int snd_ens1373_spdif_stream_put(snd_kcontrol_t * kcontrol,
1375                                         snd_ctl_elem_value_t * ucontrol)
1376 {
1377 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1378 	unsigned int val;
1379 	int change;
1380 
1381 	val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1382 	      ((u32)ucontrol->value.iec958.status[1] << 8) |
1383 	      ((u32)ucontrol->value.iec958.status[2] << 16) |
1384 	      ((u32)ucontrol->value.iec958.status[3] << 24);
1385 	spin_lock_irq(&ensoniq->reg_lock);
1386 	change = ensoniq->spdif_stream != val;
1387 	ensoniq->spdif_stream = val;
1388 	if (change && (ensoniq->playback1_substream != NULL || ensoniq->playback2_substream != NULL))
1389 		outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1390 	spin_unlock_irq(&ensoniq->reg_lock);
1391 	return change;
1392 }
1393 
1394 #define ES1371_SPDIF(xname) \
1395 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1396   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1397 
1398 static int snd_es1371_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1399 {
1400         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1401         uinfo->count = 1;
1402         uinfo->value.integer.min = 0;
1403         uinfo->value.integer.max = 1;
1404         return 0;
1405 }
1406 
1407 static int snd_es1371_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1408 {
1409 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1410 
1411 	spin_lock_irq(&ensoniq->reg_lock);
1412 	ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1413 	spin_unlock_irq(&ensoniq->reg_lock);
1414 	return 0;
1415 }
1416 
1417 static int snd_es1371_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1418 {
1419 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1420 	unsigned int nval1, nval2;
1421 	int change;
1422 
1423 	nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1424 	nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1425 	spin_lock_irq(&ensoniq->reg_lock);
1426 	change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1427 	ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1428 	ensoniq->ctrl |= nval1;
1429 	ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1430 	ensoniq->cssr |= nval2;
1431 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1432 	outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1433 	spin_unlock_irq(&ensoniq->reg_lock);
1434 	return change;
1435 }
1436 
1437 
1438 /* spdif controls */
1439 static snd_kcontrol_new_t snd_es1371_mixer_spdif[] __devinitdata = {
1440 	ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1441 	{
1442 		.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
1443 		.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1444 		.info =		snd_ens1373_spdif_info,
1445 		.get =		snd_ens1373_spdif_default_get,
1446 		.put =		snd_ens1373_spdif_default_put,
1447 	},
1448 	{
1449 		.access =	SNDRV_CTL_ELEM_ACCESS_READ,
1450 		.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
1451 		.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1452 		.info =		snd_ens1373_spdif_info,
1453 		.get =		snd_ens1373_spdif_mask_get
1454 	},
1455 	{
1456 		.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
1457 		.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1458 		.info =		snd_ens1373_spdif_info,
1459 		.get =		snd_ens1373_spdif_stream_get,
1460 		.put =		snd_ens1373_spdif_stream_put
1461 	},
1462 };
1463 
1464 
1465 static int snd_es1373_rear_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1466 {
1467         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1468         uinfo->count = 1;
1469         uinfo->value.integer.min = 0;
1470         uinfo->value.integer.max = 1;
1471         return 0;
1472 }
1473 
1474 static int snd_es1373_rear_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1475 {
1476 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1477 	int val = 0;
1478 
1479 	spin_lock_irq(&ensoniq->reg_lock);
1480 	if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1481 	    	val = 1;
1482 	ucontrol->value.integer.value[0] = val;
1483 	spin_unlock_irq(&ensoniq->reg_lock);
1484 	return 0;
1485 }
1486 
1487 static int snd_es1373_rear_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1488 {
1489 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1490 	unsigned int nval1;
1491 	int change;
1492 
1493 	nval1 = ucontrol->value.integer.value[0] ? ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1494 	spin_lock_irq(&ensoniq->reg_lock);
1495 	change = (ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1496 	ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1497 	ensoniq->cssr |= nval1;
1498 	outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1499 	spin_unlock_irq(&ensoniq->reg_lock);
1500 	return change;
1501 }
1502 
1503 static snd_kcontrol_new_t snd_ens1373_rear __devinitdata =
1504 {
1505 	.iface =	SNDRV_CTL_ELEM_IFACE_MIXER,
1506 	.name =		"AC97 2ch->4ch Copy Switch",
1507 	.info =		snd_es1373_rear_info,
1508 	.get =		snd_es1373_rear_get,
1509 	.put =		snd_es1373_rear_put,
1510 };
1511 
1512 static int snd_es1373_line_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1513 {
1514 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1515 	uinfo->count = 1;
1516 	uinfo->value.integer.min = 0;
1517 	uinfo->value.integer.max = 1;
1518 	return 0;
1519 }
1520 
1521 static int snd_es1373_line_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1522 {
1523 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1524 	int val = 0;
1525 
1526 	spin_lock_irq(&ensoniq->reg_lock);
1527 	if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1528 	    	val = 1;
1529 	ucontrol->value.integer.value[0] = val;
1530 	spin_unlock_irq(&ensoniq->reg_lock);
1531 	return 0;
1532 }
1533 
1534 static int snd_es1373_line_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1535 {
1536 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1537 	int changed;
1538 	unsigned int ctrl;
1539 
1540 	spin_lock_irq(&ensoniq->reg_lock);
1541 	ctrl = ensoniq->ctrl;
1542 	if (ucontrol->value.integer.value[0])
1543 		ensoniq->ctrl |= ES_1371_GPIO_OUT(4);	/* switch line-in -> rear out */
1544 	else
1545 		ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1546 	changed = (ctrl != ensoniq->ctrl);
1547 	if (changed)
1548 		outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1549 	spin_unlock_irq(&ensoniq->reg_lock);
1550 	return changed;
1551 }
1552 
1553 static snd_kcontrol_new_t snd_ens1373_line __devinitdata =
1554 {
1555 	.iface =	SNDRV_CTL_ELEM_IFACE_MIXER,
1556 	.name =		"Line In->Rear Out Switch",
1557 	.info =		snd_es1373_line_info,
1558 	.get =		snd_es1373_line_get,
1559 	.put =		snd_es1373_line_put,
1560 };
1561 
1562 static void snd_ensoniq_mixer_free_ac97(ac97_t *ac97)
1563 {
1564 	ensoniq_t *ensoniq = ac97->private_data;
1565 	ensoniq->u.es1371.ac97 = NULL;
1566 }
1567 
1568 static struct {
1569 	unsigned short vid;		/* vendor ID */
1570 	unsigned short did;		/* device ID */
1571 	unsigned char rev;		/* revision */
1572 } es1371_spdif_present[] __devinitdata = {
1573 	{ .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1574 	{ .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1575 	{ .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1576 	{ .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1577 	{ .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1578 	{ .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1579 };
1580 
1581 static int snd_ensoniq_1371_mixer(ensoniq_t * ensoniq)
1582 {
1583 	snd_card_t *card = ensoniq->card;
1584 	ac97_bus_t *pbus;
1585 	ac97_template_t ac97;
1586 	int err, idx;
1587 	static ac97_bus_ops_t ops = {
1588 		.write = snd_es1371_codec_write,
1589 		.read = snd_es1371_codec_read,
1590 		.wait = snd_es1371_codec_wait,
1591 	};
1592 
1593 	if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1594 		return err;
1595 
1596 	memset(&ac97, 0, sizeof(ac97));
1597 	ac97.private_data = ensoniq;
1598 	ac97.private_free = snd_ensoniq_mixer_free_ac97;
1599 	ac97.scaps = AC97_SCAP_AUDIO;
1600 	if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1601 		return err;
1602 	for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1603 		if (ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1604 		    ensoniq->pci->device == es1371_spdif_present[idx].did &&
1605 		    ensoniq->rev == es1371_spdif_present[idx].rev) {
1606 		    	snd_kcontrol_t *kctl;
1607 			int i, index = 0;
1608 
1609 			ensoniq->spdif_default = ensoniq->spdif_stream = SNDRV_PCM_DEFAULT_CON_SPDIF;
1610 			outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1611 
1612 		    	if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1613 			    	index++;
1614 
1615 			for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1616 				kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1617 				if (! kctl)
1618 					return -ENOMEM;
1619 				kctl->id.index = index;
1620 				if ((err = snd_ctl_add(card, kctl)) < 0)
1621 					return err;
1622 			}
1623 			break;
1624 		}
1625 	if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1626 		/* mirror rear to front speakers */
1627 		ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1628 		ensoniq->cssr |= ES_1373_REAR_BIT26;
1629 		err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1630 		if (err < 0)
1631 			return err;
1632 	}
1633 	if (((ensoniq->subsystem_vendor_id == 0x1274) &&
1634 	    (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */
1635 	    ((ensoniq->subsystem_vendor_id == 0x1458) &&
1636 	    (ensoniq->subsystem_device_id == 0xa000))) { /* GA-8IEXP */
1637 		 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1638 		 if (err < 0)
1639 			 return err;
1640 	}
1641 
1642 	return 0;
1643 }
1644 
1645 #endif /* CHIP1371 */
1646 
1647 /* generic control callbacks for ens1370 */
1648 #ifdef CHIP1370
1649 #define ENSONIQ_CONTROL(xname, mask) \
1650 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1651   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1652   .private_value = mask }
1653 
1654 static int snd_ensoniq_control_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
1655 {
1656         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1657         uinfo->count = 1;
1658         uinfo->value.integer.min = 0;
1659         uinfo->value.integer.max = 1;
1660         return 0;
1661 }
1662 
1663 static int snd_ensoniq_control_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1664 {
1665 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1666 	int mask = kcontrol->private_value;
1667 
1668 	spin_lock_irq(&ensoniq->reg_lock);
1669 	ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1670 	spin_unlock_irq(&ensoniq->reg_lock);
1671 	return 0;
1672 }
1673 
1674 static int snd_ensoniq_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
1675 {
1676 	ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol);
1677 	int mask = kcontrol->private_value;
1678 	unsigned int nval;
1679 	int change;
1680 
1681 	nval = ucontrol->value.integer.value[0] ? mask : 0;
1682 	spin_lock_irq(&ensoniq->reg_lock);
1683 	change = (ensoniq->ctrl & mask) != nval;
1684 	ensoniq->ctrl &= ~mask;
1685 	ensoniq->ctrl |= nval;
1686 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1687 	spin_unlock_irq(&ensoniq->reg_lock);
1688 	return change;
1689 }
1690 
1691 /*
1692  * ENS1370 mixer
1693  */
1694 
1695 static snd_kcontrol_new_t snd_es1370_controls[2] __devinitdata = {
1696 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1697 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1698 };
1699 
1700 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1701 
1702 static void snd_ensoniq_mixer_free_ak4531(ak4531_t *ak4531)
1703 {
1704 	ensoniq_t *ensoniq = ak4531->private_data;
1705 	ensoniq->u.es1370.ak4531 = NULL;
1706 }
1707 
1708 static int __devinit snd_ensoniq_1370_mixer(ensoniq_t * ensoniq)
1709 {
1710 	snd_card_t *card = ensoniq->card;
1711 	ak4531_t ak4531;
1712 	unsigned int idx;
1713 	int err;
1714 
1715 	/* try reset AK4531 */
1716 	outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1717 	inw(ES_REG(ensoniq, 1370_CODEC));
1718 	udelay(100);
1719 	outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1720 	inw(ES_REG(ensoniq, 1370_CODEC));
1721 	udelay(100);
1722 
1723 	memset(&ak4531, 0, sizeof(ak4531));
1724 	ak4531.write = snd_es1370_codec_write;
1725 	ak4531.private_data = ensoniq;
1726 	ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1727 	if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1728 		return err;
1729 	for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1730 		err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1731 		if (err < 0)
1732 			return err;
1733 	}
1734 	return 0;
1735 }
1736 
1737 #endif /* CHIP1370 */
1738 
1739 #ifdef SUPPORT_JOYSTICK
1740 
1741 #ifdef CHIP1371
1742 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1743 {
1744 	switch (joystick_port[dev]) {
1745 	case 0: /* disabled */
1746 	case 1: /* auto-detect */
1747 	case 0x200:
1748 	case 0x208:
1749 	case 0x210:
1750 	case 0x218:
1751 		return joystick_port[dev];
1752 
1753 	default:
1754 		printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1755 		return 0;
1756 	}
1757 }
1758 #else
1759 static inline int snd_ensoniq_get_joystick_port(int dev)
1760 {
1761 	return joystick[dev] ? 0x200 : 0;
1762 }
1763 #endif
1764 
1765 static int __devinit snd_ensoniq_create_gameport(ensoniq_t *ensoniq, int dev)
1766 {
1767 	struct gameport *gp;
1768 	int io_port;
1769 
1770 	io_port = snd_ensoniq_get_joystick_port(dev);
1771 
1772 	switch (io_port) {
1773 	case 0:
1774 		return -ENOSYS;
1775 
1776 	case 1: /* auto_detect */
1777 		for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1778 			if (request_region(io_port, 8, "ens137x: gameport"))
1779 				break;
1780 		if (io_port > 0x218) {
1781 			printk(KERN_WARNING "ens137x: no gameport ports available\n");
1782 			return -EBUSY;
1783 		}
1784 		break;
1785 
1786 	default:
1787 		if (!request_region(io_port, 8, "ens137x: gameport")) {
1788 			printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n", io_port);
1789 			return -EBUSY;
1790 		}
1791 		break;
1792 	}
1793 
1794 	ensoniq->gameport = gp = gameport_allocate_port();
1795 	if (!gp) {
1796 		printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1797 		release_region(io_port, 8);
1798 		return -ENOMEM;
1799 	}
1800 
1801 	gameport_set_name(gp, "ES137x");
1802 	gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1803 	gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1804 	gp->io = io_port;
1805 
1806 	ensoniq->ctrl |= ES_JYSTK_EN;
1807 #ifdef CHIP1371
1808 	ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1809 	ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1810 #endif
1811 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1812 
1813 	gameport_register_port(ensoniq->gameport);
1814 
1815 	return 0;
1816 }
1817 
1818 static void snd_ensoniq_free_gameport(ensoniq_t *ensoniq)
1819 {
1820 	if (ensoniq->gameport) {
1821 		int port = ensoniq->gameport->io;
1822 
1823 		gameport_unregister_port(ensoniq->gameport);
1824 		ensoniq->gameport = NULL;
1825 		ensoniq->ctrl &= ~ES_JYSTK_EN;
1826 		outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1827 		release_region(port, 8);
1828 	}
1829 }
1830 #else
1831 static inline int snd_ensoniq_create_gameport(ensoniq_t *ensoniq, long port) { return -ENOSYS; }
1832 static inline void snd_ensoniq_free_gameport(ensoniq_t *ensoniq) { }
1833 #endif /* SUPPORT_JOYSTICK */
1834 
1835 /*
1836 
1837  */
1838 
1839 static void snd_ensoniq_proc_read(snd_info_entry_t *entry,
1840 				  snd_info_buffer_t * buffer)
1841 {
1842 	ensoniq_t *ensoniq = entry->private_data;
1843 
1844 #ifdef CHIP1370
1845 	snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1846 #else
1847 	snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1848 #endif
1849 	snd_iprintf(buffer, "Joystick enable  : %s\n", ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1850 #ifdef CHIP1370
1851 	snd_iprintf(buffer, "MIC +5V bias     : %s\n", ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1852 	snd_iprintf(buffer, "Line In to AOUT  : %s\n", ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1853 #else
1854 	snd_iprintf(buffer, "Joystick port    : 0x%x\n", (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1855 #endif
1856 }
1857 
1858 static void __devinit snd_ensoniq_proc_init(ensoniq_t * ensoniq)
1859 {
1860 	snd_info_entry_t *entry;
1861 
1862 	if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1863 		snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1864 }
1865 
1866 /*
1867 
1868  */
1869 
1870 static int snd_ensoniq_free(ensoniq_t *ensoniq)
1871 {
1872 	snd_ensoniq_free_gameport(ensoniq);
1873 	if (ensoniq->irq < 0)
1874 		goto __hw_end;
1875 #ifdef CHIP1370
1876 	outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));	/* switch everything off */
1877 	outl(0, ES_REG(ensoniq, SERIAL));	/* clear serial interface */
1878 #else
1879 	outl(0, ES_REG(ensoniq, CONTROL));	/* switch everything off */
1880 	outl(0, ES_REG(ensoniq, SERIAL));	/* clear serial interface */
1881 #endif
1882 	synchronize_irq(ensoniq->irq);
1883 	pci_set_power_state(ensoniq->pci, 3);
1884       __hw_end:
1885 #ifdef CHIP1370
1886 	if (ensoniq->dma_bug.area)
1887 		snd_dma_free_pages(&ensoniq->dma_bug);
1888 #endif
1889 	if (ensoniq->irq >= 0)
1890 		free_irq(ensoniq->irq, (void *)ensoniq);
1891 	pci_release_regions(ensoniq->pci);
1892 	pci_disable_device(ensoniq->pci);
1893 	kfree(ensoniq);
1894 	return 0;
1895 }
1896 
1897 static int snd_ensoniq_dev_free(snd_device_t *device)
1898 {
1899 	ensoniq_t *ensoniq = device->device_data;
1900 	return snd_ensoniq_free(ensoniq);
1901 }
1902 
1903 #ifdef CHIP1371
1904 static struct {
1905 	unsigned short svid;		/* subsystem vendor ID */
1906 	unsigned short sdid;		/* subsystem device ID */
1907 } es1371_amplifier_hack[] = {
1908 	{ .svid = 0x107b, .sdid = 0x2150 },	/* Gateway Solo 2150 */
1909 	{ .svid = 0x13bd, .sdid = 0x100c },	/* EV1938 on Mebius PC-MJ100V */
1910 	{ .svid = 0x1102, .sdid = 0x5938 },	/* Targa Xtender300 */
1911 	{ .svid = 0x1102, .sdid = 0x8938 },	/* IPC Topnote G notebook */
1912 	{ .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1913 };
1914 static struct {
1915 	unsigned short vid;		/* vendor ID */
1916 	unsigned short did;		/* device ID */
1917 	unsigned char rev;		/* revision */
1918 } es1371_ac97_reset_hack[] = {
1919 	{ .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1920 	{ .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1921 	{ .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1922 	{ .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1923 	{ .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1924 	{ .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1925 };
1926 #endif
1927 
1928 static int __devinit snd_ensoniq_create(snd_card_t * card,
1929 				     struct pci_dev *pci,
1930 				     ensoniq_t ** rensoniq)
1931 {
1932 	ensoniq_t *ensoniq;
1933 	unsigned short cmdw;
1934 	unsigned char cmdb;
1935 #ifdef CHIP1371
1936 	int idx;
1937 #endif
1938 	int err;
1939 	static snd_device_ops_t ops = {
1940 		.dev_free =	snd_ensoniq_dev_free,
1941 	};
1942 
1943 	*rensoniq = NULL;
1944 	if ((err = pci_enable_device(pci)) < 0)
1945 		return err;
1946 	ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
1947 	if (ensoniq == NULL) {
1948 		pci_disable_device(pci);
1949 		return -ENOMEM;
1950 	}
1951 	spin_lock_init(&ensoniq->reg_lock);
1952 	init_MUTEX(&ensoniq->src_mutex);
1953 	ensoniq->card = card;
1954 	ensoniq->pci = pci;
1955 	ensoniq->irq = -1;
1956 	if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
1957 		kfree(ensoniq);
1958 		pci_disable_device(pci);
1959 		return err;
1960 	}
1961 	ensoniq->port = pci_resource_start(pci, 0);
1962 	if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ, "Ensoniq AudioPCI", (void *)ensoniq)) {
1963 		snd_printk("unable to grab IRQ %d\n", pci->irq);
1964 		snd_ensoniq_free(ensoniq);
1965 		return -EBUSY;
1966 	}
1967 	ensoniq->irq = pci->irq;
1968 #ifdef CHIP1370
1969 	if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1970 				16, &ensoniq->dma_bug) < 0) {
1971 		snd_printk("unable to allocate space for phantom area - dma_bug\n");
1972 		snd_ensoniq_free(ensoniq);
1973 		return -EBUSY;
1974 	}
1975 #endif
1976 	pci_set_master(pci);
1977 	pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
1978 	ensoniq->rev = cmdb;
1979 	pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
1980 	ensoniq->subsystem_vendor_id = cmdw;
1981 	pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
1982 	ensoniq->subsystem_device_id = cmdw;
1983 #ifdef CHIP1370
1984 #if 0
1985 	ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1986 #else	/* get microphone working */
1987 	ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
1988 #endif
1989 	ensoniq->sctrl = 0;
1990 	/* initialize the chips */
1991 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1992 	outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1993 	outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1994 	outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1995 	outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1996 #else
1997 	ensoniq->ctrl = 0;
1998 	ensoniq->sctrl = 0;
1999 	ensoniq->cssr = 0;
2000 	for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
2001 		if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
2002 		    ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
2003 			ensoniq->ctrl |= ES_1371_GPIO_OUT(1);	/* turn amplifier on */
2004 			break;
2005 		}
2006 	/* initialize the chips */
2007 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2008 	outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2009 	outl(0, ES_REG(ensoniq, 1371_LEGACY));
2010 	for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2011 		if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2012 		    pci->device == es1371_ac97_reset_hack[idx].did &&
2013 		    ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2014 			ensoniq->cssr |= ES_1371_ST_AC97_RST;
2015 			outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2016 			/* need to delay around 20ms(bleech) to give
2017 			some CODECs enough time to wakeup */
2018 			msleep(20);
2019 			break;
2020 		}
2021 	/* AC'97 warm reset to start the bitclk */
2022 	outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
2023 	inl(ES_REG(ensoniq, CONTROL));
2024 	udelay(20);
2025 	outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2026 	/* Init the sample rate converter */
2027 	snd_es1371_wait_src_ready(ensoniq);
2028 	outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2029 	for (idx = 0; idx < 0x80; idx++)
2030 		snd_es1371_src_write(ensoniq, idx, 0);
2031 	snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2032 	snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2033 	snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2034 	snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2035 	snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2036 	snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2037 	snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2038 	snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2039 	snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2040 	snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2041 	snd_es1371_adc_rate(ensoniq, 22050);
2042 	snd_es1371_dac1_rate(ensoniq, 22050);
2043 	snd_es1371_dac2_rate(ensoniq, 22050);
2044 	/* WARNING:
2045 	 * enabling the sample rate converter without properly programming
2046 	 * its parameters causes the chip to lock up (the SRC busy bit will
2047 	 * be stuck high, and I've found no way to rectify this other than
2048 	 * power cycle) - Thomas Sailer
2049 	 */
2050 	snd_es1371_wait_src_ready(ensoniq);
2051 	outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2052 	/* try reset codec directly */
2053 	outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2054 #endif
2055 	outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2056 	outb(0x00, ES_REG(ensoniq, UART_RES));
2057 	outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2058 	synchronize_irq(ensoniq->irq);
2059 
2060 	if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2061 		snd_ensoniq_free(ensoniq);
2062 		return err;
2063 	}
2064 
2065 	snd_ensoniq_proc_init(ensoniq);
2066 
2067 	snd_card_set_dev(card, &pci->dev);
2068 
2069 	*rensoniq = ensoniq;
2070 	return 0;
2071 }
2072 
2073 /*
2074  *  MIDI section
2075  */
2076 
2077 static void snd_ensoniq_midi_interrupt(ensoniq_t * ensoniq)
2078 {
2079 	snd_rawmidi_t * rmidi = ensoniq->rmidi;
2080 	unsigned char status, mask, byte;
2081 
2082 	if (rmidi == NULL)
2083 		return;
2084 	/* do Rx at first */
2085 	spin_lock(&ensoniq->reg_lock);
2086 	mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2087 	while (mask) {
2088 		status = inb(ES_REG(ensoniq, UART_STATUS));
2089 		if ((status & mask) == 0)
2090 			break;
2091 		byte = inb(ES_REG(ensoniq, UART_DATA));
2092 		snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2093 	}
2094 	spin_unlock(&ensoniq->reg_lock);
2095 
2096 	/* do Tx at second */
2097 	spin_lock(&ensoniq->reg_lock);
2098 	mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2099 	while (mask) {
2100 		status = inb(ES_REG(ensoniq, UART_STATUS));
2101 		if ((status & mask) == 0)
2102 			break;
2103 		if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2104 			ensoniq->uartc &= ~ES_TXINTENM;
2105 			outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2106 			mask &= ~ES_TXRDY;
2107 		} else {
2108 			outb(byte, ES_REG(ensoniq, UART_DATA));
2109 		}
2110 	}
2111 	spin_unlock(&ensoniq->reg_lock);
2112 }
2113 
2114 static int snd_ensoniq_midi_input_open(snd_rawmidi_substream_t * substream)
2115 {
2116 	ensoniq_t *ensoniq = substream->rmidi->private_data;
2117 
2118 	spin_lock_irq(&ensoniq->reg_lock);
2119 	ensoniq->uartm |= ES_MODE_INPUT;
2120 	ensoniq->midi_input = substream;
2121 	if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2122 		outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2123 		outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2124 		outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2125 	}
2126 	spin_unlock_irq(&ensoniq->reg_lock);
2127 	return 0;
2128 }
2129 
2130 static int snd_ensoniq_midi_input_close(snd_rawmidi_substream_t * substream)
2131 {
2132 	ensoniq_t *ensoniq = substream->rmidi->private_data;
2133 
2134 	spin_lock_irq(&ensoniq->reg_lock);
2135 	if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2136 		outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2137 		outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2138 	} else {
2139 		outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2140 	}
2141 	ensoniq->midi_input = NULL;
2142 	ensoniq->uartm &= ~ES_MODE_INPUT;
2143 	spin_unlock_irq(&ensoniq->reg_lock);
2144 	return 0;
2145 }
2146 
2147 static int snd_ensoniq_midi_output_open(snd_rawmidi_substream_t * substream)
2148 {
2149 	ensoniq_t *ensoniq = substream->rmidi->private_data;
2150 
2151 	spin_lock_irq(&ensoniq->reg_lock);
2152 	ensoniq->uartm |= ES_MODE_OUTPUT;
2153 	ensoniq->midi_output = substream;
2154 	if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2155 		outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2156 		outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2157 		outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2158 	}
2159 	spin_unlock_irq(&ensoniq->reg_lock);
2160 	return 0;
2161 }
2162 
2163 static int snd_ensoniq_midi_output_close(snd_rawmidi_substream_t * substream)
2164 {
2165 	ensoniq_t *ensoniq = substream->rmidi->private_data;
2166 
2167 	spin_lock_irq(&ensoniq->reg_lock);
2168 	if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2169 		outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2170 		outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2171 	} else {
2172 		outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2173 	}
2174 	ensoniq->midi_output = NULL;
2175 	ensoniq->uartm &= ~ES_MODE_OUTPUT;
2176 	spin_unlock_irq(&ensoniq->reg_lock);
2177 	return 0;
2178 }
2179 
2180 static void snd_ensoniq_midi_input_trigger(snd_rawmidi_substream_t * substream, int up)
2181 {
2182 	unsigned long flags;
2183 	ensoniq_t *ensoniq = substream->rmidi->private_data;
2184 	int idx;
2185 
2186 	spin_lock_irqsave(&ensoniq->reg_lock, flags);
2187 	if (up) {
2188 		if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2189 			/* empty input FIFO */
2190 			for (idx = 0; idx < 32; idx++)
2191 				inb(ES_REG(ensoniq, UART_DATA));
2192 			ensoniq->uartc |= ES_RXINTEN;
2193 			outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2194 		}
2195 	} else {
2196 		if (ensoniq->uartc & ES_RXINTEN) {
2197 			ensoniq->uartc &= ~ES_RXINTEN;
2198 			outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2199 		}
2200 	}
2201 	spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2202 }
2203 
2204 static void snd_ensoniq_midi_output_trigger(snd_rawmidi_substream_t * substream, int up)
2205 {
2206 	unsigned long flags;
2207 	ensoniq_t *ensoniq = substream->rmidi->private_data;
2208 	unsigned char byte;
2209 
2210 	spin_lock_irqsave(&ensoniq->reg_lock, flags);
2211 	if (up) {
2212 		if (ES_TXINTENI(ensoniq->uartc) == 0) {
2213 			ensoniq->uartc |= ES_TXINTENO(1);
2214 			/* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2215 			while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2216 			       (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2217 				if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2218 					ensoniq->uartc &= ~ES_TXINTENM;
2219 				} else {
2220 					outb(byte, ES_REG(ensoniq, UART_DATA));
2221 				}
2222 			}
2223 			outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2224 		}
2225 	} else {
2226 		if (ES_TXINTENI(ensoniq->uartc) == 1) {
2227 			ensoniq->uartc &= ~ES_TXINTENM;
2228 			outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2229 		}
2230 	}
2231 	spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2232 }
2233 
2234 static snd_rawmidi_ops_t snd_ensoniq_midi_output =
2235 {
2236 	.open =		snd_ensoniq_midi_output_open,
2237 	.close =	snd_ensoniq_midi_output_close,
2238 	.trigger =	snd_ensoniq_midi_output_trigger,
2239 };
2240 
2241 static snd_rawmidi_ops_t snd_ensoniq_midi_input =
2242 {
2243 	.open =		snd_ensoniq_midi_input_open,
2244 	.close =	snd_ensoniq_midi_input_close,
2245 	.trigger =	snd_ensoniq_midi_input_trigger,
2246 };
2247 
2248 static int __devinit snd_ensoniq_midi(ensoniq_t * ensoniq, int device, snd_rawmidi_t **rrawmidi)
2249 {
2250 	snd_rawmidi_t *rmidi;
2251 	int err;
2252 
2253 	if (rrawmidi)
2254 		*rrawmidi = NULL;
2255 	if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2256 		return err;
2257 #ifdef CHIP1370
2258 	strcpy(rmidi->name, "ES1370");
2259 #else
2260 	strcpy(rmidi->name, "ES1371");
2261 #endif
2262 	snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2263 	snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2264 	rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2265 	rmidi->private_data = ensoniq;
2266 	ensoniq->rmidi = rmidi;
2267 	if (rrawmidi)
2268 		*rrawmidi = rmidi;
2269 	return 0;
2270 }
2271 
2272 /*
2273  *  Interrupt handler
2274  */
2275 
2276 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2277 {
2278 	ensoniq_t *ensoniq = dev_id;
2279 	unsigned int status, sctrl;
2280 
2281 	if (ensoniq == NULL)
2282 		return IRQ_NONE;
2283 
2284 	status = inl(ES_REG(ensoniq, STATUS));
2285 	if (!(status & ES_INTR))
2286 		return IRQ_NONE;
2287 
2288 	spin_lock(&ensoniq->reg_lock);
2289 	sctrl = ensoniq->sctrl;
2290 	if (status & ES_DAC1)
2291 		sctrl &= ~ES_P1_INT_EN;
2292 	if (status & ES_DAC2)
2293 		sctrl &= ~ES_P2_INT_EN;
2294 	if (status & ES_ADC)
2295 		sctrl &= ~ES_R1_INT_EN;
2296 	outl(sctrl, ES_REG(ensoniq, SERIAL));
2297 	outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2298 	spin_unlock(&ensoniq->reg_lock);
2299 
2300 	if (status & ES_UART)
2301 		snd_ensoniq_midi_interrupt(ensoniq);
2302 	if ((status & ES_DAC2) && ensoniq->playback2_substream)
2303 		snd_pcm_period_elapsed(ensoniq->playback2_substream);
2304 	if ((status & ES_ADC) && ensoniq->capture_substream)
2305 		snd_pcm_period_elapsed(ensoniq->capture_substream);
2306 	if ((status & ES_DAC1) && ensoniq->playback1_substream)
2307 		snd_pcm_period_elapsed(ensoniq->playback1_substream);
2308 	return IRQ_HANDLED;
2309 }
2310 
2311 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2312 					const struct pci_device_id *pci_id)
2313 {
2314 	static int dev;
2315 	snd_card_t *card;
2316 	ensoniq_t *ensoniq;
2317 	int err, pcm_devs[2];
2318 
2319 	if (dev >= SNDRV_CARDS)
2320 		return -ENODEV;
2321 	if (!enable[dev]) {
2322 		dev++;
2323 		return -ENOENT;
2324 	}
2325 
2326 	card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2327 	if (card == NULL)
2328 		return -ENOMEM;
2329 
2330 	if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2331 		snd_card_free(card);
2332 		return err;
2333 	}
2334 
2335 	pcm_devs[0] = 0; pcm_devs[1] = 1;
2336 #ifdef CHIP1370
2337 	if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2338 		snd_card_free(card);
2339 		return err;
2340 	}
2341 #endif
2342 #ifdef CHIP1371
2343 	if ((err = snd_ensoniq_1371_mixer(ensoniq)) < 0) {
2344 		snd_card_free(card);
2345 		return err;
2346 	}
2347 #endif
2348 	if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2349 		snd_card_free(card);
2350 		return err;
2351 	}
2352 	if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2353 		snd_card_free(card);
2354 		return err;
2355 	}
2356 	if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2357 		snd_card_free(card);
2358 		return err;
2359 	}
2360 
2361 	snd_ensoniq_create_gameport(ensoniq, dev);
2362 
2363 	strcpy(card->driver, DRIVER_NAME);
2364 
2365 	strcpy(card->shortname, "Ensoniq AudioPCI");
2366 	sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2367 		card->shortname,
2368 		card->driver,
2369 		ensoniq->port,
2370 		ensoniq->irq);
2371 
2372 	if ((err = snd_card_register(card)) < 0) {
2373 		snd_card_free(card);
2374 		return err;
2375 	}
2376 
2377 	pci_set_drvdata(pci, card);
2378 	dev++;
2379 	return 0;
2380 }
2381 
2382 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2383 {
2384 	snd_card_free(pci_get_drvdata(pci));
2385 	pci_set_drvdata(pci, NULL);
2386 }
2387 
2388 static struct pci_driver driver = {
2389 	.name = DRIVER_NAME,
2390 	.owner = THIS_MODULE,
2391 	.id_table = snd_audiopci_ids,
2392 	.probe = snd_audiopci_probe,
2393 	.remove = __devexit_p(snd_audiopci_remove),
2394 };
2395 
2396 static int __init alsa_card_ens137x_init(void)
2397 {
2398 	return pci_register_driver(&driver);
2399 }
2400 
2401 static void __exit alsa_card_ens137x_exit(void)
2402 {
2403 	pci_unregister_driver(&driver);
2404 }
2405 
2406 module_init(alsa_card_ens137x_init)
2407 module_exit(alsa_card_ens137x_exit)
2408