1 /* 2 * Driver for Cirrus Logic CS4281 based PCI soundcard 3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>, 4 * 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22 #include <sound/driver.h> 23 #include <asm/io.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/init.h> 27 #include <linux/pci.h> 28 #include <linux/slab.h> 29 #include <linux/gameport.h> 30 #include <linux/moduleparam.h> 31 #include <sound/core.h> 32 #include <sound/control.h> 33 #include <sound/pcm.h> 34 #include <sound/rawmidi.h> 35 #include <sound/ac97_codec.h> 36 #include <sound/opl3.h> 37 #include <sound/initval.h> 38 39 40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); 41 MODULE_DESCRIPTION("Cirrus Logic CS4281"); 42 MODULE_LICENSE("GPL"); 43 MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}"); 44 45 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 46 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 47 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 48 static int dual_codec[SNDRV_CARDS]; /* dual codec */ 49 50 module_param_array(index, int, NULL, 0444); 51 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard."); 52 module_param_array(id, charp, NULL, 0444); 53 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard."); 54 module_param_array(enable, bool, NULL, 0444); 55 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard."); 56 module_param_array(dual_codec, bool, NULL, 0444); 57 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled)."); 58 59 /* 60 * 61 */ 62 63 #ifndef PCI_VENDOR_ID_CIRRUS 64 #define PCI_VENDOR_ID_CIRRUS 0x1013 65 #endif 66 #ifndef PCI_DEVICE_ID_CIRRUS_4281 67 #define PCI_DEVICE_ID_CIRRUS_4281 0x6005 68 #endif 69 70 /* 71 * Direct registers 72 */ 73 74 #define CS4281_BA0_SIZE 0x1000 75 #define CS4281_BA1_SIZE 0x10000 76 77 /* 78 * BA0 registers 79 */ 80 #define BA0_HISR 0x0000 /* Host Interrupt Status Register */ 81 #define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */ 82 #define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */ 83 #define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */ 84 #define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */ 85 #define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */ 86 #define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */ 87 #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */ 88 #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */ 89 #define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */ 90 #define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */ 91 #define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */ 92 #define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */ 93 94 #define BA0_HICR 0x0008 /* Host Interrupt Control Register */ 95 #define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */ 96 #define BA0_HICR_IEV (1<<0) /* INTENA Value */ 97 #define BA0_HICR_EOI (3<<0) /* End of Interrupt command */ 98 99 #define BA0_HIMR 0x000c /* Host Interrupt Mask Register */ 100 /* Use same contants as for BA0_HISR */ 101 102 #define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */ 103 104 #define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */ 105 #define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */ 106 #define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */ 107 #define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */ 108 109 #define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */ 110 #define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */ 111 #define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */ 112 #define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */ 113 #define BA0_HDSR_DRUN (1<<15) /* DMA Running */ 114 #define BA0_HDSR_RQ (1<<7) /* Pending Request */ 115 116 #define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */ 117 #define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */ 118 #define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */ 119 #define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */ 120 #define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */ 121 #define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */ 122 #define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */ 123 #define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */ 124 #define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */ 125 #define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */ 126 #define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */ 127 #define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */ 128 #define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */ 129 #define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */ 130 #define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */ 131 #define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */ 132 #define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */ 133 #define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */ 134 #define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */ 135 #define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */ 136 #define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */ 137 #define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */ 138 #define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */ 139 #define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */ 140 141 #define BA0_DMR_DMA (1<<29) /* Enable DMA mode */ 142 #define BA0_DMR_POLL (1<<28) /* Enable poll mode */ 143 #define BA0_DMR_TBC (1<<25) /* Transfer By Channel */ 144 #define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */ 145 #define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */ 146 #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */ 147 #define BA0_DMR_USIGN (1<<19) /* Unsigned */ 148 #define BA0_DMR_BEND (1<<18) /* Big Endian */ 149 #define BA0_DMR_MONO (1<<17) /* Mono */ 150 #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */ 151 #define BA0_DMR_TYPE_DEMAND (0<<6) 152 #define BA0_DMR_TYPE_SINGLE (1<<6) 153 #define BA0_DMR_TYPE_BLOCK (2<<6) 154 #define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */ 155 #define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */ 156 #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */ 157 #define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */ 158 #define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */ 159 #define BA0_DMR_TR_READ (2<<2) /* Read Transfer */ 160 161 #define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */ 162 #define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */ 163 #define BA0_DCR_MSK (1<<0) /* DMA Mask bit */ 164 165 #define BA0_FCR0 0x0180 /* FIFO Control 0 */ 166 #define BA0_FCR1 0x0184 /* FIFO Control 1 */ 167 #define BA0_FCR2 0x0188 /* FIFO Control 2 */ 168 #define BA0_FCR3 0x018c /* FIFO Control 3 */ 169 170 #define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */ 171 #define BA0_FCR_DACZ (1<<30) /* DAC Zero */ 172 #define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */ 173 #define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */ 174 #define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */ 175 #define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */ 176 #define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */ 177 178 #define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */ 179 #define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */ 180 #define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */ 181 #define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */ 182 183 #define BA0_FCHS 0x020c /* FIFO Channel Status */ 184 #define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */ 185 #define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */ 186 #define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */ 187 #define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */ 188 #define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */ 189 #define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */ 190 #define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */ 191 #define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */ 192 193 #define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */ 194 #define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */ 195 #define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */ 196 #define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */ 197 198 #define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */ 199 #define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */ 200 #define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */ 201 #define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */ 202 #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */ 203 #define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */ 204 #define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */ 205 #define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */ 206 207 #define BA0_PMCS 0x0344 /* Power Management Control/Status */ 208 #define BA0_CWPR 0x03e0 /* Configuration Write Protect */ 209 210 #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */ 211 #define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */ 212 213 #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */ 214 215 #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */ 216 #define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */ 217 #define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */ 218 #define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */ 219 #define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */ 220 #define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */ 221 #define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */ 222 #define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */ 223 #define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */ 224 #define BA0_SPMC_RSTN (1<<0) /* Reset Not! */ 225 226 #define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */ 227 #define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */ 228 #define BA0_IISR 0x03f4 /* ISA Interrupt Select */ 229 #define BA0_TMS 0x03f8 /* Test Register */ 230 #define BA0_SSVID 0x03fc /* Subsystem ID register */ 231 232 #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */ 233 #define BA0_CLKCR1_CLKON (1<<25) /* Read Only */ 234 #define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */ 235 #define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */ 236 #define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */ 237 #define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */ 238 #define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */ 239 240 #define BA0_FRR 0x0410 /* Feature Reporting Register */ 241 #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */ 242 243 #define BA0_SERMC 0x0420 /* Serial Port Master Control */ 244 #define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */ 245 #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */ 246 #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */ 247 #define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */ 248 #define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */ 249 #define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */ 250 #define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */ 251 #define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */ 252 #define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */ 253 #define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */ 254 #define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */ 255 #define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */ 256 257 #define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */ 258 #define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */ 259 #define BA0_SERC1_AC97 (1<<1) 260 #define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */ 261 262 #define BA0_SERC2 0x042c /* Serial Port Configuration 2 */ 263 #define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */ 264 #define BA0_SERC2_AC97 (1<<1) 265 #define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */ 266 267 #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */ 268 269 #define BA0_ACCTL 0x0460 /* AC'97 Control */ 270 #define BA0_ACCTL_TC (1<<6) /* Target Codec */ 271 #define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */ 272 #define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */ 273 #define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */ 274 #define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */ 275 276 #define BA0_ACSTS 0x0464 /* AC'97 Status */ 277 #define BA0_ACSTS_VSTS (1<<1) /* Valid Status */ 278 #define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */ 279 280 #define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */ 281 #define BA0_ACOSV_SLV(x) (1<<((x)-3)) 282 283 #define BA0_ACCAD 0x046c /* AC'97 Command Address */ 284 #define BA0_ACCDA 0x0470 /* AC'97 Command Data */ 285 286 #define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */ 287 #define BA0_ACISV_SLV(x) (1<<((x)-3)) 288 289 #define BA0_ACSAD 0x0478 /* AC'97 Status Address */ 290 #define BA0_ACSDA 0x047c /* AC'97 Status Data */ 291 #define BA0_JSPT 0x0480 /* Joystick poll/trigger */ 292 #define BA0_JSCTL 0x0484 /* Joystick control */ 293 #define BA0_JSC1 0x0488 /* Joystick control */ 294 #define BA0_JSC2 0x048c /* Joystick control */ 295 #define BA0_JSIO 0x04a0 296 297 #define BA0_MIDCR 0x0490 /* MIDI Control */ 298 #define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */ 299 #define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */ 300 #define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */ 301 #define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */ 302 #define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */ 303 #define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */ 304 305 #define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */ 306 307 #define BA0_MIDSR 0x0494 /* MIDI Status (ro) */ 308 #define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */ 309 #define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */ 310 #define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */ 311 #define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */ 312 313 #define BA0_MIDWP 0x0498 /* MIDI Write */ 314 #define BA0_MIDRP 0x049c /* MIDI Read (ro) */ 315 316 #define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */ 317 #define BA0_AODSD1_NDS(x) (1<<((x)-3)) 318 319 #define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */ 320 #define BA0_AODSD2_NDS(x) (1<<((x)-3)) 321 322 #define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */ 323 #define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */ 324 #define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */ 325 #define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */ 326 #define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */ 327 #define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */ 328 #define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */ 329 #define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */ 330 #define BA0_FMDP 0x0734 /* FM Data Port */ 331 #define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */ 332 #define BA0_B1DP 0x073c /* FM Bank 1 Data Port */ 333 334 #define BA0_SSPM 0x0740 /* Sound System Power Management */ 335 #define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */ 336 #define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */ 337 #define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */ 338 #define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */ 339 #define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */ 340 #define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */ 341 342 #define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */ 343 #define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */ 344 345 #define BA0_SSCR 0x074c /* Sound System Control Register */ 346 #define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */ 347 #define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */ 348 #define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */ 349 #define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */ 350 #define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */ 351 #define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */ 352 #define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */ 353 #define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */ 354 #define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */ 355 356 #define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */ 357 #define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */ 358 #define BA0_SRCSA 0x075c /* SRC Slot Assignments */ 359 #define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */ 360 #define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */ 361 #define BA0_PASR 0x0768 /* playback sample rate */ 362 #define BA0_CASR 0x076C /* capture sample rate */ 363 364 /* Source Slot Numbers - Playback */ 365 #define SRCSLOT_LEFT_PCM_PLAYBACK 0 366 #define SRCSLOT_RIGHT_PCM_PLAYBACK 1 367 #define SRCSLOT_PHONE_LINE_1_DAC 2 368 #define SRCSLOT_CENTER_PCM_PLAYBACK 3 369 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4 370 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5 371 #define SRCSLOT_LFE_PCM_PLAYBACK 6 372 #define SRCSLOT_PHONE_LINE_2_DAC 7 373 #define SRCSLOT_HEADSET_DAC 8 374 #define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */ 375 #define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */ 376 377 /* Source Slot Numbers - Capture */ 378 #define SRCSLOT_LEFT_PCM_RECORD 10 379 #define SRCSLOT_RIGHT_PCM_RECORD 11 380 #define SRCSLOT_PHONE_LINE_1_ADC 12 381 #define SRCSLOT_MIC_ADC 13 382 #define SRCSLOT_PHONE_LINE_2_ADC 17 383 #define SRCSLOT_HEADSET_ADC 18 384 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20 385 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21 386 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22 387 #define SRCSLOT_SECONDARY_MIC_ADC 23 388 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27 389 #define SRCSLOT_SECONDARY_HEADSET_ADC 28 390 391 /* Source Slot Numbers - Others */ 392 #define SRCSLOT_POWER_DOWN 31 393 394 /* MIDI modes */ 395 #define CS4281_MODE_OUTPUT (1<<0) 396 #define CS4281_MODE_INPUT (1<<1) 397 398 /* joystick bits */ 399 /* Bits for JSPT */ 400 #define JSPT_CAX 0x00000001 401 #define JSPT_CAY 0x00000002 402 #define JSPT_CBX 0x00000004 403 #define JSPT_CBY 0x00000008 404 #define JSPT_BA1 0x00000010 405 #define JSPT_BA2 0x00000020 406 #define JSPT_BB1 0x00000040 407 #define JSPT_BB2 0x00000080 408 409 /* Bits for JSCTL */ 410 #define JSCTL_SP_MASK 0x00000003 411 #define JSCTL_SP_SLOW 0x00000000 412 #define JSCTL_SP_MEDIUM_SLOW 0x00000001 413 #define JSCTL_SP_MEDIUM_FAST 0x00000002 414 #define JSCTL_SP_FAST 0x00000003 415 #define JSCTL_ARE 0x00000004 416 417 /* Data register pairs masks */ 418 #define JSC1_Y1V_MASK 0x0000FFFF 419 #define JSC1_X1V_MASK 0xFFFF0000 420 #define JSC1_Y1V_SHIFT 0 421 #define JSC1_X1V_SHIFT 16 422 #define JSC2_Y2V_MASK 0x0000FFFF 423 #define JSC2_X2V_MASK 0xFFFF0000 424 #define JSC2_Y2V_SHIFT 0 425 #define JSC2_X2V_SHIFT 16 426 427 /* JS GPIO */ 428 #define JSIO_DAX 0x00000001 429 #define JSIO_DAY 0x00000002 430 #define JSIO_DBX 0x00000004 431 #define JSIO_DBY 0x00000008 432 #define JSIO_AXOE 0x00000010 433 #define JSIO_AYOE 0x00000020 434 #define JSIO_BXOE 0x00000040 435 #define JSIO_BYOE 0x00000080 436 437 /* 438 * 439 */ 440 441 typedef struct snd_cs4281 cs4281_t; 442 typedef struct snd_cs4281_dma cs4281_dma_t; 443 444 struct snd_cs4281_dma { 445 snd_pcm_substream_t *substream; 446 unsigned int regDBA; /* offset to DBA register */ 447 unsigned int regDCA; /* offset to DCA register */ 448 unsigned int regDBC; /* offset to DBC register */ 449 unsigned int regDCC; /* offset to DCC register */ 450 unsigned int regDMR; /* offset to DMR register */ 451 unsigned int regDCR; /* offset to DCR register */ 452 unsigned int regHDSR; /* offset to HDSR register */ 453 unsigned int regFCR; /* offset to FCR register */ 454 unsigned int regFSIC; /* offset to FSIC register */ 455 unsigned int valDMR; /* DMA mode */ 456 unsigned int valDCR; /* DMA command */ 457 unsigned int valFCR; /* FIFO control */ 458 unsigned int fifo_offset; /* FIFO offset within BA1 */ 459 unsigned char left_slot; /* FIFO left slot */ 460 unsigned char right_slot; /* FIFO right slot */ 461 int frag; /* period number */ 462 }; 463 464 #define SUSPEND_REGISTERS 20 465 466 struct snd_cs4281 { 467 int irq; 468 469 void __iomem *ba0; /* virtual (accessible) address */ 470 void __iomem *ba1; /* virtual (accessible) address */ 471 unsigned long ba0_addr; 472 unsigned long ba1_addr; 473 474 int dual_codec; 475 476 ac97_bus_t *ac97_bus; 477 ac97_t *ac97; 478 ac97_t *ac97_secondary; 479 480 struct pci_dev *pci; 481 snd_card_t *card; 482 snd_pcm_t *pcm; 483 snd_rawmidi_t *rmidi; 484 snd_rawmidi_substream_t *midi_input; 485 snd_rawmidi_substream_t *midi_output; 486 487 cs4281_dma_t dma[4]; 488 489 unsigned char src_left_play_slot; 490 unsigned char src_right_play_slot; 491 unsigned char src_left_rec_slot; 492 unsigned char src_right_rec_slot; 493 494 unsigned int spurious_dhtc_irq; 495 unsigned int spurious_dtc_irq; 496 497 spinlock_t reg_lock; 498 unsigned int midcr; 499 unsigned int uartm; 500 501 struct gameport *gameport; 502 503 #ifdef CONFIG_PM 504 u32 suspend_regs[SUSPEND_REGISTERS]; 505 #endif 506 507 }; 508 509 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs); 510 511 static struct pci_device_id snd_cs4281_ids[] = { 512 { 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */ 513 { 0, } 514 }; 515 516 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids); 517 518 /* 519 * constants 520 */ 521 522 #define CS4281_FIFO_SIZE 32 523 524 /* 525 * common I/O routines 526 */ 527 528 static void snd_cs4281_delay(unsigned int delay) 529 { 530 if (delay > 999) { 531 unsigned long end_time; 532 delay = (delay * HZ) / 1000000; 533 if (delay < 1) 534 delay = 1; 535 end_time = jiffies + delay; 536 do { 537 set_current_state(TASK_UNINTERRUPTIBLE); 538 schedule_timeout(1); 539 } while (time_after_eq(end_time, jiffies)); 540 } else { 541 udelay(delay); 542 } 543 } 544 545 static inline void snd_cs4281_delay_long(void) 546 { 547 set_current_state(TASK_UNINTERRUPTIBLE); 548 schedule_timeout(1); 549 } 550 551 static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val) 552 { 553 writel(val, chip->ba0 + offset); 554 } 555 556 static inline unsigned int snd_cs4281_peekBA0(cs4281_t *chip, unsigned long offset) 557 { 558 return readl(chip->ba0 + offset); 559 } 560 561 static void snd_cs4281_ac97_write(ac97_t *ac97, 562 unsigned short reg, unsigned short val) 563 { 564 /* 565 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 566 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 567 * 3. Write ACCTL = Control Register = 460h for initiating the write 568 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h 569 * 5. if DCV not cleared, break and return error 570 */ 571 cs4281_t *chip = ac97->private_data; 572 int count; 573 574 /* 575 * Setup the AC97 control registers on the CS461x to send the 576 * appropriate command to the AC97 to perform the read. 577 * ACCAD = Command Address Register = 46Ch 578 * ACCDA = Command Data Register = 470h 579 * ACCTL = Control Register = 460h 580 * set DCV - will clear when process completed 581 * reset CRW - Write command 582 * set VFRM - valid frame enabled 583 * set ESYN - ASYNC generation enabled 584 * set RSTN - ARST# inactive, AC97 codec not reset 585 */ 586 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); 587 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val); 588 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM | 589 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0)); 590 for (count = 0; count < 2000; count++) { 591 /* 592 * First, we want to wait for a short time. 593 */ 594 udelay(10); 595 /* 596 * Now, check to see if the write has completed. 597 * ACCTL = 460h, DCV should be reset by now and 460h = 07h 598 */ 599 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) { 600 return; 601 } 602 } 603 snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val); 604 } 605 606 static unsigned short snd_cs4281_ac97_read(ac97_t *ac97, 607 unsigned short reg) 608 { 609 cs4281_t *chip = ac97->private_data; 610 int count; 611 unsigned short result; 612 // FIXME: volatile is necessary in the following due to a bug of 613 // some gcc versions 614 volatile int ac97_num = ((volatile ac97_t *)ac97)->num; 615 616 /* 617 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address 618 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 619 * 3. Write ACCTL = Control Register = 460h for initiating the write 620 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h 621 * 5. if DCV not cleared, break and return error 622 * 6. Read ACSTS = Status Register = 464h, check VSTS bit 623 */ 624 625 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); 626 627 /* 628 * Setup the AC97 control registers on the CS461x to send the 629 * appropriate command to the AC97 to perform the read. 630 * ACCAD = Command Address Register = 46Ch 631 * ACCDA = Command Data Register = 470h 632 * ACCTL = Control Register = 460h 633 * set DCV - will clear when process completed 634 * set CRW - Read command 635 * set VFRM - valid frame enabled 636 * set ESYN - ASYNC generation enabled 637 * set RSTN - ARST# inactive, AC97 codec not reset 638 */ 639 640 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg); 641 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0); 642 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW | 643 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN | 644 (ac97_num ? BA0_ACCTL_TC : 0)); 645 646 647 /* 648 * Wait for the read to occur. 649 */ 650 for (count = 0; count < 500; count++) { 651 /* 652 * First, we want to wait for a short time. 653 */ 654 udelay(10); 655 /* 656 * Now, check to see if the read has completed. 657 * ACCTL = 460h, DCV should be reset by now and 460h = 17h 658 */ 659 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) 660 goto __ok1; 661 } 662 663 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg); 664 result = 0xffff; 665 goto __end; 666 667 __ok1: 668 /* 669 * Wait for the valid status bit to go active. 670 */ 671 for (count = 0; count < 100; count++) { 672 /* 673 * Read the AC97 status register. 674 * ACSTS = Status Register = 464h 675 * VSTS - Valid Status 676 */ 677 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS) 678 goto __ok2; 679 udelay(10); 680 } 681 682 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg); 683 result = 0xffff; 684 goto __end; 685 686 __ok2: 687 /* 688 * Read the data returned from the AC97 register. 689 * ACSDA = Status Data Register = 474h 690 */ 691 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA); 692 693 __end: 694 return result; 695 } 696 697 /* 698 * PCM part 699 */ 700 701 static int snd_cs4281_trigger(snd_pcm_substream_t *substream, int cmd) 702 { 703 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data; 704 cs4281_t *chip = snd_pcm_substream_chip(substream); 705 706 spin_lock(&chip->reg_lock); 707 switch (cmd) { 708 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 709 dma->valDCR |= BA0_DCR_MSK; 710 dma->valFCR |= BA0_FCR_FEN; 711 break; 712 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 713 dma->valDCR &= ~BA0_DCR_MSK; 714 dma->valFCR &= ~BA0_FCR_FEN; 715 break; 716 case SNDRV_PCM_TRIGGER_START: 717 case SNDRV_PCM_TRIGGER_RESUME: 718 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA); 719 dma->valDMR |= BA0_DMR_DMA; 720 dma->valDCR &= ~BA0_DCR_MSK; 721 dma->valFCR |= BA0_FCR_FEN; 722 break; 723 case SNDRV_PCM_TRIGGER_STOP: 724 case SNDRV_PCM_TRIGGER_SUSPEND: 725 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL); 726 dma->valDCR |= BA0_DCR_MSK; 727 dma->valFCR &= ~BA0_FCR_FEN; 728 /* Leave wave playback FIFO enabled for FM */ 729 if (dma->regFCR != BA0_FCR0) 730 dma->valFCR &= ~BA0_FCR_FEN; 731 break; 732 default: 733 spin_unlock(&chip->reg_lock); 734 return -EINVAL; 735 } 736 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR); 737 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR); 738 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR); 739 spin_unlock(&chip->reg_lock); 740 return 0; 741 } 742 743 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate) 744 { 745 unsigned int val = ~0; 746 747 if (real_rate) 748 *real_rate = rate; 749 /* special "hardcoded" rates */ 750 switch (rate) { 751 case 8000: return 5; 752 case 11025: return 4; 753 case 16000: return 3; 754 case 22050: return 2; 755 case 44100: return 1; 756 case 48000: return 0; 757 default: 758 goto __variable; 759 } 760 __variable: 761 val = 1536000 / rate; 762 if (real_rate) 763 *real_rate = 1536000 / val; 764 return val; 765 } 766 767 static void snd_cs4281_mode(cs4281_t *chip, cs4281_dma_t *dma, snd_pcm_runtime_t *runtime, int capture, int src) 768 { 769 int rec_mono; 770 771 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO | 772 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ); 773 if (runtime->channels == 1) 774 dma->valDMR |= BA0_DMR_MONO; 775 if (snd_pcm_format_unsigned(runtime->format) > 0) 776 dma->valDMR |= BA0_DMR_USIGN; 777 if (snd_pcm_format_big_endian(runtime->format) > 0) 778 dma->valDMR |= BA0_DMR_BEND; 779 switch (snd_pcm_format_width(runtime->format)) { 780 case 8: dma->valDMR |= BA0_DMR_SIZE8; 781 if (runtime->channels == 1) 782 dma->valDMR |= BA0_DMR_SWAPC; 783 break; 784 case 32: dma->valDMR |= BA0_DMR_SIZE20; break; 785 } 786 dma->frag = 0; /* for workaround */ 787 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK; 788 if (runtime->buffer_size != runtime->period_size) 789 dma->valDCR |= BA0_DCR_HTCIE; 790 /* Initialize DMA */ 791 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr); 792 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1); 793 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO; 794 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | 795 (chip->src_right_play_slot << 8) | 796 (chip->src_left_rec_slot << 16) | 797 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24)); 798 if (!src) 799 goto __skip_src; 800 if (!capture) { 801 if (dma->left_slot == chip->src_left_play_slot) { 802 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); 803 snd_assert(dma->right_slot == chip->src_right_play_slot, ); 804 snd_cs4281_pokeBA0(chip, BA0_DACSR, val); 805 } 806 } else { 807 if (dma->left_slot == chip->src_left_rec_slot) { 808 unsigned int val = snd_cs4281_rate(runtime->rate, NULL); 809 snd_assert(dma->right_slot == chip->src_right_rec_slot, ); 810 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val); 811 } 812 } 813 __skip_src: 814 /* Deactivate wave playback FIFO before changing slot assignments */ 815 if (dma->regFCR == BA0_FCR0) 816 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN); 817 /* Initialize FIFO */ 818 dma->valFCR = BA0_FCR_LS(dma->left_slot) | 819 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) | 820 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 821 BA0_FCR_OF(dma->fifo_offset); 822 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0)); 823 /* Activate FIFO again for FM playback */ 824 if (dma->regFCR == BA0_FCR0) 825 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN); 826 /* Clear FIFO Status and Interrupt Control Register */ 827 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0); 828 } 829 830 static int snd_cs4281_hw_params(snd_pcm_substream_t * substream, 831 snd_pcm_hw_params_t * hw_params) 832 { 833 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 834 } 835 836 static int snd_cs4281_hw_free(snd_pcm_substream_t * substream) 837 { 838 return snd_pcm_lib_free_pages(substream); 839 } 840 841 static int snd_cs4281_playback_prepare(snd_pcm_substream_t * substream) 842 { 843 snd_pcm_runtime_t *runtime = substream->runtime; 844 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data; 845 cs4281_t *chip = snd_pcm_substream_chip(substream); 846 847 spin_lock_irq(&chip->reg_lock); 848 snd_cs4281_mode(chip, dma, runtime, 0, 1); 849 spin_unlock_irq(&chip->reg_lock); 850 return 0; 851 } 852 853 static int snd_cs4281_capture_prepare(snd_pcm_substream_t * substream) 854 { 855 snd_pcm_runtime_t *runtime = substream->runtime; 856 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data; 857 cs4281_t *chip = snd_pcm_substream_chip(substream); 858 859 spin_lock_irq(&chip->reg_lock); 860 snd_cs4281_mode(chip, dma, runtime, 1, 1); 861 spin_unlock_irq(&chip->reg_lock); 862 return 0; 863 } 864 865 static snd_pcm_uframes_t snd_cs4281_pointer(snd_pcm_substream_t * substream) 866 { 867 snd_pcm_runtime_t *runtime = substream->runtime; 868 cs4281_dma_t *dma = (cs4281_dma_t *)runtime->private_data; 869 cs4281_t *chip = snd_pcm_substream_chip(substream); 870 871 // printk("DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n", snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size, jiffies); 872 return runtime->buffer_size - 873 snd_cs4281_peekBA0(chip, dma->regDCC) - 1; 874 } 875 876 static snd_pcm_hardware_t snd_cs4281_playback = 877 { 878 .info = (SNDRV_PCM_INFO_MMAP | 879 SNDRV_PCM_INFO_INTERLEAVED | 880 SNDRV_PCM_INFO_MMAP_VALID | 881 SNDRV_PCM_INFO_PAUSE | 882 SNDRV_PCM_INFO_RESUME | 883 SNDRV_PCM_INFO_SYNC_START), 884 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | 885 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | 886 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | 887 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | 888 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, 889 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 890 .rate_min = 4000, 891 .rate_max = 48000, 892 .channels_min = 1, 893 .channels_max = 2, 894 .buffer_bytes_max = (512*1024), 895 .period_bytes_min = 64, 896 .period_bytes_max = (512*1024), 897 .periods_min = 1, 898 .periods_max = 2, 899 .fifo_size = CS4281_FIFO_SIZE, 900 }; 901 902 static snd_pcm_hardware_t snd_cs4281_capture = 903 { 904 .info = (SNDRV_PCM_INFO_MMAP | 905 SNDRV_PCM_INFO_INTERLEAVED | 906 SNDRV_PCM_INFO_MMAP_VALID | 907 SNDRV_PCM_INFO_PAUSE | 908 SNDRV_PCM_INFO_RESUME | 909 SNDRV_PCM_INFO_SYNC_START), 910 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 | 911 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE | 912 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE | 913 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE | 914 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE, 915 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 916 .rate_min = 4000, 917 .rate_max = 48000, 918 .channels_min = 1, 919 .channels_max = 2, 920 .buffer_bytes_max = (512*1024), 921 .period_bytes_min = 64, 922 .period_bytes_max = (512*1024), 923 .periods_min = 1, 924 .periods_max = 2, 925 .fifo_size = CS4281_FIFO_SIZE, 926 }; 927 928 static int snd_cs4281_playback_open(snd_pcm_substream_t * substream) 929 { 930 cs4281_t *chip = snd_pcm_substream_chip(substream); 931 snd_pcm_runtime_t *runtime = substream->runtime; 932 cs4281_dma_t *dma; 933 934 dma = &chip->dma[0]; 935 dma->substream = substream; 936 dma->left_slot = 0; 937 dma->right_slot = 1; 938 runtime->private_data = dma; 939 runtime->hw = snd_cs4281_playback; 940 snd_pcm_set_sync(substream); 941 /* should be detected from the AC'97 layer, but it seems 942 that although CS4297A rev B reports 18-bit ADC resolution, 943 samples are 20-bit */ 944 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 945 return 0; 946 } 947 948 static int snd_cs4281_capture_open(snd_pcm_substream_t * substream) 949 { 950 cs4281_t *chip = snd_pcm_substream_chip(substream); 951 snd_pcm_runtime_t *runtime = substream->runtime; 952 cs4281_dma_t *dma; 953 954 dma = &chip->dma[1]; 955 dma->substream = substream; 956 dma->left_slot = 10; 957 dma->right_slot = 11; 958 runtime->private_data = dma; 959 runtime->hw = snd_cs4281_capture; 960 snd_pcm_set_sync(substream); 961 /* should be detected from the AC'97 layer, but it seems 962 that although CS4297A rev B reports 18-bit ADC resolution, 963 samples are 20-bit */ 964 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 965 return 0; 966 } 967 968 static int snd_cs4281_playback_close(snd_pcm_substream_t * substream) 969 { 970 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data; 971 972 dma->substream = NULL; 973 return 0; 974 } 975 976 static int snd_cs4281_capture_close(snd_pcm_substream_t * substream) 977 { 978 cs4281_dma_t *dma = (cs4281_dma_t *)substream->runtime->private_data; 979 980 dma->substream = NULL; 981 return 0; 982 } 983 984 static snd_pcm_ops_t snd_cs4281_playback_ops = { 985 .open = snd_cs4281_playback_open, 986 .close = snd_cs4281_playback_close, 987 .ioctl = snd_pcm_lib_ioctl, 988 .hw_params = snd_cs4281_hw_params, 989 .hw_free = snd_cs4281_hw_free, 990 .prepare = snd_cs4281_playback_prepare, 991 .trigger = snd_cs4281_trigger, 992 .pointer = snd_cs4281_pointer, 993 }; 994 995 static snd_pcm_ops_t snd_cs4281_capture_ops = { 996 .open = snd_cs4281_capture_open, 997 .close = snd_cs4281_capture_close, 998 .ioctl = snd_pcm_lib_ioctl, 999 .hw_params = snd_cs4281_hw_params, 1000 .hw_free = snd_cs4281_hw_free, 1001 .prepare = snd_cs4281_capture_prepare, 1002 .trigger = snd_cs4281_trigger, 1003 .pointer = snd_cs4281_pointer, 1004 }; 1005 1006 static void snd_cs4281_pcm_free(snd_pcm_t *pcm) 1007 { 1008 cs4281_t *chip = pcm->private_data; 1009 chip->pcm = NULL; 1010 snd_pcm_lib_preallocate_free_for_all(pcm); 1011 } 1012 1013 static int __devinit snd_cs4281_pcm(cs4281_t * chip, int device, snd_pcm_t ** rpcm) 1014 { 1015 snd_pcm_t *pcm; 1016 int err; 1017 1018 if (rpcm) 1019 *rpcm = NULL; 1020 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm); 1021 if (err < 0) 1022 return err; 1023 1024 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops); 1025 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops); 1026 1027 pcm->private_data = chip; 1028 pcm->private_free = snd_cs4281_pcm_free; 1029 pcm->info_flags = 0; 1030 strcpy(pcm->name, "CS4281"); 1031 chip->pcm = pcm; 1032 1033 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1034 snd_dma_pci_data(chip->pci), 64*1024, 512*1024); 1035 1036 if (rpcm) 1037 *rpcm = pcm; 1038 return 0; 1039 } 1040 1041 /* 1042 * Mixer section 1043 */ 1044 1045 #define CS_VOL_MASK 0x1f 1046 1047 static int snd_cs4281_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo) 1048 { 1049 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1050 uinfo->count = 2; 1051 uinfo->value.integer.min = 0; 1052 uinfo->value.integer.max = CS_VOL_MASK; 1053 return 0; 1054 } 1055 1056 static int snd_cs4281_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1057 { 1058 cs4281_t *chip = snd_kcontrol_chip(kcontrol); 1059 int regL = (kcontrol->private_value >> 16) & 0xffff; 1060 int regR = kcontrol->private_value & 0xffff; 1061 int volL, volR; 1062 1063 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); 1064 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); 1065 1066 ucontrol->value.integer.value[0] = volL; 1067 ucontrol->value.integer.value[1] = volR; 1068 return 0; 1069 } 1070 1071 static int snd_cs4281_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1072 { 1073 cs4281_t *chip = snd_kcontrol_chip(kcontrol); 1074 int change = 0; 1075 int regL = (kcontrol->private_value >> 16) & 0xffff; 1076 int regR = kcontrol->private_value & 0xffff; 1077 int volL, volR; 1078 1079 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK); 1080 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK); 1081 1082 if (ucontrol->value.integer.value[0] != volL) { 1083 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK); 1084 snd_cs4281_pokeBA0(chip, regL, volL); 1085 change = 1; 1086 } 1087 if (ucontrol->value.integer.value[0] != volL) { 1088 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK); 1089 snd_cs4281_pokeBA0(chip, regR, volR); 1090 change = 1; 1091 } 1092 return change; 1093 } 1094 1095 static snd_kcontrol_new_t snd_cs4281_fm_vol = 1096 { 1097 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1098 .name = "Synth Playback Volume", 1099 .info = snd_cs4281_info_volume, 1100 .get = snd_cs4281_get_volume, 1101 .put = snd_cs4281_put_volume, 1102 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC), 1103 }; 1104 1105 static snd_kcontrol_new_t snd_cs4281_pcm_vol = 1106 { 1107 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1108 .name = "PCM Stream Playback Volume", 1109 .info = snd_cs4281_info_volume, 1110 .get = snd_cs4281_get_volume, 1111 .put = snd_cs4281_put_volume, 1112 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC), 1113 }; 1114 1115 static void snd_cs4281_mixer_free_ac97_bus(ac97_bus_t *bus) 1116 { 1117 cs4281_t *chip = bus->private_data; 1118 chip->ac97_bus = NULL; 1119 } 1120 1121 static void snd_cs4281_mixer_free_ac97(ac97_t *ac97) 1122 { 1123 cs4281_t *chip = ac97->private_data; 1124 if (ac97->num) 1125 chip->ac97_secondary = NULL; 1126 else 1127 chip->ac97 = NULL; 1128 } 1129 1130 static int __devinit snd_cs4281_mixer(cs4281_t * chip) 1131 { 1132 snd_card_t *card = chip->card; 1133 ac97_template_t ac97; 1134 int err; 1135 static ac97_bus_ops_t ops = { 1136 .write = snd_cs4281_ac97_write, 1137 .read = snd_cs4281_ac97_read, 1138 }; 1139 1140 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0) 1141 return err; 1142 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus; 1143 1144 memset(&ac97, 0, sizeof(ac97)); 1145 ac97.private_data = chip; 1146 ac97.private_free = snd_cs4281_mixer_free_ac97; 1147 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0) 1148 return err; 1149 if (chip->dual_codec) { 1150 ac97.num = 1; 1151 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0) 1152 return err; 1153 } 1154 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0) 1155 return err; 1156 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0) 1157 return err; 1158 return 0; 1159 } 1160 1161 1162 /* 1163 * proc interface 1164 */ 1165 1166 static void snd_cs4281_proc_read(snd_info_entry_t *entry, 1167 snd_info_buffer_t * buffer) 1168 { 1169 cs4281_t *chip = entry->private_data; 1170 1171 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n"); 1172 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq); 1173 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq); 1174 } 1175 1176 static long snd_cs4281_BA0_read(snd_info_entry_t *entry, void *file_private_data, 1177 struct file *file, char __user *buf, 1178 unsigned long count, unsigned long pos) 1179 { 1180 long size; 1181 cs4281_t *chip = entry->private_data; 1182 1183 size = count; 1184 if (pos + size > CS4281_BA0_SIZE) 1185 size = (long)CS4281_BA0_SIZE - pos; 1186 if (size > 0) { 1187 if (copy_to_user_fromio(buf, chip->ba0 + pos, size)) 1188 return -EFAULT; 1189 } 1190 return size; 1191 } 1192 1193 static long snd_cs4281_BA1_read(snd_info_entry_t *entry, void *file_private_data, 1194 struct file *file, char __user *buf, 1195 unsigned long count, unsigned long pos) 1196 { 1197 long size; 1198 cs4281_t *chip = entry->private_data; 1199 1200 size = count; 1201 if (pos + size > CS4281_BA1_SIZE) 1202 size = (long)CS4281_BA1_SIZE - pos; 1203 if (size > 0) { 1204 if (copy_to_user_fromio(buf, chip->ba1 + pos, size)) 1205 return -EFAULT; 1206 } 1207 return size; 1208 } 1209 1210 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = { 1211 .read = snd_cs4281_BA0_read, 1212 }; 1213 1214 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = { 1215 .read = snd_cs4281_BA1_read, 1216 }; 1217 1218 static void __devinit snd_cs4281_proc_init(cs4281_t * chip) 1219 { 1220 snd_info_entry_t *entry; 1221 1222 if (! snd_card_proc_new(chip->card, "cs4281", &entry)) 1223 snd_info_set_text_ops(entry, chip, 1024, snd_cs4281_proc_read); 1224 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) { 1225 entry->content = SNDRV_INFO_CONTENT_DATA; 1226 entry->private_data = chip; 1227 entry->c.ops = &snd_cs4281_proc_ops_BA0; 1228 entry->size = CS4281_BA0_SIZE; 1229 } 1230 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) { 1231 entry->content = SNDRV_INFO_CONTENT_DATA; 1232 entry->private_data = chip; 1233 entry->c.ops = &snd_cs4281_proc_ops_BA1; 1234 entry->size = CS4281_BA1_SIZE; 1235 } 1236 } 1237 1238 /* 1239 * joystick support 1240 */ 1241 1242 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 1243 1244 static void snd_cs4281_gameport_trigger(struct gameport *gameport) 1245 { 1246 cs4281_t *chip = gameport_get_port_data(gameport); 1247 1248 snd_assert(chip, return); 1249 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff); 1250 } 1251 1252 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport) 1253 { 1254 cs4281_t *chip = gameport_get_port_data(gameport); 1255 1256 snd_assert(chip, return 0); 1257 return snd_cs4281_peekBA0(chip, BA0_JSPT); 1258 } 1259 1260 #ifdef COOKED_MODE 1261 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons) 1262 { 1263 cs4281_t *chip = gameport_get_port_data(gameport); 1264 unsigned js1, js2, jst; 1265 1266 snd_assert(chip, return 0); 1267 1268 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1); 1269 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2); 1270 jst = snd_cs4281_peekBA0(chip, BA0_JSPT); 1271 1272 *buttons = (~jst >> 4) & 0x0F; 1273 1274 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF; 1275 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF; 1276 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF; 1277 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF; 1278 1279 for (jst = 0; jst < 4; ++jst) 1280 if (axes[jst] == 0xFFFF) axes[jst] = -1; 1281 return 0; 1282 } 1283 #else 1284 #define snd_cs4281_gameport_cooked_read NULL 1285 #endif 1286 1287 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode) 1288 { 1289 switch (mode) { 1290 #ifdef COOKED_MODE 1291 case GAMEPORT_MODE_COOKED: 1292 return 0; 1293 #endif 1294 case GAMEPORT_MODE_RAW: 1295 return 0; 1296 default: 1297 return -1; 1298 } 1299 return 0; 1300 } 1301 1302 static int __devinit snd_cs4281_create_gameport(cs4281_t *chip) 1303 { 1304 struct gameport *gp; 1305 1306 chip->gameport = gp = gameport_allocate_port(); 1307 if (!gp) { 1308 printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n"); 1309 return -ENOMEM; 1310 } 1311 1312 gameport_set_name(gp, "CS4281 Gameport"); 1313 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 1314 gameport_set_dev_parent(gp, &chip->pci->dev); 1315 gp->open = snd_cs4281_gameport_open; 1316 gp->read = snd_cs4281_gameport_read; 1317 gp->trigger = snd_cs4281_gameport_trigger; 1318 gp->cooked_read = snd_cs4281_gameport_cooked_read; 1319 gameport_set_port_data(gp, chip); 1320 1321 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ? 1322 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW); 1323 1324 gameport_register_port(gp); 1325 1326 return 0; 1327 } 1328 1329 static void snd_cs4281_free_gameport(cs4281_t *chip) 1330 { 1331 if (chip->gameport) { 1332 gameport_unregister_port(chip->gameport); 1333 chip->gameport = NULL; 1334 } 1335 } 1336 #else 1337 static inline int snd_cs4281_create_gameport(cs4281_t *chip) { return -ENOSYS; } 1338 static inline void snd_cs4281_free_gameport(cs4281_t *chip) { } 1339 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */ 1340 1341 static int snd_cs4281_free(cs4281_t *chip) 1342 { 1343 snd_cs4281_free_gameport(chip); 1344 1345 if (chip->irq >= 0) 1346 synchronize_irq(chip->irq); 1347 1348 /* Mask interrupts */ 1349 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff); 1350 /* Stop the DLL Clock logic. */ 1351 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 1352 /* Sound System Power Management - Turn Everything OFF */ 1353 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); 1354 /* PCI interface - D3 state */ 1355 pci_set_power_state(chip->pci, 3); 1356 1357 if (chip->irq >= 0) 1358 free_irq(chip->irq, (void *)chip); 1359 if (chip->ba0) 1360 iounmap(chip->ba0); 1361 if (chip->ba1) 1362 iounmap(chip->ba1); 1363 pci_release_regions(chip->pci); 1364 pci_disable_device(chip->pci); 1365 1366 kfree(chip); 1367 return 0; 1368 } 1369 1370 static int snd_cs4281_dev_free(snd_device_t *device) 1371 { 1372 cs4281_t *chip = device->device_data; 1373 return snd_cs4281_free(chip); 1374 } 1375 1376 static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */ 1377 #ifdef CONFIG_PM 1378 static int cs4281_suspend(snd_card_t *card, pm_message_t state); 1379 static int cs4281_resume(snd_card_t *card); 1380 #endif 1381 1382 static int __devinit snd_cs4281_create(snd_card_t * card, 1383 struct pci_dev *pci, 1384 cs4281_t ** rchip, 1385 int dual_codec) 1386 { 1387 cs4281_t *chip; 1388 unsigned int tmp; 1389 int err; 1390 static snd_device_ops_t ops = { 1391 .dev_free = snd_cs4281_dev_free, 1392 }; 1393 1394 *rchip = NULL; 1395 if ((err = pci_enable_device(pci)) < 0) 1396 return err; 1397 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL); 1398 if (chip == NULL) { 1399 pci_disable_device(pci); 1400 return -ENOMEM; 1401 } 1402 spin_lock_init(&chip->reg_lock); 1403 chip->card = card; 1404 chip->pci = pci; 1405 chip->irq = -1; 1406 pci_set_master(pci); 1407 if (dual_codec < 0 || dual_codec > 3) { 1408 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec); 1409 dual_codec = 0; 1410 } 1411 chip->dual_codec = dual_codec; 1412 1413 if ((err = pci_request_regions(pci, "CS4281")) < 0) { 1414 kfree(chip); 1415 pci_disable_device(pci); 1416 return err; 1417 } 1418 chip->ba0_addr = pci_resource_start(pci, 0); 1419 chip->ba1_addr = pci_resource_start(pci, 1); 1420 1421 if (request_irq(pci->irq, snd_cs4281_interrupt, SA_INTERRUPT|SA_SHIRQ, "CS4281", (void *)chip)) { 1422 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1423 snd_cs4281_free(chip); 1424 return -ENOMEM; 1425 } 1426 chip->irq = pci->irq; 1427 1428 chip->ba0 = ioremap_nocache(chip->ba0_addr, pci_resource_len(pci, 0)); 1429 chip->ba1 = ioremap_nocache(chip->ba1_addr, pci_resource_len(pci, 1)); 1430 if (!chip->ba0 || !chip->ba1) { 1431 snd_cs4281_free(chip); 1432 return -ENOMEM; 1433 } 1434 1435 tmp = snd_cs4281_chip_init(chip); 1436 if (tmp) { 1437 snd_cs4281_free(chip); 1438 return tmp; 1439 } 1440 1441 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1442 snd_cs4281_free(chip); 1443 return err; 1444 } 1445 1446 snd_cs4281_proc_init(chip); 1447 1448 snd_card_set_pm_callback(card, cs4281_suspend, cs4281_resume, chip); 1449 1450 snd_card_set_dev(card, &pci->dev); 1451 1452 *rchip = chip; 1453 return 0; 1454 } 1455 1456 static int snd_cs4281_chip_init(cs4281_t *chip) 1457 { 1458 unsigned int tmp; 1459 int timeout; 1460 int retry_count = 2; 1461 1462 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */ 1463 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC); 1464 if (tmp & BA0_EPPMC_FPDN) 1465 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN); 1466 1467 __retry: 1468 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); 1469 if (tmp != BA0_CFLR_DEFAULT) { 1470 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT); 1471 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR); 1472 if (tmp != BA0_CFLR_DEFAULT) { 1473 snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp); 1474 return -EIO; 1475 } 1476 } 1477 1478 /* Set the 'Configuration Write Protect' register 1479 * to 4281h. Allows vendor-defined configuration 1480 * space between 0e4h and 0ffh to be written. */ 1481 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281); 1482 1483 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) { 1484 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp); 1485 return -EIO; 1486 } 1487 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) { 1488 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp); 1489 return -EIO; 1490 } 1491 1492 /* Sound System Power Management */ 1493 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN | 1494 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN | 1495 BA0_SSPM_ACLEN | BA0_SSPM_FMEN); 1496 1497 /* Serial Port Power Management */ 1498 /* Blast the clock control register to zero so that the 1499 * PLL starts out in a known state, and blast the master serial 1500 * port control register to zero so that the serial ports also 1501 * start out in a known state. */ 1502 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 1503 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); 1504 1505 /* Make ESYN go to zero to turn off 1506 * the Sync pulse on the AC97 link. */ 1507 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0); 1508 udelay(50); 1509 1510 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97 1511 * spec) and then drive it high. This is done for non AC97 modes since 1512 * there might be logic external to the CS4281 that uses the ARST# line 1513 * for a reset. */ 1514 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); 1515 udelay(50); 1516 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN); 1517 snd_cs4281_delay(50000); 1518 1519 if (chip->dual_codec) 1520 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E); 1521 1522 /* 1523 * Set the serial port timing configuration. 1524 */ 1525 snd_cs4281_pokeBA0(chip, BA0_SERMC, 1526 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) | 1527 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE); 1528 1529 /* 1530 * Start the DLL Clock logic. 1531 */ 1532 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP); 1533 snd_cs4281_delay(50000); 1534 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP); 1535 1536 /* 1537 * Wait for the DLL ready signal from the clock logic. 1538 */ 1539 timeout = HZ; 1540 do { 1541 /* 1542 * Read the AC97 status register to see if we've seen a CODEC 1543 * signal from the AC97 codec. 1544 */ 1545 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY) 1546 goto __ok0; 1547 snd_cs4281_delay_long(); 1548 } while (timeout-- > 0); 1549 1550 snd_printk(KERN_ERR "DLLRDY not seen\n"); 1551 return -EIO; 1552 1553 __ok0: 1554 1555 /* 1556 * The first thing we do here is to enable sync generation. As soon 1557 * as we start receiving bit clock, we'll start producing the SYNC 1558 * signal. 1559 */ 1560 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN); 1561 1562 /* 1563 * Wait for the codec ready signal from the AC97 codec. 1564 */ 1565 timeout = HZ; 1566 do { 1567 /* 1568 * Read the AC97 status register to see if we've seen a CODEC 1569 * signal from the AC97 codec. 1570 */ 1571 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY) 1572 goto __ok1; 1573 snd_cs4281_delay_long(); 1574 } while (timeout-- > 0); 1575 1576 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS)); 1577 return -EIO; 1578 1579 __ok1: 1580 if (chip->dual_codec) { 1581 timeout = HZ; 1582 do { 1583 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY) 1584 goto __codec2_ok; 1585 snd_cs4281_delay_long(); 1586 } while (timeout-- > 0); 1587 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n"); 1588 chip->dual_codec = 0; 1589 __codec2_ok: ; 1590 } 1591 1592 /* 1593 * Assert the valid frame signal so that we can start sending commands 1594 * to the AC97 codec. 1595 */ 1596 1597 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN); 1598 1599 /* 1600 * Wait until we've sampled input slots 3 and 4 as valid, meaning that 1601 * the codec is pumping ADC data across the AC-link. 1602 */ 1603 1604 timeout = HZ; 1605 do { 1606 /* 1607 * Read the input slot valid register and see if input slots 3 1608 * 4 are valid yet. 1609 */ 1610 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) 1611 goto __ok2; 1612 snd_cs4281_delay_long(); 1613 } while (timeout-- > 0); 1614 1615 if (--retry_count > 0) 1616 goto __retry; 1617 snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n"); 1618 return -EIO; 1619 1620 __ok2: 1621 1622 /* 1623 * Now, assert valid frame and the slot 3 and 4 valid bits. This will 1624 * commense the transfer of digital audio data to the AC97 codec. 1625 */ 1626 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4)); 1627 1628 /* 1629 * Initialize DMA structures 1630 */ 1631 for (tmp = 0; tmp < 4; tmp++) { 1632 cs4281_dma_t *dma = &chip->dma[tmp]; 1633 dma->regDBA = BA0_DBA0 + (tmp * 0x10); 1634 dma->regDCA = BA0_DCA0 + (tmp * 0x10); 1635 dma->regDBC = BA0_DBC0 + (tmp * 0x10); 1636 dma->regDCC = BA0_DCC0 + (tmp * 0x10); 1637 dma->regDMR = BA0_DMR0 + (tmp * 8); 1638 dma->regDCR = BA0_DCR0 + (tmp * 8); 1639 dma->regHDSR = BA0_HDSR0 + (tmp * 4); 1640 dma->regFCR = BA0_FCR0 + (tmp * 4); 1641 dma->regFSIC = BA0_FSIC0 + (tmp * 4); 1642 dma->fifo_offset = tmp * CS4281_FIFO_SIZE; 1643 snd_cs4281_pokeBA0(chip, dma->regFCR, 1644 BA0_FCR_LS(31) | 1645 BA0_FCR_RS(31) | 1646 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 1647 BA0_FCR_OF(dma->fifo_offset)); 1648 } 1649 1650 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */ 1651 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */ 1652 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */ 1653 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */ 1654 1655 /* Activate wave playback FIFO for FM playback */ 1656 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) | 1657 BA0_FCR_RS(1) | 1658 BA0_FCR_SZ(CS4281_FIFO_SIZE) | 1659 BA0_FCR_OF(chip->dma[0].fifo_offset); 1660 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR); 1661 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) | 1662 (chip->src_right_play_slot << 8) | 1663 (chip->src_left_rec_slot << 16) | 1664 (chip->src_right_rec_slot << 24)); 1665 1666 /* Initialize digital volume */ 1667 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0); 1668 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0); 1669 1670 /* Enable IRQs */ 1671 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1672 /* Unmask interrupts */ 1673 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~( 1674 BA0_HISR_MIDI | 1675 BA0_HISR_DMAI | 1676 BA0_HISR_DMA(0) | 1677 BA0_HISR_DMA(1) | 1678 BA0_HISR_DMA(2) | 1679 BA0_HISR_DMA(3))); 1680 synchronize_irq(chip->irq); 1681 1682 return 0; 1683 } 1684 1685 /* 1686 * MIDI section 1687 */ 1688 1689 static void snd_cs4281_midi_reset(cs4281_t *chip) 1690 { 1691 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST); 1692 udelay(100); 1693 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1694 } 1695 1696 static int snd_cs4281_midi_input_open(snd_rawmidi_substream_t * substream) 1697 { 1698 cs4281_t *chip = substream->rmidi->private_data; 1699 1700 spin_lock_irq(&chip->reg_lock); 1701 chip->midcr |= BA0_MIDCR_RXE; 1702 chip->midi_input = substream; 1703 if (!(chip->uartm & CS4281_MODE_OUTPUT)) { 1704 snd_cs4281_midi_reset(chip); 1705 } else { 1706 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1707 } 1708 spin_unlock_irq(&chip->reg_lock); 1709 return 0; 1710 } 1711 1712 static int snd_cs4281_midi_input_close(snd_rawmidi_substream_t * substream) 1713 { 1714 cs4281_t *chip = substream->rmidi->private_data; 1715 1716 spin_lock_irq(&chip->reg_lock); 1717 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE); 1718 chip->midi_input = NULL; 1719 if (!(chip->uartm & CS4281_MODE_OUTPUT)) { 1720 snd_cs4281_midi_reset(chip); 1721 } else { 1722 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1723 } 1724 chip->uartm &= ~CS4281_MODE_INPUT; 1725 spin_unlock_irq(&chip->reg_lock); 1726 return 0; 1727 } 1728 1729 static int snd_cs4281_midi_output_open(snd_rawmidi_substream_t * substream) 1730 { 1731 cs4281_t *chip = substream->rmidi->private_data; 1732 1733 spin_lock_irq(&chip->reg_lock); 1734 chip->uartm |= CS4281_MODE_OUTPUT; 1735 chip->midcr |= BA0_MIDCR_TXE; 1736 chip->midi_output = substream; 1737 if (!(chip->uartm & CS4281_MODE_INPUT)) { 1738 snd_cs4281_midi_reset(chip); 1739 } else { 1740 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1741 } 1742 spin_unlock_irq(&chip->reg_lock); 1743 return 0; 1744 } 1745 1746 static int snd_cs4281_midi_output_close(snd_rawmidi_substream_t * substream) 1747 { 1748 cs4281_t *chip = substream->rmidi->private_data; 1749 1750 spin_lock_irq(&chip->reg_lock); 1751 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE); 1752 chip->midi_output = NULL; 1753 if (!(chip->uartm & CS4281_MODE_INPUT)) { 1754 snd_cs4281_midi_reset(chip); 1755 } else { 1756 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1757 } 1758 chip->uartm &= ~CS4281_MODE_OUTPUT; 1759 spin_unlock_irq(&chip->reg_lock); 1760 return 0; 1761 } 1762 1763 static void snd_cs4281_midi_input_trigger(snd_rawmidi_substream_t * substream, int up) 1764 { 1765 unsigned long flags; 1766 cs4281_t *chip = substream->rmidi->private_data; 1767 1768 spin_lock_irqsave(&chip->reg_lock, flags); 1769 if (up) { 1770 if ((chip->midcr & BA0_MIDCR_RIE) == 0) { 1771 chip->midcr |= BA0_MIDCR_RIE; 1772 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1773 } 1774 } else { 1775 if (chip->midcr & BA0_MIDCR_RIE) { 1776 chip->midcr &= ~BA0_MIDCR_RIE; 1777 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1778 } 1779 } 1780 spin_unlock_irqrestore(&chip->reg_lock, flags); 1781 } 1782 1783 static void snd_cs4281_midi_output_trigger(snd_rawmidi_substream_t * substream, int up) 1784 { 1785 unsigned long flags; 1786 cs4281_t *chip = substream->rmidi->private_data; 1787 unsigned char byte; 1788 1789 spin_lock_irqsave(&chip->reg_lock, flags); 1790 if (up) { 1791 if ((chip->midcr & BA0_MIDCR_TIE) == 0) { 1792 chip->midcr |= BA0_MIDCR_TIE; 1793 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 1794 while ((chip->midcr & BA0_MIDCR_TIE) && 1795 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { 1796 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 1797 chip->midcr &= ~BA0_MIDCR_TIE; 1798 } else { 1799 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte); 1800 } 1801 } 1802 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1803 } 1804 } else { 1805 if (chip->midcr & BA0_MIDCR_TIE) { 1806 chip->midcr &= ~BA0_MIDCR_TIE; 1807 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1808 } 1809 } 1810 spin_unlock_irqrestore(&chip->reg_lock, flags); 1811 } 1812 1813 static snd_rawmidi_ops_t snd_cs4281_midi_output = 1814 { 1815 .open = snd_cs4281_midi_output_open, 1816 .close = snd_cs4281_midi_output_close, 1817 .trigger = snd_cs4281_midi_output_trigger, 1818 }; 1819 1820 static snd_rawmidi_ops_t snd_cs4281_midi_input = 1821 { 1822 .open = snd_cs4281_midi_input_open, 1823 .close = snd_cs4281_midi_input_close, 1824 .trigger = snd_cs4281_midi_input_trigger, 1825 }; 1826 1827 static int __devinit snd_cs4281_midi(cs4281_t * chip, int device, snd_rawmidi_t **rrawmidi) 1828 { 1829 snd_rawmidi_t *rmidi; 1830 int err; 1831 1832 if (rrawmidi) 1833 *rrawmidi = NULL; 1834 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0) 1835 return err; 1836 strcpy(rmidi->name, "CS4281"); 1837 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output); 1838 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input); 1839 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 1840 rmidi->private_data = chip; 1841 chip->rmidi = rmidi; 1842 if (rrawmidi) 1843 *rrawmidi = rmidi; 1844 return 0; 1845 } 1846 1847 /* 1848 * Interrupt handler 1849 */ 1850 1851 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1852 { 1853 cs4281_t *chip = dev_id; 1854 unsigned int status, dma, val; 1855 cs4281_dma_t *cdma; 1856 1857 if (chip == NULL) 1858 return IRQ_NONE; 1859 status = snd_cs4281_peekBA0(chip, BA0_HISR); 1860 if ((status & 0x7fffffff) == 0) { 1861 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1862 return IRQ_NONE; 1863 } 1864 1865 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) { 1866 for (dma = 0; dma < 4; dma++) 1867 if (status & BA0_HISR_DMA(dma)) { 1868 cdma = &chip->dma[dma]; 1869 spin_lock(&chip->reg_lock); 1870 /* ack DMA IRQ */ 1871 val = snd_cs4281_peekBA0(chip, cdma->regHDSR); 1872 /* workaround, sometimes CS4281 acknowledges */ 1873 /* end or middle transfer position twice */ 1874 cdma->frag++; 1875 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) { 1876 cdma->frag--; 1877 chip->spurious_dhtc_irq++; 1878 spin_unlock(&chip->reg_lock); 1879 continue; 1880 } 1881 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) { 1882 cdma->frag--; 1883 chip->spurious_dtc_irq++; 1884 spin_unlock(&chip->reg_lock); 1885 continue; 1886 } 1887 spin_unlock(&chip->reg_lock); 1888 snd_pcm_period_elapsed(cdma->substream); 1889 } 1890 } 1891 1892 if ((status & BA0_HISR_MIDI) && chip->rmidi) { 1893 unsigned char c; 1894 1895 spin_lock(&chip->reg_lock); 1896 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) { 1897 c = snd_cs4281_peekBA0(chip, BA0_MIDRP); 1898 if ((chip->midcr & BA0_MIDCR_RIE) == 0) 1899 continue; 1900 snd_rawmidi_receive(chip->midi_input, &c, 1); 1901 } 1902 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) { 1903 if ((chip->midcr & BA0_MIDCR_TIE) == 0) 1904 break; 1905 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) { 1906 chip->midcr &= ~BA0_MIDCR_TIE; 1907 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr); 1908 break; 1909 } 1910 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c); 1911 } 1912 spin_unlock(&chip->reg_lock); 1913 } 1914 1915 /* EOI to the PCI part... reenables interrupts */ 1916 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI); 1917 1918 return IRQ_HANDLED; 1919 } 1920 1921 1922 /* 1923 * OPL3 command 1924 */ 1925 static void snd_cs4281_opl3_command(opl3_t * opl3, unsigned short cmd, unsigned char val) 1926 { 1927 unsigned long flags; 1928 cs4281_t *chip = opl3->private_data; 1929 void __iomem *port; 1930 1931 if (cmd & OPL3_RIGHT) 1932 port = chip->ba0 + BA0_B1AP; /* right port */ 1933 else 1934 port = chip->ba0 + BA0_B0AP; /* left port */ 1935 1936 spin_lock_irqsave(&opl3->reg_lock, flags); 1937 1938 writel((unsigned int)cmd, port); 1939 udelay(10); 1940 1941 writel((unsigned int)val, port + 4); 1942 udelay(30); 1943 1944 spin_unlock_irqrestore(&opl3->reg_lock, flags); 1945 } 1946 1947 static int __devinit snd_cs4281_probe(struct pci_dev *pci, 1948 const struct pci_device_id *pci_id) 1949 { 1950 static int dev; 1951 snd_card_t *card; 1952 cs4281_t *chip; 1953 opl3_t *opl3; 1954 int err; 1955 1956 if (dev >= SNDRV_CARDS) 1957 return -ENODEV; 1958 if (!enable[dev]) { 1959 dev++; 1960 return -ENOENT; 1961 } 1962 1963 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 1964 if (card == NULL) 1965 return -ENOMEM; 1966 1967 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) { 1968 snd_card_free(card); 1969 return err; 1970 } 1971 1972 if ((err = snd_cs4281_mixer(chip)) < 0) { 1973 snd_card_free(card); 1974 return err; 1975 } 1976 if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) { 1977 snd_card_free(card); 1978 return err; 1979 } 1980 if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) { 1981 snd_card_free(card); 1982 return err; 1983 } 1984 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) { 1985 snd_card_free(card); 1986 return err; 1987 } 1988 opl3->private_data = chip; 1989 opl3->command = snd_cs4281_opl3_command; 1990 snd_opl3_init(opl3); 1991 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) { 1992 snd_card_free(card); 1993 return err; 1994 } 1995 snd_cs4281_create_gameport(chip); 1996 strcpy(card->driver, "CS4281"); 1997 strcpy(card->shortname, "Cirrus Logic CS4281"); 1998 sprintf(card->longname, "%s at 0x%lx, irq %d", 1999 card->shortname, 2000 chip->ba0_addr, 2001 chip->irq); 2002 2003 if ((err = snd_card_register(card)) < 0) { 2004 snd_card_free(card); 2005 return err; 2006 } 2007 2008 pci_set_drvdata(pci, card); 2009 dev++; 2010 return 0; 2011 } 2012 2013 static void __devexit snd_cs4281_remove(struct pci_dev *pci) 2014 { 2015 snd_card_free(pci_get_drvdata(pci)); 2016 pci_set_drvdata(pci, NULL); 2017 } 2018 2019 /* 2020 * Power Management 2021 */ 2022 #ifdef CONFIG_PM 2023 2024 static int saved_regs[SUSPEND_REGISTERS] = { 2025 BA0_JSCTL, 2026 BA0_GPIOR, 2027 BA0_SSCR, 2028 BA0_MIDCR, 2029 BA0_SRCSA, 2030 BA0_PASR, 2031 BA0_CASR, 2032 BA0_DACSR, 2033 BA0_ADCSR, 2034 BA0_FMLVC, 2035 BA0_FMRVC, 2036 BA0_PPLVC, 2037 BA0_PPRVC, 2038 }; 2039 2040 #define CLKCR1_CKRA 0x00010000L 2041 2042 static int cs4281_suspend(snd_card_t *card, pm_message_t state) 2043 { 2044 cs4281_t *chip = card->pm_private_data; 2045 u32 ulCLK; 2046 unsigned int i; 2047 2048 snd_pcm_suspend_all(chip->pcm); 2049 2050 if (chip->ac97) 2051 snd_ac97_suspend(chip->ac97); 2052 if (chip->ac97_secondary) 2053 snd_ac97_suspend(chip->ac97_secondary); 2054 2055 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2056 ulCLK |= CLKCR1_CKRA; 2057 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2058 2059 /* Disable interrupts. */ 2060 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM); 2061 2062 /* remember the status registers */ 2063 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 2064 if (saved_regs[i]) 2065 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]); 2066 2067 /* Turn off the serial ports. */ 2068 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0); 2069 2070 /* Power off FM, Joystick, AC link, */ 2071 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0); 2072 2073 /* DLL off. */ 2074 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0); 2075 2076 /* AC link off. */ 2077 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0); 2078 2079 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2080 ulCLK &= ~CLKCR1_CKRA; 2081 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2082 2083 pci_disable_device(chip->pci); 2084 return 0; 2085 } 2086 2087 static int cs4281_resume(snd_card_t *card) 2088 { 2089 cs4281_t *chip = card->pm_private_data; 2090 unsigned int i; 2091 u32 ulCLK; 2092 2093 pci_enable_device(chip->pci); 2094 pci_set_master(chip->pci); 2095 2096 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2097 ulCLK |= CLKCR1_CKRA; 2098 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2099 2100 snd_cs4281_chip_init(chip); 2101 2102 /* restore the status registers */ 2103 for (i = 0; i < ARRAY_SIZE(saved_regs); i++) 2104 if (saved_regs[i]) 2105 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]); 2106 2107 if (chip->ac97) 2108 snd_ac97_resume(chip->ac97); 2109 if (chip->ac97_secondary) 2110 snd_ac97_resume(chip->ac97_secondary); 2111 2112 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1); 2113 ulCLK &= ~CLKCR1_CKRA; 2114 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK); 2115 2116 return 0; 2117 } 2118 #endif /* CONFIG_PM */ 2119 2120 static struct pci_driver driver = { 2121 .name = "CS4281", 2122 .id_table = snd_cs4281_ids, 2123 .probe = snd_cs4281_probe, 2124 .remove = __devexit_p(snd_cs4281_remove), 2125 SND_PCI_PM_CALLBACKS 2126 }; 2127 2128 static int __init alsa_card_cs4281_init(void) 2129 { 2130 return pci_register_driver(&driver); 2131 } 2132 2133 static void __exit alsa_card_cs4281_exit(void) 2134 { 2135 pci_unregister_driver(&driver); 2136 } 2137 2138 module_init(alsa_card_cs4281_init) 2139 module_exit(alsa_card_cs4281_exit) 2140