1 /* 2 * Driver for C-Media CMI8338 and 8738 PCI soundcards. 3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 /* Does not work. Warning may block system in capture mode */ 21 /* #define USE_VAR48KRATE */ 22 23 #include <sound/driver.h> 24 #include <asm/io.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/init.h> 28 #include <linux/pci.h> 29 #include <linux/slab.h> 30 #include <linux/gameport.h> 31 #include <linux/moduleparam.h> 32 #include <sound/core.h> 33 #include <sound/info.h> 34 #include <sound/control.h> 35 #include <sound/pcm.h> 36 #include <sound/rawmidi.h> 37 #include <sound/mpu401.h> 38 #include <sound/opl3.h> 39 #include <sound/sb.h> 40 #include <sound/asoundef.h> 41 #include <sound/initval.h> 42 43 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); 44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI"); 45 MODULE_LICENSE("GPL"); 46 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738}," 47 "{C-Media,CMI8738B}," 48 "{C-Media,CMI8338A}," 49 "{C-Media,CMI8338B}}"); 50 51 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 52 #define SUPPORT_JOYSTICK 1 53 #endif 54 55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 58 static long mpu_port[SNDRV_CARDS]; 59 static long fm_port[SNDRV_CARDS]; 60 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; 61 #ifdef SUPPORT_JOYSTICK 62 static int joystick_port[SNDRV_CARDS]; 63 #endif 64 65 module_param_array(index, int, NULL, 0444); 66 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard."); 67 module_param_array(id, charp, NULL, 0444); 68 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard."); 69 module_param_array(enable, bool, NULL, 0444); 70 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard."); 71 module_param_array(mpu_port, long, NULL, 0444); 72 MODULE_PARM_DESC(mpu_port, "MPU-401 port."); 73 module_param_array(fm_port, long, NULL, 0444); 74 MODULE_PARM_DESC(fm_port, "FM port."); 75 module_param_array(soft_ac3, bool, NULL, 0444); 76 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only)."); 77 #ifdef SUPPORT_JOYSTICK 78 module_param_array(joystick_port, int, NULL, 0444); 79 MODULE_PARM_DESC(joystick_port, "Joystick port address."); 80 #endif 81 82 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738 83 #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 84 #endif 85 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B 86 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 87 #endif 88 89 /* 90 * CM8x38 registers definition 91 */ 92 93 #define CM_REG_FUNCTRL0 0x00 94 #define CM_RST_CH1 0x00080000 95 #define CM_RST_CH0 0x00040000 96 #define CM_CHEN1 0x00020000 /* ch1: enable */ 97 #define CM_CHEN0 0x00010000 /* ch0: enable */ 98 #define CM_PAUSE1 0x00000008 /* ch1: pause */ 99 #define CM_PAUSE0 0x00000004 /* ch0: pause */ 100 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */ 101 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */ 102 103 #define CM_REG_FUNCTRL1 0x04 104 #define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */ 105 #define CM_ASFC_SHIFT 13 106 #define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */ 107 #define CM_DSFC_SHIFT 10 108 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */ 109 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */ 110 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */ 111 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */ 112 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */ 113 #define CM_BREQ 0x00000010 /* bus master enabled */ 114 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */ 115 #define CM_UART_EN 0x00000004 /* UART */ 116 #define CM_JYSTK_EN 0x00000002 /* joy stick */ 117 118 #define CM_REG_CHFORMAT 0x08 119 120 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */ 121 #define CM_CHB3D 0x20000000 /* 4 channels */ 122 123 #define CM_CHIP_MASK1 0x1f000000 124 #define CM_CHIP_037 0x01000000 125 126 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */ 127 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */ 128 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */ 129 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */ 130 131 #define CM_ADCBITLEN_MASK 0x0000C000 132 #define CM_ADCBITLEN_16 0x00000000 133 #define CM_ADCBITLEN_15 0x00004000 134 #define CM_ADCBITLEN_14 0x00008000 135 #define CM_ADCBITLEN_13 0x0000C000 136 137 #define CM_ADCDACLEN_MASK 0x00003000 138 #define CM_ADCDACLEN_060 0x00000000 139 #define CM_ADCDACLEN_066 0x00001000 140 #define CM_ADCDACLEN_130 0x00002000 141 #define CM_ADCDACLEN_280 0x00003000 142 143 #define CM_CH1_SRATE_176K 0x00000800 144 #define CM_CH1_SRATE_88K 0x00000400 145 #define CM_CH0_SRATE_176K 0x00000200 146 #define CM_CH0_SRATE_88K 0x00000100 147 148 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */ 149 150 #define CM_CH1FMT_MASK 0x0000000C 151 #define CM_CH1FMT_SHIFT 2 152 #define CM_CH0FMT_MASK 0x00000003 153 #define CM_CH0FMT_SHIFT 0 154 155 #define CM_REG_INT_HLDCLR 0x0C 156 #define CM_CHIP_MASK2 0xff000000 157 #define CM_CHIP_039 0x04000000 158 #define CM_CHIP_039_6CH 0x01000000 159 #define CM_CHIP_055 0x08000000 160 #define CM_CHIP_8768 0x20000000 161 #define CM_TDMA_INT_EN 0x00040000 162 #define CM_CH1_INT_EN 0x00020000 163 #define CM_CH0_INT_EN 0x00010000 164 #define CM_INT_HOLD 0x00000002 165 #define CM_INT_CLEAR 0x00000001 166 167 #define CM_REG_INT_STATUS 0x10 168 #define CM_INTR 0x80000000 169 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */ 170 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */ 171 #define CM_UARTINT 0x00010000 172 #define CM_LTDMAINT 0x00008000 173 #define CM_HTDMAINT 0x00004000 174 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */ 175 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */ 176 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */ 177 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */ 178 #define CM_CH1BUSY 0x00000008 179 #define CM_CH0BUSY 0x00000004 180 #define CM_CHINT1 0x00000002 181 #define CM_CHINT0 0x00000001 182 183 #define CM_REG_LEGACY_CTRL 0x14 184 #define CM_NXCHG 0x80000000 /* h/w multi channels? */ 185 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */ 186 #define CM_VMPU_330 0x00000000 187 #define CM_VMPU_320 0x20000000 188 #define CM_VMPU_310 0x40000000 189 #define CM_VMPU_300 0x60000000 190 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */ 191 #define CM_VSBSEL_220 0x00000000 192 #define CM_VSBSEL_240 0x04000000 193 #define CM_VSBSEL_260 0x08000000 194 #define CM_VSBSEL_280 0x0C000000 195 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */ 196 #define CM_FMSEL_388 0x00000000 197 #define CM_FMSEL_3C8 0x01000000 198 #define CM_FMSEL_3E0 0x02000000 199 #define CM_FMSEL_3E8 0x03000000 200 #define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */ 201 #define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */ 202 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */ 203 #define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */ 204 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */ 205 #define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */ 206 207 #define CM_REG_MISC_CTRL 0x18 208 #define CM_PWD 0x80000000 209 #define CM_RESET 0x40000000 210 #define CM_SFIL_MASK 0x30000000 211 #define CM_TXVX 0x08000000 212 #define CM_N4SPK3D 0x04000000 /* 4ch output */ 213 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */ 214 #define CM_SPDIF48K 0x01000000 /* write */ 215 #define CM_SPATUS48K 0x01000000 /* read */ 216 #define CM_ENDBDAC 0x00800000 /* enable dual dac */ 217 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */ 218 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */ 219 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */ 220 #define CM_FM_EN 0x00080000 /* enalbe FM */ 221 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */ 222 #define CM_VIDWPDSB 0x00010000 223 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */ 224 #define CM_MASK_EN 0x00004000 225 #define CM_VIDWPPRT 0x00002000 226 #define CM_SFILENB 0x00001000 227 #define CM_MMODE_MASK 0x00000E00 228 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */ 229 #define CM_ENCENTER 0x00000080 230 #define CM_FLINKON 0x00000040 231 #define CM_FLINKOFF 0x00000020 232 #define CM_MIDSMP 0x00000010 233 #define CM_UPDDMA_MASK 0x0000000C 234 #define CM_TWAIT_MASK 0x00000003 235 236 /* byte */ 237 #define CM_REG_MIXER0 0x20 238 239 #define CM_REG_SB16_DATA 0x22 240 #define CM_REG_SB16_ADDR 0x23 241 242 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */ 243 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */ 244 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */ 245 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */ 246 247 #define CM_REG_MIXER1 0x24 248 #define CM_FMMUTE 0x80 /* mute FM */ 249 #define CM_FMMUTE_SHIFT 7 250 #define CM_WSMUTE 0x40 /* mute PCM */ 251 #define CM_WSMUTE_SHIFT 6 252 #define CM_SPK4 0x20 /* lin-in -> rear line out */ 253 #define CM_SPK4_SHIFT 5 254 #define CM_REAR2FRONT 0x10 /* exchange rear/front */ 255 #define CM_REAR2FRONT_SHIFT 4 256 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */ 257 #define CM_WAVEINL_SHIFT 3 258 #define CM_WAVEINR 0x04 /* digical wave rec. right */ 259 #define CM_WAVEINR_SHIFT 2 260 #define CM_X3DEN 0x02 /* 3D surround enable */ 261 #define CM_X3DEN_SHIFT 1 262 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */ 263 #define CM_CDPLAY_SHIFT 0 264 265 #define CM_REG_MIXER2 0x25 266 #define CM_RAUXREN 0x80 /* AUX right capture */ 267 #define CM_RAUXREN_SHIFT 7 268 #define CM_RAUXLEN 0x40 /* AUX left capture */ 269 #define CM_RAUXLEN_SHIFT 6 270 #define CM_VAUXRM 0x20 /* AUX right mute */ 271 #define CM_VAUXRM_SHIFT 5 272 #define CM_VAUXLM 0x10 /* AUX left mute */ 273 #define CM_VAUXLM_SHIFT 4 274 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */ 275 #define CM_VADMIC_SHIFT 1 276 #define CM_MICGAINZ 0x01 /* mic boost */ 277 #define CM_MICGAINZ_SHIFT 0 278 279 #define CM_REG_AUX_VOL 0x26 280 #define CM_VAUXL_MASK 0xf0 281 #define CM_VAUXR_MASK 0x0f 282 283 #define CM_REG_MISC 0x27 284 #define CM_XGPO1 0x20 285 // #define CM_XGPBIO 0x04 286 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */ 287 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */ 288 #define CM_SPDVALID 0x02 /* spdif input valid check */ 289 #define CM_DMAUTO 0x01 290 291 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */ 292 /* 293 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738 294 * or identical with AC97 codec? 295 */ 296 #define CM_REG_EXTERN_CODEC CM_REG_AC97 297 298 /* 299 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6) 300 */ 301 #define CM_REG_MPU_PCI 0x40 302 303 /* 304 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6) 305 */ 306 #define CM_REG_FM_PCI 0x50 307 308 /* 309 * for CMI-8338 .. this is not valid for CMI-8738. 310 */ 311 #define CM_REG_EXTENT_IND 0xf0 312 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */ 313 #define CM_VPHONE_SHIFT 5 314 #define CM_VPHOM 0x10 /* Phone mute control */ 315 #define CM_VSPKM 0x08 /* Speaker mute control, default high */ 316 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */ 317 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */ 318 319 /* 320 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738): 321 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL 322 * unit (readonly?). 323 */ 324 #define CM_REG_PLL 0xf8 325 326 /* 327 * extended registers 328 */ 329 #define CM_REG_CH0_FRAME1 0x80 /* base address */ 330 #define CM_REG_CH0_FRAME2 0x84 331 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */ 332 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */ 333 #define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */ 334 #define CM_CHB3D8C 0x20 /* 7.1 channels support */ 335 #define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */ 336 #define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */ 337 #define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */ 338 #define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */ 339 #define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */ 340 341 /* 342 * size of i/o region 343 */ 344 #define CM_EXTENT_CODEC 0x100 345 #define CM_EXTENT_MIDI 0x2 346 #define CM_EXTENT_SYNTH 0x4 347 348 349 /* 350 * pci ids 351 */ 352 #ifndef PCI_VENDOR_ID_CMEDIA 353 #define PCI_VENDOR_ID_CMEDIA 0x13F6 354 #endif 355 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338A 356 #define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 357 #endif 358 #ifndef PCI_DEVICE_ID_CMEDIA_CM8338B 359 #define PCI_DEVICE_ID_CMEDIA_CM8338B 0x0101 360 #endif 361 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738 362 #define PCI_DEVICE_ID_CMEDIA_CM8738 0x0111 363 #endif 364 #ifndef PCI_DEVICE_ID_CMEDIA_CM8738B 365 #define PCI_DEVICE_ID_CMEDIA_CM8738B 0x0112 366 #endif 367 368 /* 369 * channels for playback / capture 370 */ 371 #define CM_CH_PLAY 0 372 #define CM_CH_CAPT 1 373 374 /* 375 * flags to check device open/close 376 */ 377 #define CM_OPEN_NONE 0 378 #define CM_OPEN_CH_MASK 0x01 379 #define CM_OPEN_DAC 0x10 380 #define CM_OPEN_ADC 0x20 381 #define CM_OPEN_SPDIF 0x40 382 #define CM_OPEN_MCHAN 0x80 383 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC) 384 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC) 385 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN) 386 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC) 387 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF) 388 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF) 389 390 391 #if CM_CH_PLAY == 1 392 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K 393 #define CM_PLAYBACK_SPDF CM_SPDF_1 394 #define CM_CAPTURE_SPDF CM_SPDF_0 395 #else 396 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K 397 #define CM_PLAYBACK_SPDF CM_SPDF_0 398 #define CM_CAPTURE_SPDF CM_SPDF_1 399 #endif 400 401 402 /* 403 * driver data 404 */ 405 406 typedef struct snd_stru_cmipci cmipci_t; 407 typedef struct snd_stru_cmipci_pcm cmipci_pcm_t; 408 409 struct snd_stru_cmipci_pcm { 410 snd_pcm_substream_t *substream; 411 int running; /* dac/adc running? */ 412 unsigned int dma_size; /* in frames */ 413 unsigned int period_size; /* in frames */ 414 unsigned int offset; /* physical address of the buffer */ 415 unsigned int fmt; /* format bits */ 416 int ch; /* channel (0/1) */ 417 unsigned int is_dac; /* is dac? */ 418 int bytes_per_frame; 419 int shift; 420 }; 421 422 /* mixer elements toggled/resumed during ac3 playback */ 423 struct cmipci_mixer_auto_switches { 424 const char *name; /* switch to toggle */ 425 int toggle_on; /* value to change when ac3 mode */ 426 }; 427 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = { 428 {"PCM Playback Switch", 0}, 429 {"IEC958 Output Switch", 1}, 430 {"IEC958 Mix Analog", 0}, 431 // {"IEC958 Out To DAC", 1}, // no longer used 432 {"IEC958 Loop", 0}, 433 }; 434 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer) 435 436 struct snd_stru_cmipci { 437 snd_card_t *card; 438 439 struct pci_dev *pci; 440 unsigned int device; /* device ID */ 441 int irq; 442 443 unsigned long iobase; 444 unsigned int ctrl; /* FUNCTRL0 current value */ 445 446 snd_pcm_t *pcm; /* DAC/ADC PCM */ 447 snd_pcm_t *pcm2; /* 2nd DAC */ 448 snd_pcm_t *pcm_spdif; /* SPDIF */ 449 450 int chip_version; 451 int max_channels; 452 unsigned int has_dual_dac: 1; 453 unsigned int can_ac3_sw: 1; 454 unsigned int can_ac3_hw: 1; 455 unsigned int can_multi_ch: 1; 456 unsigned int do_soft_ac3: 1; 457 458 unsigned int spdif_playback_avail: 1; /* spdif ready? */ 459 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */ 460 int spdif_counter; /* for software AC3 */ 461 462 unsigned int dig_status; 463 unsigned int dig_pcm_status; 464 465 snd_pcm_hardware_t *hw_info[3]; /* for playbacks */ 466 467 int opened[2]; /* open mode */ 468 struct semaphore open_mutex; 469 470 unsigned int mixer_insensitive: 1; 471 snd_kcontrol_t *mixer_res_ctl[CM_SAVED_MIXERS]; 472 int mixer_res_status[CM_SAVED_MIXERS]; 473 474 opl3_t *opl3; 475 snd_hwdep_t *opl3hwdep; 476 477 cmipci_pcm_t channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */ 478 479 /* external MIDI */ 480 snd_rawmidi_t *rmidi; 481 482 #ifdef SUPPORT_JOYSTICK 483 struct gameport *gameport; 484 #endif 485 486 spinlock_t reg_lock; 487 }; 488 489 490 /* read/write operations for dword register */ 491 static inline void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data) 492 { 493 outl(data, cm->iobase + cmd); 494 } 495 496 static inline unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd) 497 { 498 return inl(cm->iobase + cmd); 499 } 500 501 /* read/write operations for word register */ 502 static inline void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data) 503 { 504 outw(data, cm->iobase + cmd); 505 } 506 507 static inline unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd) 508 { 509 return inw(cm->iobase + cmd); 510 } 511 512 /* read/write operations for byte register */ 513 static inline void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data) 514 { 515 outb(data, cm->iobase + cmd); 516 } 517 518 static inline unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd) 519 { 520 return inb(cm->iobase + cmd); 521 } 522 523 /* bit operations for dword register */ 524 static int snd_cmipci_set_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag) 525 { 526 unsigned int val, oval; 527 val = oval = inl(cm->iobase + cmd); 528 val |= flag; 529 if (val == oval) 530 return 0; 531 outl(val, cm->iobase + cmd); 532 return 1; 533 } 534 535 static int snd_cmipci_clear_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag) 536 { 537 unsigned int val, oval; 538 val = oval = inl(cm->iobase + cmd); 539 val &= ~flag; 540 if (val == oval) 541 return 0; 542 outl(val, cm->iobase + cmd); 543 return 1; 544 } 545 546 /* bit operations for byte register */ 547 static int snd_cmipci_set_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag) 548 { 549 unsigned char val, oval; 550 val = oval = inb(cm->iobase + cmd); 551 val |= flag; 552 if (val == oval) 553 return 0; 554 outb(val, cm->iobase + cmd); 555 return 1; 556 } 557 558 static int snd_cmipci_clear_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag) 559 { 560 unsigned char val, oval; 561 val = oval = inb(cm->iobase + cmd); 562 val &= ~flag; 563 if (val == oval) 564 return 0; 565 outb(val, cm->iobase + cmd); 566 return 1; 567 } 568 569 570 /* 571 * PCM interface 572 */ 573 574 /* 575 * calculate frequency 576 */ 577 578 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 }; 579 580 static unsigned int snd_cmipci_rate_freq(unsigned int rate) 581 { 582 unsigned int i; 583 for (i = 0; i < ARRAY_SIZE(rates); i++) { 584 if (rates[i] == rate) 585 return i; 586 } 587 snd_BUG(); 588 return 0; 589 } 590 591 #ifdef USE_VAR48KRATE 592 /* 593 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???) 594 * does it this way .. maybe not. Never get any information from C-Media about 595 * that <werner@suse.de>. 596 */ 597 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n) 598 { 599 unsigned int delta, tolerance; 600 int xm, xn, xr; 601 602 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5)) 603 rate <<= 1; 604 *n = -1; 605 if (*r > 0xff) 606 goto out; 607 tolerance = rate*CM_TOLERANCE_RATE; 608 609 for (xn = (1+2); xn < (0x1f+2); xn++) { 610 for (xm = (1+2); xm < (0xff+2); xm++) { 611 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn; 612 613 if (xr < rate) 614 delta = rate - xr; 615 else 616 delta = xr - rate; 617 618 /* 619 * If we found one, remember this, 620 * and try to find a closer one 621 */ 622 if (delta < tolerance) { 623 tolerance = delta; 624 *m = xm - 2; 625 *n = xn - 2; 626 } 627 } 628 } 629 out: 630 return (*n > -1); 631 } 632 633 /* 634 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff 635 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen 636 * at the register CM_REG_FUNCTRL1 (0x04). 637 * Problem: other ways are also possible (any information about that?) 638 */ 639 static void snd_cmipci_set_pll(cmipci_t *cm, unsigned int rate, unsigned int slot) 640 { 641 unsigned int reg = CM_REG_PLL + slot; 642 /* 643 * Guess that this programs at reg. 0x04 the pos 15:13/12:10 644 * for DSFC/ASFC (000 upto 111). 645 */ 646 647 /* FIXME: Init (Do we've to set an other register first before programming?) */ 648 649 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */ 650 snd_cmipci_write_b(cm, reg, rate>>8); 651 snd_cmipci_write_b(cm, reg, rate&0xff); 652 653 /* FIXME: Setup (Do we've to set an other register first to enable this?) */ 654 } 655 #endif /* USE_VAR48KRATE */ 656 657 static int snd_cmipci_hw_params(snd_pcm_substream_t * substream, 658 snd_pcm_hw_params_t * hw_params) 659 { 660 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 661 } 662 663 static int snd_cmipci_playback2_hw_params(snd_pcm_substream_t * substream, 664 snd_pcm_hw_params_t * hw_params) 665 { 666 cmipci_t *cm = snd_pcm_substream_chip(substream); 667 if (params_channels(hw_params) > 2) { 668 down(&cm->open_mutex); 669 if (cm->opened[CM_CH_PLAY]) { 670 up(&cm->open_mutex); 671 return -EBUSY; 672 } 673 /* reserve the channel A */ 674 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI; 675 up(&cm->open_mutex); 676 } 677 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 678 } 679 680 static void snd_cmipci_ch_reset(cmipci_t *cm, int ch) 681 { 682 int reset = CM_RST_CH0 << (cm->channel[ch].ch); 683 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 684 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 685 udelay(10); 686 } 687 688 static int snd_cmipci_hw_free(snd_pcm_substream_t * substream) 689 { 690 return snd_pcm_lib_free_pages(substream); 691 } 692 693 694 /* 695 */ 696 697 static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8}; 698 static snd_pcm_hw_constraint_list_t hw_constraints_channels_4 = { 699 .count = 3, 700 .list = hw_channels, 701 .mask = 0, 702 }; 703 static snd_pcm_hw_constraint_list_t hw_constraints_channels_6 = { 704 .count = 5, 705 .list = hw_channels, 706 .mask = 0, 707 }; 708 static snd_pcm_hw_constraint_list_t hw_constraints_channels_8 = { 709 .count = 6, 710 .list = hw_channels, 711 .mask = 0, 712 }; 713 714 static int set_dac_channels(cmipci_t *cm, cmipci_pcm_t *rec, int channels) 715 { 716 if (channels > 2) { 717 if (! cm->can_multi_ch) 718 return -EINVAL; 719 if (rec->fmt != 0x03) /* stereo 16bit only */ 720 return -EINVAL; 721 722 spin_lock_irq(&cm->reg_lock); 723 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 724 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 725 if (channels > 4) { 726 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 727 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 728 } else { 729 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 730 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 731 } 732 if (channels >= 6) { 733 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 734 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 735 } else { 736 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 737 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 738 } 739 if (cm->chip_version == 68) { 740 if (channels == 8) { 741 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); 742 } else { 743 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); 744 } 745 } 746 spin_unlock_irq(&cm->reg_lock); 747 748 } else { 749 if (cm->can_multi_ch) { 750 spin_lock_irq(&cm->reg_lock); 751 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 752 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 753 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 754 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 755 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 756 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 757 spin_unlock_irq(&cm->reg_lock); 758 } 759 } 760 return 0; 761 } 762 763 764 /* 765 * prepare playback/capture channel 766 * channel to be used must have been set in rec->ch. 767 */ 768 static int snd_cmipci_pcm_prepare(cmipci_t *cm, cmipci_pcm_t *rec, 769 snd_pcm_substream_t *substream) 770 { 771 unsigned int reg, freq, val; 772 snd_pcm_runtime_t *runtime = substream->runtime; 773 774 rec->fmt = 0; 775 rec->shift = 0; 776 if (snd_pcm_format_width(runtime->format) >= 16) { 777 rec->fmt |= 0x02; 778 if (snd_pcm_format_width(runtime->format) > 16) 779 rec->shift++; /* 24/32bit */ 780 } 781 if (runtime->channels > 1) 782 rec->fmt |= 0x01; 783 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) { 784 snd_printd("cannot set dac channels\n"); 785 return -EINVAL; 786 } 787 788 rec->offset = runtime->dma_addr; 789 /* buffer and period sizes in frame */ 790 rec->dma_size = runtime->buffer_size << rec->shift; 791 rec->period_size = runtime->period_size << rec->shift; 792 if (runtime->channels > 2) { 793 /* multi-channels */ 794 rec->dma_size = (rec->dma_size * runtime->channels) / 2; 795 rec->period_size = (rec->period_size * runtime->channels) / 2; 796 } 797 798 spin_lock_irq(&cm->reg_lock); 799 800 /* set buffer address */ 801 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; 802 snd_cmipci_write(cm, reg, rec->offset); 803 /* program sample counts */ 804 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 805 snd_cmipci_write_w(cm, reg, rec->dma_size - 1); 806 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1); 807 808 /* set adc/dac flag */ 809 val = rec->ch ? CM_CHADC1 : CM_CHADC0; 810 if (rec->is_dac) 811 cm->ctrl &= ~val; 812 else 813 cm->ctrl |= val; 814 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 815 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 816 817 /* set sample rate */ 818 freq = snd_cmipci_rate_freq(runtime->rate); 819 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); 820 if (rec->ch) { 821 val &= ~CM_ASFC_MASK; 822 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK; 823 } else { 824 val &= ~CM_DSFC_MASK; 825 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; 826 } 827 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); 828 //snd_printd("cmipci: functrl1 = %08x\n", val); 829 830 /* set format */ 831 val = snd_cmipci_read(cm, CM_REG_CHFORMAT); 832 if (rec->ch) { 833 val &= ~CM_CH1FMT_MASK; 834 val |= rec->fmt << CM_CH1FMT_SHIFT; 835 } else { 836 val &= ~CM_CH0FMT_MASK; 837 val |= rec->fmt << CM_CH0FMT_SHIFT; 838 } 839 snd_cmipci_write(cm, CM_REG_CHFORMAT, val); 840 //snd_printd("cmipci: chformat = %08x\n", val); 841 842 rec->running = 0; 843 spin_unlock_irq(&cm->reg_lock); 844 845 return 0; 846 } 847 848 /* 849 * PCM trigger/stop 850 */ 851 static int snd_cmipci_pcm_trigger(cmipci_t *cm, cmipci_pcm_t *rec, 852 snd_pcm_substream_t *substream, int cmd) 853 { 854 unsigned int inthld, chen, reset, pause; 855 int result = 0; 856 857 inthld = CM_CH0_INT_EN << rec->ch; 858 chen = CM_CHEN0 << rec->ch; 859 reset = CM_RST_CH0 << rec->ch; 860 pause = CM_PAUSE0 << rec->ch; 861 862 spin_lock(&cm->reg_lock); 863 switch (cmd) { 864 case SNDRV_PCM_TRIGGER_START: 865 rec->running = 1; 866 /* set interrupt */ 867 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld); 868 cm->ctrl |= chen; 869 /* enable channel */ 870 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 871 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 872 break; 873 case SNDRV_PCM_TRIGGER_STOP: 874 rec->running = 0; 875 /* disable interrupt */ 876 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld); 877 /* reset */ 878 cm->ctrl &= ~chen; 879 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 880 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 881 break; 882 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 883 cm->ctrl |= pause; 884 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 885 break; 886 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 887 cm->ctrl &= ~pause; 888 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 889 break; 890 default: 891 result = -EINVAL; 892 break; 893 } 894 spin_unlock(&cm->reg_lock); 895 return result; 896 } 897 898 /* 899 * return the current pointer 900 */ 901 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(cmipci_t *cm, cmipci_pcm_t *rec, 902 snd_pcm_substream_t *substream) 903 { 904 size_t ptr; 905 unsigned int reg; 906 if (!rec->running) 907 return 0; 908 #if 1 // this seems better.. 909 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 910 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1); 911 ptr >>= rec->shift; 912 #else 913 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; 914 ptr = snd_cmipci_read(cm, reg) - rec->offset; 915 ptr = bytes_to_frames(substream->runtime, ptr); 916 #endif 917 if (substream->runtime->channels > 2) 918 ptr = (ptr * 2) / substream->runtime->channels; 919 return ptr; 920 } 921 922 /* 923 * playback 924 */ 925 926 static int snd_cmipci_playback_trigger(snd_pcm_substream_t *substream, 927 int cmd) 928 { 929 cmipci_t *cm = snd_pcm_substream_chip(substream); 930 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd); 931 } 932 933 static snd_pcm_uframes_t snd_cmipci_playback_pointer(snd_pcm_substream_t *substream) 934 { 935 cmipci_t *cm = snd_pcm_substream_chip(substream); 936 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream); 937 } 938 939 940 941 /* 942 * capture 943 */ 944 945 static int snd_cmipci_capture_trigger(snd_pcm_substream_t *substream, 946 int cmd) 947 { 948 cmipci_t *cm = snd_pcm_substream_chip(substream); 949 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd); 950 } 951 952 static snd_pcm_uframes_t snd_cmipci_capture_pointer(snd_pcm_substream_t *substream) 953 { 954 cmipci_t *cm = snd_pcm_substream_chip(substream); 955 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream); 956 } 957 958 959 /* 960 * hw preparation for spdif 961 */ 962 963 static int snd_cmipci_spdif_default_info(snd_kcontrol_t *kcontrol, 964 snd_ctl_elem_info_t *uinfo) 965 { 966 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 967 uinfo->count = 1; 968 return 0; 969 } 970 971 static int snd_cmipci_spdif_default_get(snd_kcontrol_t *kcontrol, 972 snd_ctl_elem_value_t *ucontrol) 973 { 974 cmipci_t *chip = snd_kcontrol_chip(kcontrol); 975 int i; 976 977 spin_lock_irq(&chip->reg_lock); 978 for (i = 0; i < 4; i++) 979 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff; 980 spin_unlock_irq(&chip->reg_lock); 981 return 0; 982 } 983 984 static int snd_cmipci_spdif_default_put(snd_kcontrol_t * kcontrol, 985 snd_ctl_elem_value_t * ucontrol) 986 { 987 cmipci_t *chip = snd_kcontrol_chip(kcontrol); 988 int i, change; 989 unsigned int val; 990 991 val = 0; 992 spin_lock_irq(&chip->reg_lock); 993 for (i = 0; i < 4; i++) 994 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); 995 change = val != chip->dig_status; 996 chip->dig_status = val; 997 spin_unlock_irq(&chip->reg_lock); 998 return change; 999 } 1000 1001 static snd_kcontrol_new_t snd_cmipci_spdif_default __devinitdata = 1002 { 1003 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1004 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 1005 .info = snd_cmipci_spdif_default_info, 1006 .get = snd_cmipci_spdif_default_get, 1007 .put = snd_cmipci_spdif_default_put 1008 }; 1009 1010 static int snd_cmipci_spdif_mask_info(snd_kcontrol_t *kcontrol, 1011 snd_ctl_elem_info_t *uinfo) 1012 { 1013 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1014 uinfo->count = 1; 1015 return 0; 1016 } 1017 1018 static int snd_cmipci_spdif_mask_get(snd_kcontrol_t * kcontrol, 1019 snd_ctl_elem_value_t *ucontrol) 1020 { 1021 ucontrol->value.iec958.status[0] = 0xff; 1022 ucontrol->value.iec958.status[1] = 0xff; 1023 ucontrol->value.iec958.status[2] = 0xff; 1024 ucontrol->value.iec958.status[3] = 0xff; 1025 return 0; 1026 } 1027 1028 static snd_kcontrol_new_t snd_cmipci_spdif_mask __devinitdata = 1029 { 1030 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1031 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1032 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 1033 .info = snd_cmipci_spdif_mask_info, 1034 .get = snd_cmipci_spdif_mask_get, 1035 }; 1036 1037 static int snd_cmipci_spdif_stream_info(snd_kcontrol_t *kcontrol, 1038 snd_ctl_elem_info_t *uinfo) 1039 { 1040 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1041 uinfo->count = 1; 1042 return 0; 1043 } 1044 1045 static int snd_cmipci_spdif_stream_get(snd_kcontrol_t *kcontrol, 1046 snd_ctl_elem_value_t *ucontrol) 1047 { 1048 cmipci_t *chip = snd_kcontrol_chip(kcontrol); 1049 int i; 1050 1051 spin_lock_irq(&chip->reg_lock); 1052 for (i = 0; i < 4; i++) 1053 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff; 1054 spin_unlock_irq(&chip->reg_lock); 1055 return 0; 1056 } 1057 1058 static int snd_cmipci_spdif_stream_put(snd_kcontrol_t *kcontrol, 1059 snd_ctl_elem_value_t *ucontrol) 1060 { 1061 cmipci_t *chip = snd_kcontrol_chip(kcontrol); 1062 int i, change; 1063 unsigned int val; 1064 1065 val = 0; 1066 spin_lock_irq(&chip->reg_lock); 1067 for (i = 0; i < 4; i++) 1068 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); 1069 change = val != chip->dig_pcm_status; 1070 chip->dig_pcm_status = val; 1071 spin_unlock_irq(&chip->reg_lock); 1072 return change; 1073 } 1074 1075 static snd_kcontrol_new_t snd_cmipci_spdif_stream __devinitdata = 1076 { 1077 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 1078 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1079 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1080 .info = snd_cmipci_spdif_stream_info, 1081 .get = snd_cmipci_spdif_stream_get, 1082 .put = snd_cmipci_spdif_stream_put 1083 }; 1084 1085 /* 1086 */ 1087 1088 /* save mixer setting and mute for AC3 playback */ 1089 static int save_mixer_state(cmipci_t *cm) 1090 { 1091 if (! cm->mixer_insensitive) { 1092 snd_ctl_elem_value_t *val; 1093 unsigned int i; 1094 1095 val = kmalloc(sizeof(*val), GFP_ATOMIC); 1096 if (!val) 1097 return -ENOMEM; 1098 for (i = 0; i < CM_SAVED_MIXERS; i++) { 1099 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i]; 1100 if (ctl) { 1101 int event; 1102 memset(val, 0, sizeof(*val)); 1103 ctl->get(ctl, val); 1104 cm->mixer_res_status[i] = val->value.integer.value[0]; 1105 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on; 1106 event = SNDRV_CTL_EVENT_MASK_INFO; 1107 if (cm->mixer_res_status[i] != val->value.integer.value[0]) { 1108 ctl->put(ctl, val); /* toggle */ 1109 event |= SNDRV_CTL_EVENT_MASK_VALUE; 1110 } 1111 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1112 snd_ctl_notify(cm->card, event, &ctl->id); 1113 } 1114 } 1115 kfree(val); 1116 cm->mixer_insensitive = 1; 1117 } 1118 return 0; 1119 } 1120 1121 1122 /* restore the previously saved mixer status */ 1123 static void restore_mixer_state(cmipci_t *cm) 1124 { 1125 if (cm->mixer_insensitive) { 1126 snd_ctl_elem_value_t *val; 1127 unsigned int i; 1128 1129 val = kmalloc(sizeof(*val), GFP_KERNEL); 1130 if (!val) 1131 return; 1132 cm->mixer_insensitive = 0; /* at first clear this; 1133 otherwise the changes will be ignored */ 1134 for (i = 0; i < CM_SAVED_MIXERS; i++) { 1135 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i]; 1136 if (ctl) { 1137 int event; 1138 1139 memset(val, 0, sizeof(*val)); 1140 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1141 ctl->get(ctl, val); 1142 event = SNDRV_CTL_EVENT_MASK_INFO; 1143 if (val->value.integer.value[0] != cm->mixer_res_status[i]) { 1144 val->value.integer.value[0] = cm->mixer_res_status[i]; 1145 ctl->put(ctl, val); 1146 event |= SNDRV_CTL_EVENT_MASK_VALUE; 1147 } 1148 snd_ctl_notify(cm->card, event, &ctl->id); 1149 } 1150 } 1151 kfree(val); 1152 } 1153 } 1154 1155 /* spinlock held! */ 1156 static void setup_ac3(cmipci_t *cm, snd_pcm_substream_t *subs, int do_ac3, int rate) 1157 { 1158 if (do_ac3) { 1159 /* AC3EN for 037 */ 1160 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); 1161 /* AC3EN for 039 */ 1162 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); 1163 1164 if (cm->can_ac3_hw) { 1165 /* SPD24SEL for 037, 0x02 */ 1166 /* SPD24SEL for 039, 0x20, but cannot be set */ 1167 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1168 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1169 } else { /* can_ac3_sw */ 1170 /* SPD32SEL for 037 & 039, 0x20 */ 1171 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1172 /* set 176K sample rate to fix 033 HW bug */ 1173 if (cm->chip_version == 33) { 1174 if (rate >= 48000) { 1175 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1176 } else { 1177 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1178 } 1179 } 1180 } 1181 1182 } else { 1183 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); 1184 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); 1185 1186 if (cm->can_ac3_hw) { 1187 /* chip model >= 37 */ 1188 if (snd_pcm_format_width(subs->runtime->format) > 16) { 1189 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1190 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1191 } else { 1192 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1193 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1194 } 1195 } else { 1196 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1197 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1198 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1199 } 1200 } 1201 } 1202 1203 static int setup_spdif_playback(cmipci_t *cm, snd_pcm_substream_t *subs, int up, int do_ac3) 1204 { 1205 int rate, err; 1206 1207 rate = subs->runtime->rate; 1208 1209 if (up && do_ac3) 1210 if ((err = save_mixer_state(cm)) < 0) 1211 return err; 1212 1213 spin_lock_irq(&cm->reg_lock); 1214 cm->spdif_playback_avail = up; 1215 if (up) { 1216 /* they are controlled via "IEC958 Output Switch" */ 1217 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1218 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1219 if (cm->spdif_playback_enabled) 1220 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1221 setup_ac3(cm, subs, do_ac3, rate); 1222 1223 if (rate == 48000) 1224 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1225 else 1226 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1227 1228 } else { 1229 /* they are controlled via "IEC958 Output Switch" */ 1230 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1231 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1232 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1233 setup_ac3(cm, subs, 0, 0); 1234 } 1235 spin_unlock_irq(&cm->reg_lock); 1236 return 0; 1237 } 1238 1239 1240 /* 1241 * preparation 1242 */ 1243 1244 /* playback - enable spdif only on the certain condition */ 1245 static int snd_cmipci_playback_prepare(snd_pcm_substream_t *substream) 1246 { 1247 cmipci_t *cm = snd_pcm_substream_chip(substream); 1248 int rate = substream->runtime->rate; 1249 int err, do_spdif, do_ac3 = 0; 1250 1251 do_spdif = ((rate == 44100 || rate == 48000) && 1252 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE && 1253 substream->runtime->channels == 2); 1254 if (do_spdif && cm->can_ac3_hw) 1255 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1256 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0) 1257 return err; 1258 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1259 } 1260 1261 /* playback (via device #2) - enable spdif always */ 1262 static int snd_cmipci_playback_spdif_prepare(snd_pcm_substream_t *substream) 1263 { 1264 cmipci_t *cm = snd_pcm_substream_chip(substream); 1265 int err, do_ac3; 1266 1267 if (cm->can_ac3_hw) 1268 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1269 else 1270 do_ac3 = 1; /* doesn't matter */ 1271 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0) 1272 return err; 1273 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1274 } 1275 1276 static int snd_cmipci_playback_hw_free(snd_pcm_substream_t *substream) 1277 { 1278 cmipci_t *cm = snd_pcm_substream_chip(substream); 1279 setup_spdif_playback(cm, substream, 0, 0); 1280 restore_mixer_state(cm); 1281 return snd_cmipci_hw_free(substream); 1282 } 1283 1284 /* capture */ 1285 static int snd_cmipci_capture_prepare(snd_pcm_substream_t *substream) 1286 { 1287 cmipci_t *cm = snd_pcm_substream_chip(substream); 1288 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); 1289 } 1290 1291 /* capture with spdif (via device #2) */ 1292 static int snd_cmipci_capture_spdif_prepare(snd_pcm_substream_t *substream) 1293 { 1294 cmipci_t *cm = snd_pcm_substream_chip(substream); 1295 1296 spin_lock_irq(&cm->reg_lock); 1297 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1298 spin_unlock_irq(&cm->reg_lock); 1299 1300 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); 1301 } 1302 1303 static int snd_cmipci_capture_spdif_hw_free(snd_pcm_substream_t *subs) 1304 { 1305 cmipci_t *cm = snd_pcm_substream_chip(subs); 1306 1307 spin_lock_irq(&cm->reg_lock); 1308 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1309 spin_unlock_irq(&cm->reg_lock); 1310 1311 return snd_cmipci_hw_free(subs); 1312 } 1313 1314 1315 /* 1316 * interrupt handler 1317 */ 1318 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1319 { 1320 cmipci_t *cm = dev_id; 1321 unsigned int status, mask = 0; 1322 1323 /* fastpath out, to ease interrupt sharing */ 1324 status = snd_cmipci_read(cm, CM_REG_INT_STATUS); 1325 if (!(status & CM_INTR)) 1326 return IRQ_NONE; 1327 1328 /* acknowledge interrupt */ 1329 spin_lock(&cm->reg_lock); 1330 if (status & CM_CHINT0) 1331 mask |= CM_CH0_INT_EN; 1332 if (status & CM_CHINT1) 1333 mask |= CM_CH1_INT_EN; 1334 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask); 1335 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask); 1336 spin_unlock(&cm->reg_lock); 1337 1338 if (cm->rmidi && (status & CM_UARTINT)) 1339 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs); 1340 1341 if (cm->pcm) { 1342 if ((status & CM_CHINT0) && cm->channel[0].running) 1343 snd_pcm_period_elapsed(cm->channel[0].substream); 1344 if ((status & CM_CHINT1) && cm->channel[1].running) 1345 snd_pcm_period_elapsed(cm->channel[1].substream); 1346 } 1347 return IRQ_HANDLED; 1348 } 1349 1350 /* 1351 * h/w infos 1352 */ 1353 1354 /* playback on channel A */ 1355 static snd_pcm_hardware_t snd_cmipci_playback = 1356 { 1357 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1358 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1359 SNDRV_PCM_INFO_MMAP_VALID), 1360 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1361 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1362 .rate_min = 5512, 1363 .rate_max = 48000, 1364 .channels_min = 1, 1365 .channels_max = 2, 1366 .buffer_bytes_max = (128*1024), 1367 .period_bytes_min = 64, 1368 .period_bytes_max = (128*1024), 1369 .periods_min = 2, 1370 .periods_max = 1024, 1371 .fifo_size = 0, 1372 }; 1373 1374 /* capture on channel B */ 1375 static snd_pcm_hardware_t snd_cmipci_capture = 1376 { 1377 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1378 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1379 SNDRV_PCM_INFO_MMAP_VALID), 1380 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1381 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1382 .rate_min = 5512, 1383 .rate_max = 48000, 1384 .channels_min = 1, 1385 .channels_max = 2, 1386 .buffer_bytes_max = (128*1024), 1387 .period_bytes_min = 64, 1388 .period_bytes_max = (128*1024), 1389 .periods_min = 2, 1390 .periods_max = 1024, 1391 .fifo_size = 0, 1392 }; 1393 1394 /* playback on channel B - stereo 16bit only? */ 1395 static snd_pcm_hardware_t snd_cmipci_playback2 = 1396 { 1397 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1398 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1399 SNDRV_PCM_INFO_MMAP_VALID), 1400 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1401 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1402 .rate_min = 5512, 1403 .rate_max = 48000, 1404 .channels_min = 2, 1405 .channels_max = 2, 1406 .buffer_bytes_max = (128*1024), 1407 .period_bytes_min = 64, 1408 .period_bytes_max = (128*1024), 1409 .periods_min = 2, 1410 .periods_max = 1024, 1411 .fifo_size = 0, 1412 }; 1413 1414 /* spdif playback on channel A */ 1415 static snd_pcm_hardware_t snd_cmipci_playback_spdif = 1416 { 1417 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1418 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1419 SNDRV_PCM_INFO_MMAP_VALID), 1420 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1421 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1422 .rate_min = 44100, 1423 .rate_max = 48000, 1424 .channels_min = 2, 1425 .channels_max = 2, 1426 .buffer_bytes_max = (128*1024), 1427 .period_bytes_min = 64, 1428 .period_bytes_max = (128*1024), 1429 .periods_min = 2, 1430 .periods_max = 1024, 1431 .fifo_size = 0, 1432 }; 1433 1434 /* spdif playback on channel A (32bit, IEC958 subframes) */ 1435 static snd_pcm_hardware_t snd_cmipci_playback_iec958_subframe = 1436 { 1437 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1438 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1439 SNDRV_PCM_INFO_MMAP_VALID), 1440 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1441 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1442 .rate_min = 44100, 1443 .rate_max = 48000, 1444 .channels_min = 2, 1445 .channels_max = 2, 1446 .buffer_bytes_max = (128*1024), 1447 .period_bytes_min = 64, 1448 .period_bytes_max = (128*1024), 1449 .periods_min = 2, 1450 .periods_max = 1024, 1451 .fifo_size = 0, 1452 }; 1453 1454 /* spdif capture on channel B */ 1455 static snd_pcm_hardware_t snd_cmipci_capture_spdif = 1456 { 1457 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1458 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1459 SNDRV_PCM_INFO_MMAP_VALID), 1460 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1461 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1462 .rate_min = 44100, 1463 .rate_max = 48000, 1464 .channels_min = 2, 1465 .channels_max = 2, 1466 .buffer_bytes_max = (128*1024), 1467 .period_bytes_min = 64, 1468 .period_bytes_max = (128*1024), 1469 .periods_min = 2, 1470 .periods_max = 1024, 1471 .fifo_size = 0, 1472 }; 1473 1474 /* 1475 * check device open/close 1476 */ 1477 static int open_device_check(cmipci_t *cm, int mode, snd_pcm_substream_t *subs) 1478 { 1479 int ch = mode & CM_OPEN_CH_MASK; 1480 1481 /* FIXME: a file should wait until the device becomes free 1482 * when it's opened on blocking mode. however, since the current 1483 * pcm framework doesn't pass file pointer before actually opened, 1484 * we can't know whether blocking mode or not in open callback.. 1485 */ 1486 down(&cm->open_mutex); 1487 if (cm->opened[ch]) { 1488 up(&cm->open_mutex); 1489 return -EBUSY; 1490 } 1491 cm->opened[ch] = mode; 1492 cm->channel[ch].substream = subs; 1493 if (! (mode & CM_OPEN_DAC)) { 1494 /* disable dual DAC mode */ 1495 cm->channel[ch].is_dac = 0; 1496 spin_lock_irq(&cm->reg_lock); 1497 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); 1498 spin_unlock_irq(&cm->reg_lock); 1499 } 1500 up(&cm->open_mutex); 1501 return 0; 1502 } 1503 1504 static void close_device_check(cmipci_t *cm, int mode) 1505 { 1506 int ch = mode & CM_OPEN_CH_MASK; 1507 1508 down(&cm->open_mutex); 1509 if (cm->opened[ch] == mode) { 1510 if (cm->channel[ch].substream) { 1511 snd_cmipci_ch_reset(cm, ch); 1512 cm->channel[ch].running = 0; 1513 cm->channel[ch].substream = NULL; 1514 } 1515 cm->opened[ch] = 0; 1516 if (! cm->channel[ch].is_dac) { 1517 /* enable dual DAC mode again */ 1518 cm->channel[ch].is_dac = 1; 1519 spin_lock_irq(&cm->reg_lock); 1520 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); 1521 spin_unlock_irq(&cm->reg_lock); 1522 } 1523 } 1524 up(&cm->open_mutex); 1525 } 1526 1527 /* 1528 */ 1529 1530 static int snd_cmipci_playback_open(snd_pcm_substream_t *substream) 1531 { 1532 cmipci_t *cm = snd_pcm_substream_chip(substream); 1533 snd_pcm_runtime_t *runtime = substream->runtime; 1534 int err; 1535 1536 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0) 1537 return err; 1538 runtime->hw = snd_cmipci_playback; 1539 runtime->hw.channels_max = cm->max_channels; 1540 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1541 cm->dig_pcm_status = cm->dig_status; 1542 return 0; 1543 } 1544 1545 static int snd_cmipci_capture_open(snd_pcm_substream_t *substream) 1546 { 1547 cmipci_t *cm = snd_pcm_substream_chip(substream); 1548 snd_pcm_runtime_t *runtime = substream->runtime; 1549 int err; 1550 1551 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0) 1552 return err; 1553 runtime->hw = snd_cmipci_capture; 1554 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording 1555 runtime->hw.rate_min = 41000; 1556 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000; 1557 } 1558 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1559 return 0; 1560 } 1561 1562 static int snd_cmipci_playback2_open(snd_pcm_substream_t *substream) 1563 { 1564 cmipci_t *cm = snd_pcm_substream_chip(substream); 1565 snd_pcm_runtime_t *runtime = substream->runtime; 1566 int err; 1567 1568 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */ 1569 return err; 1570 runtime->hw = snd_cmipci_playback2; 1571 down(&cm->open_mutex); 1572 if (! cm->opened[CM_CH_PLAY]) { 1573 if (cm->can_multi_ch) { 1574 runtime->hw.channels_max = cm->max_channels; 1575 if (cm->max_channels == 4) 1576 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4); 1577 else if (cm->max_channels == 6) 1578 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6); 1579 else if (cm->max_channels == 8) 1580 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8); 1581 } 1582 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1583 } 1584 up(&cm->open_mutex); 1585 return 0; 1586 } 1587 1588 static int snd_cmipci_playback_spdif_open(snd_pcm_substream_t *substream) 1589 { 1590 cmipci_t *cm = snd_pcm_substream_chip(substream); 1591 snd_pcm_runtime_t *runtime = substream->runtime; 1592 int err; 1593 1594 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */ 1595 return err; 1596 if (cm->can_ac3_hw) { 1597 runtime->hw = snd_cmipci_playback_spdif; 1598 if (cm->chip_version >= 37) 1599 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1600 } else { 1601 runtime->hw = snd_cmipci_playback_iec958_subframe; 1602 } 1603 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1604 cm->dig_pcm_status = cm->dig_status; 1605 return 0; 1606 } 1607 1608 static int snd_cmipci_capture_spdif_open(snd_pcm_substream_t * substream) 1609 { 1610 cmipci_t *cm = snd_pcm_substream_chip(substream); 1611 snd_pcm_runtime_t *runtime = substream->runtime; 1612 int err; 1613 1614 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */ 1615 return err; 1616 runtime->hw = snd_cmipci_capture_spdif; 1617 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1618 return 0; 1619 } 1620 1621 1622 /* 1623 */ 1624 1625 static int snd_cmipci_playback_close(snd_pcm_substream_t * substream) 1626 { 1627 cmipci_t *cm = snd_pcm_substream_chip(substream); 1628 close_device_check(cm, CM_OPEN_PLAYBACK); 1629 return 0; 1630 } 1631 1632 static int snd_cmipci_capture_close(snd_pcm_substream_t * substream) 1633 { 1634 cmipci_t *cm = snd_pcm_substream_chip(substream); 1635 close_device_check(cm, CM_OPEN_CAPTURE); 1636 return 0; 1637 } 1638 1639 static int snd_cmipci_playback2_close(snd_pcm_substream_t * substream) 1640 { 1641 cmipci_t *cm = snd_pcm_substream_chip(substream); 1642 close_device_check(cm, CM_OPEN_PLAYBACK2); 1643 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI); 1644 return 0; 1645 } 1646 1647 static int snd_cmipci_playback_spdif_close(snd_pcm_substream_t * substream) 1648 { 1649 cmipci_t *cm = snd_pcm_substream_chip(substream); 1650 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK); 1651 return 0; 1652 } 1653 1654 static int snd_cmipci_capture_spdif_close(snd_pcm_substream_t * substream) 1655 { 1656 cmipci_t *cm = snd_pcm_substream_chip(substream); 1657 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE); 1658 return 0; 1659 } 1660 1661 1662 /* 1663 */ 1664 1665 static snd_pcm_ops_t snd_cmipci_playback_ops = { 1666 .open = snd_cmipci_playback_open, 1667 .close = snd_cmipci_playback_close, 1668 .ioctl = snd_pcm_lib_ioctl, 1669 .hw_params = snd_cmipci_hw_params, 1670 .hw_free = snd_cmipci_playback_hw_free, 1671 .prepare = snd_cmipci_playback_prepare, 1672 .trigger = snd_cmipci_playback_trigger, 1673 .pointer = snd_cmipci_playback_pointer, 1674 }; 1675 1676 static snd_pcm_ops_t snd_cmipci_capture_ops = { 1677 .open = snd_cmipci_capture_open, 1678 .close = snd_cmipci_capture_close, 1679 .ioctl = snd_pcm_lib_ioctl, 1680 .hw_params = snd_cmipci_hw_params, 1681 .hw_free = snd_cmipci_hw_free, 1682 .prepare = snd_cmipci_capture_prepare, 1683 .trigger = snd_cmipci_capture_trigger, 1684 .pointer = snd_cmipci_capture_pointer, 1685 }; 1686 1687 static snd_pcm_ops_t snd_cmipci_playback2_ops = { 1688 .open = snd_cmipci_playback2_open, 1689 .close = snd_cmipci_playback2_close, 1690 .ioctl = snd_pcm_lib_ioctl, 1691 .hw_params = snd_cmipci_playback2_hw_params, 1692 .hw_free = snd_cmipci_hw_free, 1693 .prepare = snd_cmipci_capture_prepare, /* channel B */ 1694 .trigger = snd_cmipci_capture_trigger, /* channel B */ 1695 .pointer = snd_cmipci_capture_pointer, /* channel B */ 1696 }; 1697 1698 static snd_pcm_ops_t snd_cmipci_playback_spdif_ops = { 1699 .open = snd_cmipci_playback_spdif_open, 1700 .close = snd_cmipci_playback_spdif_close, 1701 .ioctl = snd_pcm_lib_ioctl, 1702 .hw_params = snd_cmipci_hw_params, 1703 .hw_free = snd_cmipci_playback_hw_free, 1704 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */ 1705 .trigger = snd_cmipci_playback_trigger, 1706 .pointer = snd_cmipci_playback_pointer, 1707 }; 1708 1709 static snd_pcm_ops_t snd_cmipci_capture_spdif_ops = { 1710 .open = snd_cmipci_capture_spdif_open, 1711 .close = snd_cmipci_capture_spdif_close, 1712 .ioctl = snd_pcm_lib_ioctl, 1713 .hw_params = snd_cmipci_hw_params, 1714 .hw_free = snd_cmipci_capture_spdif_hw_free, 1715 .prepare = snd_cmipci_capture_spdif_prepare, 1716 .trigger = snd_cmipci_capture_trigger, 1717 .pointer = snd_cmipci_capture_pointer, 1718 }; 1719 1720 1721 /* 1722 */ 1723 1724 static void snd_cmipci_pcm_free(snd_pcm_t *pcm) 1725 { 1726 snd_pcm_lib_preallocate_free_for_all(pcm); 1727 } 1728 1729 static int __devinit snd_cmipci_pcm_new(cmipci_t *cm, int device) 1730 { 1731 snd_pcm_t *pcm; 1732 int err; 1733 1734 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1735 if (err < 0) 1736 return err; 1737 1738 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops); 1739 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops); 1740 1741 pcm->private_data = cm; 1742 pcm->private_free = snd_cmipci_pcm_free; 1743 pcm->info_flags = 0; 1744 strcpy(pcm->name, "C-Media PCI DAC/ADC"); 1745 cm->pcm = pcm; 1746 1747 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1748 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1749 1750 return 0; 1751 } 1752 1753 static int __devinit snd_cmipci_pcm2_new(cmipci_t *cm, int device) 1754 { 1755 snd_pcm_t *pcm; 1756 int err; 1757 1758 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm); 1759 if (err < 0) 1760 return err; 1761 1762 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops); 1763 1764 pcm->private_data = cm; 1765 pcm->private_free = snd_cmipci_pcm_free; 1766 pcm->info_flags = 0; 1767 strcpy(pcm->name, "C-Media PCI 2nd DAC"); 1768 cm->pcm2 = pcm; 1769 1770 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1771 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1772 1773 return 0; 1774 } 1775 1776 static int __devinit snd_cmipci_pcm_spdif_new(cmipci_t *cm, int device) 1777 { 1778 snd_pcm_t *pcm; 1779 int err; 1780 1781 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1782 if (err < 0) 1783 return err; 1784 1785 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops); 1786 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops); 1787 1788 pcm->private_data = cm; 1789 pcm->private_free = snd_cmipci_pcm_free; 1790 pcm->info_flags = 0; 1791 strcpy(pcm->name, "C-Media PCI IEC958"); 1792 cm->pcm_spdif = pcm; 1793 1794 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1795 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1796 1797 return 0; 1798 } 1799 1800 /* 1801 * mixer interface: 1802 * - CM8338/8738 has a compatible mixer interface with SB16, but 1803 * lack of some elements like tone control, i/o gain and AGC. 1804 * - Access to native registers: 1805 * - A 3D switch 1806 * - Output mute switches 1807 */ 1808 1809 static void snd_cmipci_mixer_write(cmipci_t *s, unsigned char idx, unsigned char data) 1810 { 1811 outb(idx, s->iobase + CM_REG_SB16_ADDR); 1812 outb(data, s->iobase + CM_REG_SB16_DATA); 1813 } 1814 1815 static unsigned char snd_cmipci_mixer_read(cmipci_t *s, unsigned char idx) 1816 { 1817 unsigned char v; 1818 1819 outb(idx, s->iobase + CM_REG_SB16_ADDR); 1820 v = inb(s->iobase + CM_REG_SB16_DATA); 1821 return v; 1822 } 1823 1824 /* 1825 * general mixer element 1826 */ 1827 typedef struct cmipci_sb_reg { 1828 unsigned int left_reg, right_reg; 1829 unsigned int left_shift, right_shift; 1830 unsigned int mask; 1831 unsigned int invert: 1; 1832 unsigned int stereo: 1; 1833 } cmipci_sb_reg_t; 1834 1835 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \ 1836 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23)) 1837 1838 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \ 1839 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1840 .info = snd_cmipci_info_volume, \ 1841 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \ 1842 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \ 1843 } 1844 1845 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1) 1846 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0) 1847 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1) 1848 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0) 1849 1850 static void cmipci_sb_reg_decode(cmipci_sb_reg_t *r, unsigned long val) 1851 { 1852 r->left_reg = val & 0xff; 1853 r->right_reg = (val >> 8) & 0xff; 1854 r->left_shift = (val >> 16) & 0x07; 1855 r->right_shift = (val >> 19) & 0x07; 1856 r->invert = (val >> 22) & 1; 1857 r->stereo = (val >> 23) & 1; 1858 r->mask = (val >> 24) & 0xff; 1859 } 1860 1861 static int snd_cmipci_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo) 1862 { 1863 cmipci_sb_reg_t reg; 1864 1865 cmipci_sb_reg_decode(®, kcontrol->private_value); 1866 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1867 uinfo->count = reg.stereo + 1; 1868 uinfo->value.integer.min = 0; 1869 uinfo->value.integer.max = reg.mask; 1870 return 0; 1871 } 1872 1873 static int snd_cmipci_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1874 { 1875 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 1876 cmipci_sb_reg_t reg; 1877 int val; 1878 1879 cmipci_sb_reg_decode(®, kcontrol->private_value); 1880 spin_lock_irq(&cm->reg_lock); 1881 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; 1882 if (reg.invert) 1883 val = reg.mask - val; 1884 ucontrol->value.integer.value[0] = val; 1885 if (reg.stereo) { 1886 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; 1887 if (reg.invert) 1888 val = reg.mask - val; 1889 ucontrol->value.integer.value[1] = val; 1890 } 1891 spin_unlock_irq(&cm->reg_lock); 1892 return 0; 1893 } 1894 1895 static int snd_cmipci_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1896 { 1897 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 1898 cmipci_sb_reg_t reg; 1899 int change; 1900 int left, right, oleft, oright; 1901 1902 cmipci_sb_reg_decode(®, kcontrol->private_value); 1903 left = ucontrol->value.integer.value[0] & reg.mask; 1904 if (reg.invert) 1905 left = reg.mask - left; 1906 left <<= reg.left_shift; 1907 if (reg.stereo) { 1908 right = ucontrol->value.integer.value[1] & reg.mask; 1909 if (reg.invert) 1910 right = reg.mask - right; 1911 right <<= reg.right_shift; 1912 } else 1913 right = 0; 1914 spin_lock_irq(&cm->reg_lock); 1915 oleft = snd_cmipci_mixer_read(cm, reg.left_reg); 1916 left |= oleft & ~(reg.mask << reg.left_shift); 1917 change = left != oleft; 1918 if (reg.stereo) { 1919 if (reg.left_reg != reg.right_reg) { 1920 snd_cmipci_mixer_write(cm, reg.left_reg, left); 1921 oright = snd_cmipci_mixer_read(cm, reg.right_reg); 1922 } else 1923 oright = left; 1924 right |= oright & ~(reg.mask << reg.right_shift); 1925 change |= right != oright; 1926 snd_cmipci_mixer_write(cm, reg.right_reg, right); 1927 } else 1928 snd_cmipci_mixer_write(cm, reg.left_reg, left); 1929 spin_unlock_irq(&cm->reg_lock); 1930 return change; 1931 } 1932 1933 /* 1934 * input route (left,right) -> (left,right) 1935 */ 1936 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \ 1937 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1938 .info = snd_cmipci_info_input_sw, \ 1939 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \ 1940 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \ 1941 } 1942 1943 static int snd_cmipci_info_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo) 1944 { 1945 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1946 uinfo->count = 4; 1947 uinfo->value.integer.min = 0; 1948 uinfo->value.integer.max = 1; 1949 return 0; 1950 } 1951 1952 static int snd_cmipci_get_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1953 { 1954 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 1955 cmipci_sb_reg_t reg; 1956 int val1, val2; 1957 1958 cmipci_sb_reg_decode(®, kcontrol->private_value); 1959 spin_lock_irq(&cm->reg_lock); 1960 val1 = snd_cmipci_mixer_read(cm, reg.left_reg); 1961 val2 = snd_cmipci_mixer_read(cm, reg.right_reg); 1962 spin_unlock_irq(&cm->reg_lock); 1963 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1; 1964 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1; 1965 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1; 1966 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1; 1967 return 0; 1968 } 1969 1970 static int snd_cmipci_put_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1971 { 1972 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 1973 cmipci_sb_reg_t reg; 1974 int change; 1975 int val1, val2, oval1, oval2; 1976 1977 cmipci_sb_reg_decode(®, kcontrol->private_value); 1978 spin_lock_irq(&cm->reg_lock); 1979 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg); 1980 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg); 1981 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); 1982 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); 1983 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift; 1984 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift; 1985 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift; 1986 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift; 1987 change = val1 != oval1 || val2 != oval2; 1988 snd_cmipci_mixer_write(cm, reg.left_reg, val1); 1989 snd_cmipci_mixer_write(cm, reg.right_reg, val2); 1990 spin_unlock_irq(&cm->reg_lock); 1991 return change; 1992 } 1993 1994 /* 1995 * native mixer switches/volumes 1996 */ 1997 1998 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \ 1999 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2000 .info = snd_cmipci_info_native_mixer, \ 2001 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2002 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \ 2003 } 2004 2005 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \ 2006 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2007 .info = snd_cmipci_info_native_mixer, \ 2008 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2009 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \ 2010 } 2011 2012 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \ 2013 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2014 .info = snd_cmipci_info_native_mixer, \ 2015 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2016 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ 2017 } 2018 2019 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \ 2020 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2021 .info = snd_cmipci_info_native_mixer, \ 2022 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 2023 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ 2024 } 2025 2026 static int snd_cmipci_info_native_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 2027 { 2028 cmipci_sb_reg_t reg; 2029 2030 cmipci_sb_reg_decode(®, kcontrol->private_value); 2031 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 2032 uinfo->count = reg.stereo + 1; 2033 uinfo->value.integer.min = 0; 2034 uinfo->value.integer.max = reg.mask; 2035 return 0; 2036 2037 } 2038 2039 static int snd_cmipci_get_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2040 { 2041 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2042 cmipci_sb_reg_t reg; 2043 unsigned char oreg, val; 2044 2045 cmipci_sb_reg_decode(®, kcontrol->private_value); 2046 spin_lock_irq(&cm->reg_lock); 2047 oreg = inb(cm->iobase + reg.left_reg); 2048 val = (oreg >> reg.left_shift) & reg.mask; 2049 if (reg.invert) 2050 val = reg.mask - val; 2051 ucontrol->value.integer.value[0] = val; 2052 if (reg.stereo) { 2053 val = (oreg >> reg.right_shift) & reg.mask; 2054 if (reg.invert) 2055 val = reg.mask - val; 2056 ucontrol->value.integer.value[1] = val; 2057 } 2058 spin_unlock_irq(&cm->reg_lock); 2059 return 0; 2060 } 2061 2062 static int snd_cmipci_put_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2063 { 2064 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2065 cmipci_sb_reg_t reg; 2066 unsigned char oreg, nreg, val; 2067 2068 cmipci_sb_reg_decode(®, kcontrol->private_value); 2069 spin_lock_irq(&cm->reg_lock); 2070 oreg = inb(cm->iobase + reg.left_reg); 2071 val = ucontrol->value.integer.value[0] & reg.mask; 2072 if (reg.invert) 2073 val = reg.mask - val; 2074 nreg = oreg & ~(reg.mask << reg.left_shift); 2075 nreg |= (val << reg.left_shift); 2076 if (reg.stereo) { 2077 val = ucontrol->value.integer.value[1] & reg.mask; 2078 if (reg.invert) 2079 val = reg.mask - val; 2080 nreg &= ~(reg.mask << reg.right_shift); 2081 nreg |= (val << reg.right_shift); 2082 } 2083 outb(nreg, cm->iobase + reg.left_reg); 2084 spin_unlock_irq(&cm->reg_lock); 2085 return (nreg != oreg); 2086 } 2087 2088 /* 2089 * special case - check mixer sensitivity 2090 */ 2091 static int snd_cmipci_get_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2092 { 2093 //cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2094 return snd_cmipci_get_native_mixer(kcontrol, ucontrol); 2095 } 2096 2097 static int snd_cmipci_put_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2098 { 2099 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2100 if (cm->mixer_insensitive) { 2101 /* ignored */ 2102 return 0; 2103 } 2104 return snd_cmipci_put_native_mixer(kcontrol, ucontrol); 2105 } 2106 2107 2108 static snd_kcontrol_new_t snd_cmipci_mixers[] __devinitdata = { 2109 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31), 2110 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0), 2111 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31), 2112 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1), 2113 { /* switch with sensitivity */ 2114 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2115 .name = "PCM Playback Switch", 2116 .info = snd_cmipci_info_native_mixer, 2117 .get = snd_cmipci_get_native_mixer_sensitive, 2118 .put = snd_cmipci_put_native_mixer_sensitive, 2119 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0), 2120 }, 2121 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0), 2122 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31), 2123 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1), 2124 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5), 2125 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31), 2126 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1), 2127 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1), 2128 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31), 2129 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3), 2130 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3), 2131 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31), 2132 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0), 2133 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0), 2134 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3), 2135 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15), 2136 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0), 2137 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0), 2138 CMIPCI_MIXER_SW_MONO("Mic Boost", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), 2139 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7), 2140 }; 2141 2142 /* 2143 * other switches 2144 */ 2145 2146 typedef struct snd_cmipci_switch_args { 2147 int reg; /* register index */ 2148 unsigned int mask; /* mask bits */ 2149 unsigned int mask_on; /* mask bits to turn on */ 2150 unsigned int is_byte: 1; /* byte access? */ 2151 unsigned int ac3_sensitive: 1; /* access forbidden during non-audio operation? */ 2152 } snd_cmipci_switch_args_t; 2153 2154 static int snd_cmipci_uswitch_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 2155 { 2156 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2157 uinfo->count = 1; 2158 uinfo->value.integer.min = 0; 2159 uinfo->value.integer.max = 1; 2160 return 0; 2161 } 2162 2163 static int _snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args) 2164 { 2165 unsigned int val; 2166 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2167 2168 spin_lock_irq(&cm->reg_lock); 2169 if (args->ac3_sensitive && cm->mixer_insensitive) { 2170 ucontrol->value.integer.value[0] = 0; 2171 spin_unlock_irq(&cm->reg_lock); 2172 return 0; 2173 } 2174 if (args->is_byte) 2175 val = inb(cm->iobase + args->reg); 2176 else 2177 val = snd_cmipci_read(cm, args->reg); 2178 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0; 2179 spin_unlock_irq(&cm->reg_lock); 2180 return 0; 2181 } 2182 2183 static int snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2184 { 2185 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value; 2186 snd_assert(args != NULL, return -EINVAL); 2187 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args); 2188 } 2189 2190 static int _snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args) 2191 { 2192 unsigned int val; 2193 int change; 2194 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2195 2196 spin_lock_irq(&cm->reg_lock); 2197 if (args->ac3_sensitive && cm->mixer_insensitive) { 2198 /* ignored */ 2199 spin_unlock_irq(&cm->reg_lock); 2200 return 0; 2201 } 2202 if (args->is_byte) 2203 val = inb(cm->iobase + args->reg); 2204 else 2205 val = snd_cmipci_read(cm, args->reg); 2206 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0); 2207 if (change) { 2208 val &= ~args->mask; 2209 if (ucontrol->value.integer.value[0]) 2210 val |= args->mask_on; 2211 else 2212 val |= (args->mask & ~args->mask_on); 2213 if (args->is_byte) 2214 outb((unsigned char)val, cm->iobase + args->reg); 2215 else 2216 snd_cmipci_write(cm, args->reg, val); 2217 } 2218 spin_unlock_irq(&cm->reg_lock); 2219 return change; 2220 } 2221 2222 static int snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2223 { 2224 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value; 2225 snd_assert(args != NULL, return -EINVAL); 2226 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args); 2227 } 2228 2229 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \ 2230 static snd_cmipci_switch_args_t cmipci_switch_arg_##sname = { \ 2231 .reg = xreg, \ 2232 .mask = xmask, \ 2233 .mask_on = xmask_on, \ 2234 .is_byte = xis_byte, \ 2235 .ac3_sensitive = xac3, \ 2236 } 2237 2238 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \ 2239 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3) 2240 2241 #if 0 /* these will be controlled in pcm device */ 2242 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0); 2243 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0); 2244 #endif 2245 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0); 2246 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0); 2247 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0); 2248 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1); 2249 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0); 2250 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0); 2251 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1); 2252 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */ 2253 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1); 2254 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1); 2255 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0); 2256 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */ 2257 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0); 2258 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0); 2259 #if CM_CH_PLAY == 1 2260 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */ 2261 #else 2262 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0); 2263 #endif 2264 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0); 2265 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0); 2266 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0); 2267 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */ 2268 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0); 2269 2270 #define DEFINE_SWITCH(sname, stype, sarg) \ 2271 { .name = sname, \ 2272 .iface = stype, \ 2273 .info = snd_cmipci_uswitch_info, \ 2274 .get = snd_cmipci_uswitch_get, \ 2275 .put = snd_cmipci_uswitch_put, \ 2276 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\ 2277 } 2278 2279 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg) 2280 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg) 2281 2282 2283 /* 2284 * callbacks for spdif output switch 2285 * needs toggle two registers.. 2286 */ 2287 static int snd_cmipci_spdout_enable_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2288 { 2289 int changed; 2290 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); 2291 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); 2292 return changed; 2293 } 2294 2295 static int snd_cmipci_spdout_enable_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2296 { 2297 cmipci_t *chip = snd_kcontrol_chip(kcontrol); 2298 int changed; 2299 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); 2300 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); 2301 if (changed) { 2302 if (ucontrol->value.integer.value[0]) { 2303 if (chip->spdif_playback_avail) 2304 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2305 } else { 2306 if (chip->spdif_playback_avail) 2307 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2308 } 2309 } 2310 chip->spdif_playback_enabled = ucontrol->value.integer.value[0]; 2311 return changed; 2312 } 2313 2314 2315 static int snd_cmipci_line_in_mode_info(snd_kcontrol_t *kcontrol, 2316 snd_ctl_elem_info_t *uinfo) 2317 { 2318 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2319 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" }; 2320 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2321 uinfo->count = 1; 2322 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2; 2323 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2324 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2325 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2326 return 0; 2327 } 2328 2329 static inline unsigned int get_line_in_mode(cmipci_t *cm) 2330 { 2331 unsigned int val; 2332 if (cm->chip_version >= 39) { 2333 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL); 2334 if (val & CM_LINE_AS_BASS) 2335 return 2; 2336 } 2337 val = snd_cmipci_read_b(cm, CM_REG_MIXER1); 2338 if (val & CM_SPK4) 2339 return 1; 2340 return 0; 2341 } 2342 2343 static int snd_cmipci_line_in_mode_get(snd_kcontrol_t *kcontrol, 2344 snd_ctl_elem_value_t *ucontrol) 2345 { 2346 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2347 2348 spin_lock_irq(&cm->reg_lock); 2349 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm); 2350 spin_unlock_irq(&cm->reg_lock); 2351 return 0; 2352 } 2353 2354 static int snd_cmipci_line_in_mode_put(snd_kcontrol_t *kcontrol, 2355 snd_ctl_elem_value_t *ucontrol) 2356 { 2357 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2358 int change; 2359 2360 spin_lock_irq(&cm->reg_lock); 2361 if (ucontrol->value.enumerated.item[0] == 2) 2362 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); 2363 else 2364 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); 2365 if (ucontrol->value.enumerated.item[0] == 1) 2366 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4); 2367 else 2368 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4); 2369 spin_unlock_irq(&cm->reg_lock); 2370 return change; 2371 } 2372 2373 static int snd_cmipci_mic_in_mode_info(snd_kcontrol_t *kcontrol, 2374 snd_ctl_elem_info_t *uinfo) 2375 { 2376 static char *texts[2] = { "Mic-In", "Center/LFE Output" }; 2377 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2378 uinfo->count = 1; 2379 uinfo->value.enumerated.items = 2; 2380 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2381 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2382 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2383 return 0; 2384 } 2385 2386 static int snd_cmipci_mic_in_mode_get(snd_kcontrol_t *kcontrol, 2387 snd_ctl_elem_value_t *ucontrol) 2388 { 2389 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2390 /* same bit as spdi_phase */ 2391 spin_lock_irq(&cm->reg_lock); 2392 ucontrol->value.enumerated.item[0] = 2393 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0; 2394 spin_unlock_irq(&cm->reg_lock); 2395 return 0; 2396 } 2397 2398 static int snd_cmipci_mic_in_mode_put(snd_kcontrol_t *kcontrol, 2399 snd_ctl_elem_value_t *ucontrol) 2400 { 2401 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2402 int change; 2403 2404 spin_lock_irq(&cm->reg_lock); 2405 if (ucontrol->value.enumerated.item[0]) 2406 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); 2407 else 2408 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); 2409 spin_unlock_irq(&cm->reg_lock); 2410 return change; 2411 } 2412 2413 /* both for CM8338/8738 */ 2414 static snd_kcontrol_new_t snd_cmipci_mixer_switches[] __devinitdata = { 2415 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch), 2416 { 2417 .name = "Line-In Mode", 2418 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2419 .info = snd_cmipci_line_in_mode_info, 2420 .get = snd_cmipci_line_in_mode_get, 2421 .put = snd_cmipci_line_in_mode_put, 2422 }, 2423 }; 2424 2425 /* for non-multichannel chips */ 2426 static snd_kcontrol_new_t snd_cmipci_nomulti_switch __devinitdata = 2427 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac); 2428 2429 /* only for CM8738 */ 2430 static snd_kcontrol_new_t snd_cmipci_8738_mixer_switches[] __devinitdata = { 2431 #if 0 /* controlled in pcm device */ 2432 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in), 2433 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out), 2434 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac), 2435 #endif 2436 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable), 2437 { .name = "IEC958 Output Switch", 2438 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2439 .info = snd_cmipci_uswitch_info, 2440 .get = snd_cmipci_spdout_enable_get, 2441 .put = snd_cmipci_spdout_enable_put, 2442 }, 2443 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid), 2444 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright), 2445 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v), 2446 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k), 2447 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop), 2448 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor), 2449 }; 2450 2451 /* only for model 033/037 */ 2452 static snd_kcontrol_new_t snd_cmipci_old_mixer_switches[] __devinitdata = { 2453 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out), 2454 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase), 2455 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1), 2456 }; 2457 2458 /* only for model 039 or later */ 2459 static snd_kcontrol_new_t snd_cmipci_extra_mixer_switches[] __devinitdata = { 2460 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2), 2461 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2), 2462 { 2463 .name = "Mic-In Mode", 2464 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2465 .info = snd_cmipci_mic_in_mode_info, 2466 .get = snd_cmipci_mic_in_mode_get, 2467 .put = snd_cmipci_mic_in_mode_put, 2468 } 2469 }; 2470 2471 /* card control switches */ 2472 static snd_kcontrol_new_t snd_cmipci_control_switches[] __devinitdata = { 2473 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */ 2474 DEFINE_CARD_SWITCH("Modem", modem), 2475 }; 2476 2477 2478 static int __devinit snd_cmipci_mixer_new(cmipci_t *cm, int pcm_spdif_device) 2479 { 2480 snd_card_t *card; 2481 snd_kcontrol_new_t *sw; 2482 snd_kcontrol_t *kctl; 2483 unsigned int idx; 2484 int err; 2485 2486 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL); 2487 2488 card = cm->card; 2489 2490 strcpy(card->mixername, "CMedia PCI"); 2491 2492 spin_lock_irq(&cm->reg_lock); 2493 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */ 2494 spin_unlock_irq(&cm->reg_lock); 2495 2496 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) { 2497 if (cm->chip_version == 68) { // 8768 has no PCM volume 2498 if (!strcmp(snd_cmipci_mixers[idx].name, 2499 "PCM Playback Volume")) 2500 continue; 2501 } 2502 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0) 2503 return err; 2504 } 2505 2506 /* mixer switches */ 2507 sw = snd_cmipci_mixer_switches; 2508 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) { 2509 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2510 if (err < 0) 2511 return err; 2512 } 2513 if (! cm->can_multi_ch) { 2514 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm)); 2515 if (err < 0) 2516 return err; 2517 } 2518 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 || 2519 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) { 2520 sw = snd_cmipci_8738_mixer_switches; 2521 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) { 2522 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2523 if (err < 0) 2524 return err; 2525 } 2526 if (cm->can_ac3_hw) { 2527 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0) 2528 return err; 2529 kctl->id.device = pcm_spdif_device; 2530 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0) 2531 return err; 2532 kctl->id.device = pcm_spdif_device; 2533 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0) 2534 return err; 2535 kctl->id.device = pcm_spdif_device; 2536 } 2537 if (cm->chip_version <= 37) { 2538 sw = snd_cmipci_old_mixer_switches; 2539 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) { 2540 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2541 if (err < 0) 2542 return err; 2543 } 2544 } 2545 } 2546 if (cm->chip_version >= 39) { 2547 sw = snd_cmipci_extra_mixer_switches; 2548 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) { 2549 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2550 if (err < 0) 2551 return err; 2552 } 2553 } 2554 2555 /* card switches */ 2556 sw = snd_cmipci_control_switches; 2557 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) { 2558 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2559 if (err < 0) 2560 return err; 2561 } 2562 2563 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) { 2564 snd_ctl_elem_id_t id; 2565 snd_kcontrol_t *ctl; 2566 memset(&id, 0, sizeof(id)); 2567 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2568 strcpy(id.name, cm_saved_mixer[idx].name); 2569 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL) 2570 cm->mixer_res_ctl[idx] = ctl; 2571 } 2572 2573 return 0; 2574 } 2575 2576 2577 /* 2578 * proc interface 2579 */ 2580 2581 #ifdef CONFIG_PROC_FS 2582 static void snd_cmipci_proc_read(snd_info_entry_t *entry, 2583 snd_info_buffer_t *buffer) 2584 { 2585 cmipci_t *cm = entry->private_data; 2586 int i; 2587 2588 snd_iprintf(buffer, "%s\n\n", cm->card->longname); 2589 for (i = 0; i < 0x40; i++) { 2590 int v = inb(cm->iobase + i); 2591 if (i % 4 == 0) 2592 snd_iprintf(buffer, "%02x: ", i); 2593 snd_iprintf(buffer, "%02x", v); 2594 if (i % 4 == 3) 2595 snd_iprintf(buffer, "\n"); 2596 else 2597 snd_iprintf(buffer, " "); 2598 } 2599 } 2600 2601 static void __devinit snd_cmipci_proc_init(cmipci_t *cm) 2602 { 2603 snd_info_entry_t *entry; 2604 2605 if (! snd_card_proc_new(cm->card, "cmipci", &entry)) 2606 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read); 2607 } 2608 #else /* !CONFIG_PROC_FS */ 2609 static inline void snd_cmipci_proc_init(cmipci_t *cm) {} 2610 #endif 2611 2612 2613 static struct pci_device_id snd_cmipci_ids[] = { 2614 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2615 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2616 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2617 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2618 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2619 {0,}, 2620 }; 2621 2622 2623 /* 2624 * check chip version and capabilities 2625 * driver name is modified according to the chip model 2626 */ 2627 static void __devinit query_chip(cmipci_t *cm) 2628 { 2629 unsigned int detect; 2630 2631 /* check reg 0Ch, bit 24-31 */ 2632 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2; 2633 if (! detect) { 2634 /* check reg 08h, bit 24-28 */ 2635 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1; 2636 if (! detect) { 2637 cm->chip_version = 33; 2638 cm->max_channels = 2; 2639 if (cm->do_soft_ac3) 2640 cm->can_ac3_sw = 1; 2641 else 2642 cm->can_ac3_hw = 1; 2643 cm->has_dual_dac = 1; 2644 } else { 2645 cm->chip_version = 37; 2646 cm->max_channels = 2; 2647 cm->can_ac3_hw = 1; 2648 cm->has_dual_dac = 1; 2649 } 2650 } else { 2651 /* check reg 0Ch, bit 26 */ 2652 if (detect & CM_CHIP_8768) { 2653 cm->chip_version = 68; 2654 cm->max_channels = 8; 2655 cm->can_ac3_hw = 1; 2656 cm->has_dual_dac = 1; 2657 cm->can_multi_ch = 1; 2658 } else if (detect & CM_CHIP_055) { 2659 cm->chip_version = 55; 2660 cm->max_channels = 6; 2661 cm->can_ac3_hw = 1; 2662 cm->has_dual_dac = 1; 2663 cm->can_multi_ch = 1; 2664 } else if (detect & CM_CHIP_039) { 2665 cm->chip_version = 39; 2666 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */ 2667 cm->max_channels = 6; 2668 else 2669 cm->max_channels = 4; 2670 cm->can_ac3_hw = 1; 2671 cm->has_dual_dac = 1; 2672 cm->can_multi_ch = 1; 2673 } else { 2674 printk(KERN_ERR "chip %x version not supported\n", detect); 2675 } 2676 } 2677 } 2678 2679 #ifdef SUPPORT_JOYSTICK 2680 static int __devinit snd_cmipci_create_gameport(cmipci_t *cm, int dev) 2681 { 2682 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */ 2683 struct gameport *gp; 2684 struct resource *r = NULL; 2685 int i, io_port = 0; 2686 2687 if (joystick_port[dev] == 0) 2688 return -ENODEV; 2689 2690 if (joystick_port[dev] == 1) { /* auto-detect */ 2691 for (i = 0; ports[i]; i++) { 2692 io_port = ports[i]; 2693 r = request_region(io_port, 1, "CMIPCI gameport"); 2694 if (r) 2695 break; 2696 } 2697 } else { 2698 io_port = joystick_port[dev]; 2699 r = request_region(io_port, 1, "CMIPCI gameport"); 2700 } 2701 2702 if (!r) { 2703 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n"); 2704 return -EBUSY; 2705 } 2706 2707 cm->gameport = gp = gameport_allocate_port(); 2708 if (!gp) { 2709 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n"); 2710 release_resource(r); 2711 kfree_nocheck(r); 2712 return -ENOMEM; 2713 } 2714 gameport_set_name(gp, "C-Media Gameport"); 2715 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci)); 2716 gameport_set_dev_parent(gp, &cm->pci->dev); 2717 gp->io = io_port; 2718 gameport_set_port_data(gp, r); 2719 2720 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2721 2722 gameport_register_port(cm->gameport); 2723 2724 return 0; 2725 } 2726 2727 static void snd_cmipci_free_gameport(cmipci_t *cm) 2728 { 2729 if (cm->gameport) { 2730 struct resource *r = gameport_get_port_data(cm->gameport); 2731 2732 gameport_unregister_port(cm->gameport); 2733 cm->gameport = NULL; 2734 2735 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2736 release_resource(r); 2737 kfree_nocheck(r); 2738 } 2739 } 2740 #else 2741 static inline int snd_cmipci_create_gameport(cmipci_t *cm, int dev) { return -ENOSYS; } 2742 static inline void snd_cmipci_free_gameport(cmipci_t *cm) { } 2743 #endif 2744 2745 static int snd_cmipci_free(cmipci_t *cm) 2746 { 2747 if (cm->irq >= 0) { 2748 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2749 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); 2750 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 2751 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 2752 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 2753 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 2754 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 2755 2756 /* reset mixer */ 2757 snd_cmipci_mixer_write(cm, 0, 0); 2758 2759 synchronize_irq(cm->irq); 2760 2761 free_irq(cm->irq, (void *)cm); 2762 } 2763 2764 snd_cmipci_free_gameport(cm); 2765 pci_release_regions(cm->pci); 2766 pci_disable_device(cm->pci); 2767 kfree(cm); 2768 return 0; 2769 } 2770 2771 static int snd_cmipci_dev_free(snd_device_t *device) 2772 { 2773 cmipci_t *cm = device->device_data; 2774 return snd_cmipci_free(cm); 2775 } 2776 2777 static int __devinit snd_cmipci_create(snd_card_t *card, struct pci_dev *pci, 2778 int dev, cmipci_t **rcmipci) 2779 { 2780 cmipci_t *cm; 2781 int err; 2782 static snd_device_ops_t ops = { 2783 .dev_free = snd_cmipci_dev_free, 2784 }; 2785 unsigned int val = 0; 2786 long iomidi = mpu_port[dev]; 2787 long iosynth = fm_port[dev]; 2788 int pcm_index, pcm_spdif_index; 2789 static struct pci_device_id intel_82437vx[] = { 2790 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) }, 2791 { }, 2792 }; 2793 2794 *rcmipci = NULL; 2795 2796 if ((err = pci_enable_device(pci)) < 0) 2797 return err; 2798 2799 cm = kcalloc(1, sizeof(*cm), GFP_KERNEL); 2800 if (cm == NULL) { 2801 pci_disable_device(pci); 2802 return -ENOMEM; 2803 } 2804 2805 spin_lock_init(&cm->reg_lock); 2806 init_MUTEX(&cm->open_mutex); 2807 cm->device = pci->device; 2808 cm->card = card; 2809 cm->pci = pci; 2810 cm->irq = -1; 2811 cm->channel[0].ch = 0; 2812 cm->channel[1].ch = 1; 2813 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */ 2814 2815 if ((err = pci_request_regions(pci, card->driver)) < 0) { 2816 kfree(cm); 2817 pci_disable_device(pci); 2818 return err; 2819 } 2820 cm->iobase = pci_resource_start(pci, 0); 2821 2822 if (request_irq(pci->irq, snd_cmipci_interrupt, SA_INTERRUPT|SA_SHIRQ, card->driver, (void *)cm)) { 2823 snd_printk("unable to grab IRQ %d\n", pci->irq); 2824 snd_cmipci_free(cm); 2825 return -EBUSY; 2826 } 2827 cm->irq = pci->irq; 2828 2829 pci_set_master(cm->pci); 2830 2831 /* 2832 * check chip version, max channels and capabilities 2833 */ 2834 2835 cm->chip_version = 0; 2836 cm->max_channels = 2; 2837 cm->do_soft_ac3 = soft_ac3[dev]; 2838 2839 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A && 2840 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B) 2841 query_chip(cm); 2842 /* added -MCx suffix for chip supporting multi-channels */ 2843 if (cm->can_multi_ch) 2844 sprintf(cm->card->driver + strlen(cm->card->driver), 2845 "-MC%d", cm->max_channels); 2846 else if (cm->can_ac3_sw) 2847 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC"); 2848 2849 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 2850 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 2851 2852 #if CM_CH_PLAY == 1 2853 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */ 2854 #else 2855 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */ 2856 #endif 2857 2858 /* initialize codec registers */ 2859 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 2860 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 2861 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 2862 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 2863 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 2864 2865 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0); 2866 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D); 2867 #if CM_CH_PLAY == 1 2868 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 2869 #else 2870 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 2871 #endif 2872 /* Set Bus Master Request */ 2873 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ); 2874 2875 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */ 2876 switch (pci->device) { 2877 case PCI_DEVICE_ID_CMEDIA_CM8738: 2878 case PCI_DEVICE_ID_CMEDIA_CM8738B: 2879 if (!pci_dev_present(intel_82437vx)) 2880 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX); 2881 break; 2882 default: 2883 break; 2884 } 2885 2886 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) { 2887 snd_cmipci_free(cm); 2888 return err; 2889 } 2890 2891 /* set MPU address */ 2892 switch (iomidi) { 2893 case 0x320: val = CM_VMPU_320; break; 2894 case 0x310: val = CM_VMPU_310; break; 2895 case 0x300: val = CM_VMPU_300; break; 2896 case 0x330: val = CM_VMPU_330; break; 2897 default: 2898 iomidi = 0; break; 2899 } 2900 if (iomidi > 0) { 2901 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 2902 /* enable UART */ 2903 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); 2904 } 2905 2906 /* set FM address */ 2907 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; 2908 switch (iosynth) { 2909 case 0x3E8: val |= CM_FMSEL_3E8; break; 2910 case 0x3E0: val |= CM_FMSEL_3E0; break; 2911 case 0x3C8: val |= CM_FMSEL_3C8; break; 2912 case 0x388: val |= CM_FMSEL_388; break; 2913 default: 2914 iosynth = 0; break; 2915 } 2916 if (iosynth > 0) { 2917 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 2918 /* enable FM */ 2919 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2920 2921 if (snd_opl3_create(card, iosynth, iosynth + 2, 2922 OPL3_HW_OPL3, 0, &cm->opl3) < 0) { 2923 printk(KERN_ERR "cmipci: no OPL device at 0x%lx, skipping...\n", iosynth); 2924 iosynth = 0; 2925 } else { 2926 if ((err = snd_opl3_hwdep_new(cm->opl3, 0, 1, &cm->opl3hwdep)) < 0) { 2927 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n"); 2928 return err; 2929 } 2930 } 2931 } 2932 if (! iosynth) { 2933 /* disable FM */ 2934 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val & ~CM_FMSEL_MASK); 2935 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2936 } 2937 2938 /* reset mixer */ 2939 snd_cmipci_mixer_write(cm, 0, 0); 2940 2941 snd_cmipci_proc_init(cm); 2942 2943 /* create pcm devices */ 2944 pcm_index = pcm_spdif_index = 0; 2945 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0) 2946 return err; 2947 pcm_index++; 2948 if (cm->has_dual_dac) { 2949 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0) 2950 return err; 2951 pcm_index++; 2952 } 2953 if (cm->can_ac3_hw || cm->can_ac3_sw) { 2954 pcm_spdif_index = pcm_index; 2955 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0) 2956 return err; 2957 } 2958 2959 /* create mixer interface & switches */ 2960 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0) 2961 return err; 2962 2963 if (iomidi > 0) { 2964 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, 2965 iomidi, 0, 2966 cm->irq, 0, &cm->rmidi)) < 0) { 2967 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi); 2968 } 2969 } 2970 2971 #ifdef USE_VAR48KRATE 2972 for (val = 0; val < ARRAY_SIZE(rates); val++) 2973 snd_cmipci_set_pll(cm, rates[val], val); 2974 2975 /* 2976 * (Re-)Enable external switch spdo_48k 2977 */ 2978 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97); 2979 #endif /* USE_VAR48KRATE */ 2980 2981 if (snd_cmipci_create_gameport(cm, dev) < 0) 2982 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2983 2984 snd_card_set_dev(card, &pci->dev); 2985 2986 *rcmipci = cm; 2987 return 0; 2988 } 2989 2990 /* 2991 */ 2992 2993 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids); 2994 2995 static int __devinit snd_cmipci_probe(struct pci_dev *pci, 2996 const struct pci_device_id *pci_id) 2997 { 2998 static int dev; 2999 snd_card_t *card; 3000 cmipci_t *cm; 3001 int err; 3002 3003 if (dev >= SNDRV_CARDS) 3004 return -ENODEV; 3005 if (! enable[dev]) { 3006 dev++; 3007 return -ENOENT; 3008 } 3009 3010 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 3011 if (card == NULL) 3012 return -ENOMEM; 3013 3014 switch (pci->device) { 3015 case PCI_DEVICE_ID_CMEDIA_CM8738: 3016 case PCI_DEVICE_ID_CMEDIA_CM8738B: 3017 strcpy(card->driver, "CMI8738"); 3018 break; 3019 case PCI_DEVICE_ID_CMEDIA_CM8338A: 3020 case PCI_DEVICE_ID_CMEDIA_CM8338B: 3021 strcpy(card->driver, "CMI8338"); 3022 break; 3023 default: 3024 strcpy(card->driver, "CMIPCI"); 3025 break; 3026 } 3027 3028 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) { 3029 snd_card_free(card); 3030 return err; 3031 } 3032 3033 sprintf(card->shortname, "C-Media PCI %s", card->driver); 3034 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i", 3035 card->shortname, 3036 cm->chip_version, 3037 cm->iobase, 3038 cm->irq); 3039 3040 //snd_printd("%s is detected\n", card->longname); 3041 3042 if ((err = snd_card_register(card)) < 0) { 3043 snd_card_free(card); 3044 return err; 3045 } 3046 pci_set_drvdata(pci, card); 3047 dev++; 3048 return 0; 3049 3050 } 3051 3052 static void __devexit snd_cmipci_remove(struct pci_dev *pci) 3053 { 3054 snd_card_free(pci_get_drvdata(pci)); 3055 pci_set_drvdata(pci, NULL); 3056 } 3057 3058 3059 static struct pci_driver driver = { 3060 .name = "C-Media PCI", 3061 .id_table = snd_cmipci_ids, 3062 .probe = snd_cmipci_probe, 3063 .remove = __devexit_p(snd_cmipci_remove), 3064 }; 3065 3066 static int __init alsa_card_cmipci_init(void) 3067 { 3068 return pci_register_driver(&driver); 3069 } 3070 3071 static void __exit alsa_card_cmipci_exit(void) 3072 { 3073 pci_unregister_driver(&driver); 3074 } 3075 3076 module_init(alsa_card_cmipci_init) 3077 module_exit(alsa_card_cmipci_exit) 3078