1 /****************************************************************************** 2 3 AudioScience HPI driver 4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of version 2 of the GNU General Public License as 8 published by the Free Software Foundation; 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 19 Hardware Programming Interface (HPI) for AudioScience 20 ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters. 21 These PCI and PCIe bus adapters are based on a 22 TMS320C6205 PCI bus mastering DSP, 23 and (except ASI50xx) TI TMS320C6xxx floating point DSP 24 25 Exported function: 26 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) 27 28 (C) Copyright AudioScience Inc. 1998-2010 29 *******************************************************************************/ 30 #define SOURCEFILE_NAME "hpi6205.c" 31 32 #include "hpi_internal.h" 33 #include "hpimsginit.h" 34 #include "hpidebug.h" 35 #include "hpi6205.h" 36 #include "hpidspcd.h" 37 #include "hpicmn.h" 38 39 /*****************************************************************************/ 40 /* HPI6205 specific error codes */ 41 #define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */ 42 43 /* operational/messaging errors */ 44 #define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015 45 #define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016 46 47 /* initialization/bootload errors */ 48 #define HPI6205_ERROR_6205_NO_IRQ 1002 49 #define HPI6205_ERROR_6205_INIT_FAILED 1003 50 #define HPI6205_ERROR_6205_REG 1006 51 #define HPI6205_ERROR_6205_DSPPAGE 1007 52 #define HPI6205_ERROR_C6713_HPIC 1009 53 #define HPI6205_ERROR_C6713_HPIA 1010 54 #define HPI6205_ERROR_C6713_PLL 1011 55 #define HPI6205_ERROR_DSP_INTMEM 1012 56 #define HPI6205_ERROR_DSP_EXTMEM 1013 57 #define HPI6205_ERROR_DSP_PLD 1014 58 #define HPI6205_ERROR_6205_EEPROM 1017 59 #define HPI6205_ERROR_DSP_EMIF 1018 60 61 /*****************************************************************************/ 62 /* for C6205 PCI i/f */ 63 /* Host Status Register (HSR) bitfields */ 64 #define C6205_HSR_INTSRC 0x01 65 #define C6205_HSR_INTAVAL 0x02 66 #define C6205_HSR_INTAM 0x04 67 #define C6205_HSR_CFGERR 0x08 68 #define C6205_HSR_EEREAD 0x10 69 /* Host-to-DSP Control Register (HDCR) bitfields */ 70 #define C6205_HDCR_WARMRESET 0x01 71 #define C6205_HDCR_DSPINT 0x02 72 #define C6205_HDCR_PCIBOOT 0x04 73 /* DSP Page Register (DSPP) bitfields, */ 74 /* defines 4 Mbyte page that BAR0 points to */ 75 #define C6205_DSPP_MAP1 0x400 76 77 /* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP. 78 * BAR1 maps to non-prefetchable 8 Mbyte memory block 79 * of DSP memory mapped registers (starting at 0x01800000). 80 * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this 81 * needs to be added to the BAR1 base address set in the PCI config reg 82 */ 83 #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L) 84 #define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET) 85 #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4) 86 #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8) 87 88 /* used to control LED (revA) and reset C6713 (revB) */ 89 #define C6205_BAR0_TIMER1_CTL (0x01980000L) 90 91 /* For first 6713 in CE1 space, using DA17,16,2 */ 92 #define HPICL_ADDR 0x01400000L 93 #define HPICH_ADDR 0x01400004L 94 #define HPIAL_ADDR 0x01410000L 95 #define HPIAH_ADDR 0x01410004L 96 #define HPIDIL_ADDR 0x01420000L 97 #define HPIDIH_ADDR 0x01420004L 98 #define HPIDL_ADDR 0x01430000L 99 #define HPIDH_ADDR 0x01430004L 100 101 #define C6713_EMIF_GCTL 0x01800000 102 #define C6713_EMIF_CE1 0x01800004 103 #define C6713_EMIF_CE0 0x01800008 104 #define C6713_EMIF_CE2 0x01800010 105 #define C6713_EMIF_CE3 0x01800014 106 #define C6713_EMIF_SDRAMCTL 0x01800018 107 #define C6713_EMIF_SDRAMTIMING 0x0180001C 108 #define C6713_EMIF_SDRAMEXT 0x01800020 109 110 struct hpi_hw_obj { 111 /* PCI registers */ 112 __iomem u32 *prHSR; 113 __iomem u32 *prHDCR; 114 __iomem u32 *prDSPP; 115 116 u32 dsp_page; 117 118 struct consistent_dma_area h_locked_mem; 119 struct bus_master_interface *p_interface_buffer; 120 121 u16 flag_outstream_just_reset[HPI_MAX_STREAMS]; 122 /* a non-NULL handle means there is an HPI allocated buffer */ 123 struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS]; 124 struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS]; 125 /* non-zero size means a buffer exists, may be external */ 126 u32 instream_host_buffer_size[HPI_MAX_STREAMS]; 127 u32 outstream_host_buffer_size[HPI_MAX_STREAMS]; 128 129 struct consistent_dma_area h_control_cache; 130 struct consistent_dma_area h_async_event_buffer; 131 /* struct hpi_control_cache_single *pControlCache; */ 132 struct hpi_async_event *p_async_event_buffer; 133 struct hpi_control_cache *p_cache; 134 }; 135 136 /*****************************************************************************/ 137 /* local prototypes */ 138 139 #define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write) 140 141 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us); 142 143 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd); 144 145 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 146 u32 *pos_error_code); 147 148 static u16 message_response_sequence(struct hpi_adapter_obj *pao, 149 struct hpi_message *phm, struct hpi_response *phr); 150 151 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 152 struct hpi_response *phr); 153 154 #define HPI6205_TIMEOUT 1000000 155 156 static void subsys_create_adapter(struct hpi_message *phm, 157 struct hpi_response *phr); 158 static void subsys_delete_adapter(struct hpi_message *phm, 159 struct hpi_response *phr); 160 161 static u16 create_adapter_obj(struct hpi_adapter_obj *pao, 162 u32 *pos_error_code); 163 164 static void delete_adapter_obj(struct hpi_adapter_obj *pao); 165 166 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, 167 struct hpi_message *phm, struct hpi_response *phr); 168 169 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, 170 struct hpi_message *phm, struct hpi_response *phr); 171 172 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, 173 struct hpi_message *phm, struct hpi_response *phr); 174 static void outstream_write(struct hpi_adapter_obj *pao, 175 struct hpi_message *phm, struct hpi_response *phr); 176 177 static void outstream_get_info(struct hpi_adapter_obj *pao, 178 struct hpi_message *phm, struct hpi_response *phr); 179 180 static void outstream_start(struct hpi_adapter_obj *pao, 181 struct hpi_message *phm, struct hpi_response *phr); 182 183 static void outstream_open(struct hpi_adapter_obj *pao, 184 struct hpi_message *phm, struct hpi_response *phr); 185 186 static void outstream_reset(struct hpi_adapter_obj *pao, 187 struct hpi_message *phm, struct hpi_response *phr); 188 189 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, 190 struct hpi_message *phm, struct hpi_response *phr); 191 192 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, 193 struct hpi_message *phm, struct hpi_response *phr); 194 195 static void instream_host_buffer_free(struct hpi_adapter_obj *pao, 196 struct hpi_message *phm, struct hpi_response *phr); 197 198 static void instream_read(struct hpi_adapter_obj *pao, 199 struct hpi_message *phm, struct hpi_response *phr); 200 201 static void instream_get_info(struct hpi_adapter_obj *pao, 202 struct hpi_message *phm, struct hpi_response *phr); 203 204 static void instream_start(struct hpi_adapter_obj *pao, 205 struct hpi_message *phm, struct hpi_response *phr); 206 207 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, 208 u32 address); 209 210 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, 211 int dsp_index, u32 address, u32 data); 212 213 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, 214 int dsp_index); 215 216 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, 217 u32 address, u32 length); 218 219 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, 220 int dsp_index); 221 222 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, 223 int dsp_index); 224 225 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index); 226 227 /*****************************************************************************/ 228 229 static void subsys_message(struct hpi_message *phm, struct hpi_response *phr) 230 { 231 switch (phm->function) { 232 case HPI_SUBSYS_CREATE_ADAPTER: 233 subsys_create_adapter(phm, phr); 234 break; 235 case HPI_SUBSYS_DELETE_ADAPTER: 236 subsys_delete_adapter(phm, phr); 237 break; 238 default: 239 phr->error = HPI_ERROR_INVALID_FUNC; 240 break; 241 } 242 } 243 244 static void control_message(struct hpi_adapter_obj *pao, 245 struct hpi_message *phm, struct hpi_response *phr) 246 { 247 248 struct hpi_hw_obj *phw = pao->priv; 249 u16 pending_cache_error = 0; 250 251 switch (phm->function) { 252 case HPI_CONTROL_GET_STATE: 253 if (pao->has_control_cache) { 254 rmb(); /* make sure we see updates DMAed from DSP */ 255 if (hpi_check_control_cache(phw->p_cache, phm, phr)) { 256 break; 257 } else if (phm->u.c.attribute == HPI_METER_PEAK) { 258 pending_cache_error = 259 HPI_ERROR_CONTROL_CACHING; 260 } 261 } 262 hw_message(pao, phm, phr); 263 if (pending_cache_error && !phr->error) 264 phr->error = pending_cache_error; 265 break; 266 case HPI_CONTROL_GET_INFO: 267 hw_message(pao, phm, phr); 268 break; 269 case HPI_CONTROL_SET_STATE: 270 hw_message(pao, phm, phr); 271 if (pao->has_control_cache) 272 hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm, 273 phr); 274 break; 275 default: 276 phr->error = HPI_ERROR_INVALID_FUNC; 277 break; 278 } 279 } 280 281 static void adapter_message(struct hpi_adapter_obj *pao, 282 struct hpi_message *phm, struct hpi_response *phr) 283 { 284 switch (phm->function) { 285 default: 286 hw_message(pao, phm, phr); 287 break; 288 } 289 } 290 291 static void outstream_message(struct hpi_adapter_obj *pao, 292 struct hpi_message *phm, struct hpi_response *phr) 293 { 294 295 if (phm->obj_index >= HPI_MAX_STREAMS) { 296 phr->error = HPI_ERROR_INVALID_STREAM; 297 HPI_DEBUG_LOG(WARNING, 298 "Message referencing invalid stream %d " 299 "on adapter index %d\n", phm->obj_index, 300 phm->adapter_index); 301 return; 302 } 303 304 switch (phm->function) { 305 case HPI_OSTREAM_WRITE: 306 outstream_write(pao, phm, phr); 307 break; 308 case HPI_OSTREAM_GET_INFO: 309 outstream_get_info(pao, phm, phr); 310 break; 311 case HPI_OSTREAM_HOSTBUFFER_ALLOC: 312 outstream_host_buffer_allocate(pao, phm, phr); 313 break; 314 case HPI_OSTREAM_HOSTBUFFER_GET_INFO: 315 outstream_host_buffer_get_info(pao, phm, phr); 316 break; 317 case HPI_OSTREAM_HOSTBUFFER_FREE: 318 outstream_host_buffer_free(pao, phm, phr); 319 break; 320 case HPI_OSTREAM_START: 321 outstream_start(pao, phm, phr); 322 break; 323 case HPI_OSTREAM_OPEN: 324 outstream_open(pao, phm, phr); 325 break; 326 case HPI_OSTREAM_RESET: 327 outstream_reset(pao, phm, phr); 328 break; 329 default: 330 hw_message(pao, phm, phr); 331 break; 332 } 333 } 334 335 static void instream_message(struct hpi_adapter_obj *pao, 336 struct hpi_message *phm, struct hpi_response *phr) 337 { 338 339 if (phm->obj_index >= HPI_MAX_STREAMS) { 340 phr->error = HPI_ERROR_INVALID_STREAM; 341 HPI_DEBUG_LOG(WARNING, 342 "Message referencing invalid stream %d " 343 "on adapter index %d\n", phm->obj_index, 344 phm->adapter_index); 345 return; 346 } 347 348 switch (phm->function) { 349 case HPI_ISTREAM_READ: 350 instream_read(pao, phm, phr); 351 break; 352 case HPI_ISTREAM_GET_INFO: 353 instream_get_info(pao, phm, phr); 354 break; 355 case HPI_ISTREAM_HOSTBUFFER_ALLOC: 356 instream_host_buffer_allocate(pao, phm, phr); 357 break; 358 case HPI_ISTREAM_HOSTBUFFER_GET_INFO: 359 instream_host_buffer_get_info(pao, phm, phr); 360 break; 361 case HPI_ISTREAM_HOSTBUFFER_FREE: 362 instream_host_buffer_free(pao, phm, phr); 363 break; 364 case HPI_ISTREAM_START: 365 instream_start(pao, phm, phr); 366 break; 367 default: 368 hw_message(pao, phm, phr); 369 break; 370 } 371 } 372 373 /*****************************************************************************/ 374 /** Entry point to this HPI backend 375 * All calls to the HPI start here 376 */ 377 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) 378 { 379 struct hpi_adapter_obj *pao = NULL; 380 381 /* subsytem messages are processed by every HPI. 382 * All other messages are ignored unless the adapter index matches 383 * an adapter in the HPI 384 */ 385 /* HPI_DEBUG_LOG(DEBUG, "HPI Obj=%d, Func=%d\n", phm->wObject, 386 phm->wFunction); */ 387 388 /* if Dsp has crashed then do not communicate with it any more */ 389 if (phm->object != HPI_OBJ_SUBSYSTEM) { 390 pao = hpi_find_adapter(phm->adapter_index); 391 if (!pao) { 392 HPI_DEBUG_LOG(DEBUG, 393 " %d,%d refused, for another HPI?\n", 394 phm->object, phm->function); 395 return; 396 } 397 398 if ((pao->dsp_crashed >= 10) 399 && (phm->function != HPI_ADAPTER_DEBUG_READ)) { 400 /* allow last resort debug read even after crash */ 401 hpi_init_response(phr, phm->object, phm->function, 402 HPI_ERROR_DSP_HARDWARE); 403 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", 404 phm->object, phm->function); 405 return; 406 } 407 } 408 409 /* Init default response */ 410 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER) 411 phr->error = HPI_ERROR_PROCESSING_MESSAGE; 412 413 HPI_DEBUG_LOG(VERBOSE, "start of switch\n"); 414 switch (phm->type) { 415 case HPI_TYPE_MESSAGE: 416 switch (phm->object) { 417 case HPI_OBJ_SUBSYSTEM: 418 subsys_message(phm, phr); 419 break; 420 421 case HPI_OBJ_ADAPTER: 422 adapter_message(pao, phm, phr); 423 break; 424 425 case HPI_OBJ_CONTROLEX: 426 case HPI_OBJ_CONTROL: 427 control_message(pao, phm, phr); 428 break; 429 430 case HPI_OBJ_OSTREAM: 431 outstream_message(pao, phm, phr); 432 break; 433 434 case HPI_OBJ_ISTREAM: 435 instream_message(pao, phm, phr); 436 break; 437 438 default: 439 hw_message(pao, phm, phr); 440 break; 441 } 442 break; 443 444 default: 445 phr->error = HPI_ERROR_INVALID_TYPE; 446 break; 447 } 448 } 449 450 /*****************************************************************************/ 451 /* SUBSYSTEM */ 452 453 /** Create an adapter object and initialise it based on resource information 454 * passed in in the message 455 * *** NOTE - you cannot use this function AND the FindAdapters function at the 456 * same time, the application must use only one of them to get the adapters *** 457 */ 458 static void subsys_create_adapter(struct hpi_message *phm, 459 struct hpi_response *phr) 460 { 461 /* create temp adapter obj, because we don't know what index yet */ 462 struct hpi_adapter_obj ao; 463 u32 os_error_code; 464 u16 err; 465 466 HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n"); 467 468 memset(&ao, 0, sizeof(ao)); 469 470 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL); 471 if (!ao.priv) { 472 HPI_DEBUG_LOG(ERROR, "cant get mem for adapter object\n"); 473 phr->error = HPI_ERROR_MEMORY_ALLOC; 474 return; 475 } 476 477 ao.pci = *phm->u.s.resource.r.pci; 478 err = create_adapter_obj(&ao, &os_error_code); 479 if (err) { 480 delete_adapter_obj(&ao); 481 phr->error = err; 482 phr->u.s.data = os_error_code; 483 return; 484 } 485 486 phr->u.s.aw_adapter_list[ao.index] = ao.adapter_type; 487 phr->u.s.adapter_index = ao.index; 488 phr->u.s.num_adapters++; 489 phr->error = 0; 490 } 491 492 /** delete an adapter - required by WDM driver */ 493 static void subsys_delete_adapter(struct hpi_message *phm, 494 struct hpi_response *phr) 495 { 496 struct hpi_adapter_obj *pao; 497 struct hpi_hw_obj *phw; 498 499 pao = hpi_find_adapter(phm->obj_index); 500 if (!pao) { 501 phr->error = HPI_ERROR_INVALID_OBJ_INDEX; 502 return; 503 } 504 phw = (struct hpi_hw_obj *)pao->priv; 505 /* reset adapter h/w */ 506 /* Reset C6713 #1 */ 507 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); 508 /* reset C6205 */ 509 iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR); 510 511 delete_adapter_obj(pao); 512 hpi_delete_adapter(pao); 513 phr->error = 0; 514 } 515 516 /** Create adapter object 517 allocate buffers, bootload DSPs, initialise control cache 518 */ 519 static u16 create_adapter_obj(struct hpi_adapter_obj *pao, 520 u32 *pos_error_code) 521 { 522 struct hpi_hw_obj *phw = pao->priv; 523 struct bus_master_interface *interface; 524 u32 phys_addr; 525 #ifndef HPI6205_NO_HSR_POLL 526 u32 time_out = HPI6205_TIMEOUT; 527 u32 temp1; 528 #endif 529 int i; 530 u16 err; 531 532 /* init error reporting */ 533 pao->dsp_crashed = 0; 534 535 for (i = 0; i < HPI_MAX_STREAMS; i++) 536 phw->flag_outstream_just_reset[i] = 1; 537 538 /* The C6205 memory area 1 is 8Mbyte window into DSP registers */ 539 phw->prHSR = 540 pao->pci.ap_mem_base[1] + 541 C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]); 542 phw->prHDCR = 543 pao->pci.ap_mem_base[1] + 544 C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]); 545 phw->prDSPP = 546 pao->pci.ap_mem_base[1] + 547 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]); 548 549 pao->has_control_cache = 0; 550 551 if (hpios_locked_mem_alloc(&phw->h_locked_mem, 552 sizeof(struct bus_master_interface), 553 pao->pci.pci_dev)) 554 phw->p_interface_buffer = NULL; 555 else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem, 556 (void *)&phw->p_interface_buffer)) 557 phw->p_interface_buffer = NULL; 558 559 HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n", 560 phw->p_interface_buffer); 561 562 if (phw->p_interface_buffer) { 563 memset((void *)phw->p_interface_buffer, 0, 564 sizeof(struct bus_master_interface)); 565 phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN; 566 } 567 568 err = adapter_boot_load_dsp(pao, pos_error_code); 569 if (err) 570 /* no need to clean up as SubSysCreateAdapter */ 571 /* calls DeleteAdapter on error. */ 572 return err; 573 574 HPI_DEBUG_LOG(INFO, "load DSP code OK\n"); 575 576 /* allow boot load even if mem alloc wont work */ 577 if (!phw->p_interface_buffer) 578 return HPI_ERROR_MEMORY_ALLOC; 579 580 interface = phw->p_interface_buffer; 581 582 #ifndef HPI6205_NO_HSR_POLL 583 /* wait for first interrupt indicating the DSP init is done */ 584 time_out = HPI6205_TIMEOUT * 10; 585 temp1 = 0; 586 while (((temp1 & C6205_HSR_INTSRC) == 0) && --time_out) 587 temp1 = ioread32(phw->prHSR); 588 589 if (temp1 & C6205_HSR_INTSRC) 590 HPI_DEBUG_LOG(INFO, 591 "Interrupt confirming DSP code running OK\n"); 592 else { 593 HPI_DEBUG_LOG(ERROR, 594 "Timed out waiting for interrupt " 595 "confirming DSP code running\n"); 596 return HPI6205_ERROR_6205_NO_IRQ; 597 } 598 599 /* reset the interrupt */ 600 iowrite32(C6205_HSR_INTSRC, phw->prHSR); 601 #endif 602 603 /* make sure the DSP has started ok */ 604 if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) { 605 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n"); 606 return HPI6205_ERROR_6205_INIT_FAILED; 607 } 608 /* Note that *pao, *phw are zeroed after allocation, 609 * so pointers and flags are NULL by default. 610 * Allocate bus mastering control cache buffer and tell the DSP about it 611 */ 612 if (interface->control_cache.number_of_controls) { 613 u8 *p_control_cache_virtual; 614 615 err = hpios_locked_mem_alloc(&phw->h_control_cache, 616 interface->control_cache.size_in_bytes, 617 pao->pci.pci_dev); 618 if (!err) 619 err = hpios_locked_mem_get_virt_addr(&phw-> 620 h_control_cache, 621 (void *)&p_control_cache_virtual); 622 if (!err) { 623 memset(p_control_cache_virtual, 0, 624 interface->control_cache.size_in_bytes); 625 626 phw->p_cache = 627 hpi_alloc_control_cache(interface-> 628 control_cache.number_of_controls, 629 interface->control_cache.size_in_bytes, 630 p_control_cache_virtual); 631 if (!phw->p_cache) 632 err = HPI_ERROR_MEMORY_ALLOC; 633 } 634 if (!err) { 635 err = hpios_locked_mem_get_phys_addr(&phw-> 636 h_control_cache, &phys_addr); 637 interface->control_cache.physical_address32 = 638 phys_addr; 639 } 640 641 if (!err) 642 pao->has_control_cache = 1; 643 else { 644 if (hpios_locked_mem_valid(&phw->h_control_cache)) 645 hpios_locked_mem_free(&phw->h_control_cache); 646 pao->has_control_cache = 0; 647 } 648 } 649 /* allocate bus mastering async buffer and tell the DSP about it */ 650 if (interface->async_buffer.b.size) { 651 err = hpios_locked_mem_alloc(&phw->h_async_event_buffer, 652 interface->async_buffer.b.size * 653 sizeof(struct hpi_async_event), pao->pci.pci_dev); 654 if (!err) 655 err = hpios_locked_mem_get_virt_addr 656 (&phw->h_async_event_buffer, (void *) 657 &phw->p_async_event_buffer); 658 if (!err) 659 memset((void *)phw->p_async_event_buffer, 0, 660 interface->async_buffer.b.size * 661 sizeof(struct hpi_async_event)); 662 if (!err) { 663 err = hpios_locked_mem_get_phys_addr 664 (&phw->h_async_event_buffer, &phys_addr); 665 interface->async_buffer.physical_address32 = 666 phys_addr; 667 } 668 if (err) { 669 if (hpios_locked_mem_valid(&phw-> 670 h_async_event_buffer)) { 671 hpios_locked_mem_free 672 (&phw->h_async_event_buffer); 673 phw->p_async_event_buffer = NULL; 674 } 675 } 676 } 677 send_dsp_command(phw, H620_HIF_IDLE); 678 679 { 680 struct hpi_message hm; 681 struct hpi_response hr; 682 u32 max_streams; 683 684 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n"); 685 memset(&hm, 0, sizeof(hm)); 686 hm.type = HPI_TYPE_MESSAGE; 687 hm.size = sizeof(hm); 688 hm.object = HPI_OBJ_ADAPTER; 689 hm.function = HPI_ADAPTER_GET_INFO; 690 hm.adapter_index = 0; 691 memset(&hr, 0, sizeof(hr)); 692 hr.size = sizeof(hr); 693 694 err = message_response_sequence(pao, &hm, &hr); 695 if (err) { 696 HPI_DEBUG_LOG(ERROR, "message transport error %d\n", 697 err); 698 return err; 699 } 700 if (hr.error) 701 return hr.error; 702 703 pao->adapter_type = hr.u.ax.info.adapter_type; 704 pao->index = hr.u.ax.info.adapter_index; 705 706 max_streams = 707 hr.u.ax.info.num_outstreams + 708 hr.u.ax.info.num_instreams; 709 710 hpios_locked_mem_prepare((max_streams * 6) / 10, max_streams, 711 65536, pao->pci.pci_dev); 712 713 HPI_DEBUG_LOG(VERBOSE, 714 "got adapter info type %x index %d serial %d\n", 715 hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index, 716 hr.u.ax.info.serial_number); 717 } 718 719 pao->open = 0; /* upon creation the adapter is closed */ 720 721 if (phw->p_cache) 722 phw->p_cache->adap_idx = pao->index; 723 724 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n"); 725 726 return hpi_add_adapter(pao); 727 } 728 729 /** Free memory areas allocated by adapter 730 * this routine is called from SubSysDeleteAdapter, 731 * and SubSysCreateAdapter if duplicate index 732 */ 733 static void delete_adapter_obj(struct hpi_adapter_obj *pao) 734 { 735 struct hpi_hw_obj *phw; 736 int i; 737 738 phw = pao->priv; 739 740 if (hpios_locked_mem_valid(&phw->h_async_event_buffer)) { 741 hpios_locked_mem_free(&phw->h_async_event_buffer); 742 phw->p_async_event_buffer = NULL; 743 } 744 745 if (hpios_locked_mem_valid(&phw->h_control_cache)) { 746 hpios_locked_mem_free(&phw->h_control_cache); 747 hpi_free_control_cache(phw->p_cache); 748 } 749 750 if (hpios_locked_mem_valid(&phw->h_locked_mem)) { 751 hpios_locked_mem_free(&phw->h_locked_mem); 752 phw->p_interface_buffer = NULL; 753 } 754 755 for (i = 0; i < HPI_MAX_STREAMS; i++) 756 if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) { 757 hpios_locked_mem_free(&phw->instream_host_buffers[i]); 758 /*?phw->InStreamHostBuffers[i] = NULL; */ 759 phw->instream_host_buffer_size[i] = 0; 760 } 761 762 for (i = 0; i < HPI_MAX_STREAMS; i++) 763 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) { 764 hpios_locked_mem_free(&phw->outstream_host_buffers 765 [i]); 766 phw->outstream_host_buffer_size[i] = 0; 767 } 768 769 hpios_locked_mem_unprepare(pao->pci.pci_dev); 770 771 kfree(phw); 772 } 773 774 /*****************************************************************************/ 775 /* OutStream Host buffer functions */ 776 777 /** Allocate or attach buffer for busmastering 778 */ 779 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, 780 struct hpi_message *phm, struct hpi_response *phr) 781 { 782 u16 err = 0; 783 u32 command = phm->u.d.u.buffer.command; 784 struct hpi_hw_obj *phw = pao->priv; 785 struct bus_master_interface *interface = phw->p_interface_buffer; 786 787 hpi_init_response(phr, phm->object, phm->function, 0); 788 789 if (command == HPI_BUFFER_CMD_EXTERNAL 790 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { 791 /* ALLOC phase, allocate a buffer with power of 2 size, 792 get its bus address for PCI bus mastering 793 */ 794 phm->u.d.u.buffer.buffer_size = 795 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); 796 /* return old size and allocated size, 797 so caller can detect change */ 798 phr->u.d.u.stream_info.data_available = 799 phw->outstream_host_buffer_size[phm->obj_index]; 800 phr->u.d.u.stream_info.buffer_size = 801 phm->u.d.u.buffer.buffer_size; 802 803 if (phw->outstream_host_buffer_size[phm->obj_index] == 804 phm->u.d.u.buffer.buffer_size) { 805 /* Same size, no action required */ 806 return; 807 } 808 809 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 810 obj_index])) 811 hpios_locked_mem_free(&phw->outstream_host_buffers 812 [phm->obj_index]); 813 814 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers 815 [phm->obj_index], phm->u.d.u.buffer.buffer_size, 816 pao->pci.pci_dev); 817 818 if (err) { 819 phr->error = HPI_ERROR_INVALID_DATASIZE; 820 phw->outstream_host_buffer_size[phm->obj_index] = 0; 821 return; 822 } 823 824 err = hpios_locked_mem_get_phys_addr 825 (&phw->outstream_host_buffers[phm->obj_index], 826 &phm->u.d.u.buffer.pci_address); 827 /* get the phys addr into msg for single call alloc caller 828 * needs to do this for split alloc (or use the same message) 829 * return the phy address for split alloc in the respose too 830 */ 831 phr->u.d.u.stream_info.auxiliary_data_available = 832 phm->u.d.u.buffer.pci_address; 833 834 if (err) { 835 hpios_locked_mem_free(&phw->outstream_host_buffers 836 [phm->obj_index]); 837 phw->outstream_host_buffer_size[phm->obj_index] = 0; 838 phr->error = HPI_ERROR_MEMORY_ALLOC; 839 return; 840 } 841 } 842 843 if (command == HPI_BUFFER_CMD_EXTERNAL 844 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { 845 /* GRANT phase. Set up the BBM status, tell the DSP about 846 the buffer so it can start using BBM. 847 */ 848 struct hpi_hostbuffer_status *status; 849 850 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. 851 buffer_size - 1)) { 852 HPI_DEBUG_LOG(ERROR, 853 "Buffer size must be 2^N not %d\n", 854 phm->u.d.u.buffer.buffer_size); 855 phr->error = HPI_ERROR_INVALID_DATASIZE; 856 return; 857 } 858 phw->outstream_host_buffer_size[phm->obj_index] = 859 phm->u.d.u.buffer.buffer_size; 860 status = &interface->outstream_host_buffer_status[phm-> 861 obj_index]; 862 status->samples_processed = 0; 863 status->stream_state = HPI_STATE_STOPPED; 864 status->dSP_index = 0; 865 status->host_index = status->dSP_index; 866 status->size_in_bytes = phm->u.d.u.buffer.buffer_size; 867 868 hw_message(pao, phm, phr); 869 870 if (phr->error 871 && hpios_locked_mem_valid(&phw-> 872 outstream_host_buffers[phm->obj_index])) { 873 hpios_locked_mem_free(&phw->outstream_host_buffers 874 [phm->obj_index]); 875 phw->outstream_host_buffer_size[phm->obj_index] = 0; 876 } 877 } 878 } 879 880 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, 881 struct hpi_message *phm, struct hpi_response *phr) 882 { 883 struct hpi_hw_obj *phw = pao->priv; 884 struct bus_master_interface *interface = phw->p_interface_buffer; 885 struct hpi_hostbuffer_status *status; 886 u8 *p_bbm_data; 887 888 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 889 obj_index])) { 890 if (hpios_locked_mem_get_virt_addr(&phw-> 891 outstream_host_buffers[phm->obj_index], 892 (void *)&p_bbm_data)) { 893 phr->error = HPI_ERROR_INVALID_OPERATION; 894 return; 895 } 896 status = &interface->outstream_host_buffer_status[phm-> 897 obj_index]; 898 hpi_init_response(phr, HPI_OBJ_OSTREAM, 899 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0); 900 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; 901 phr->u.d.u.hostbuffer_info.p_status = status; 902 } else { 903 hpi_init_response(phr, HPI_OBJ_OSTREAM, 904 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 905 HPI_ERROR_INVALID_OPERATION); 906 } 907 } 908 909 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, 910 struct hpi_message *phm, struct hpi_response *phr) 911 { 912 struct hpi_hw_obj *phw = pao->priv; 913 u32 command = phm->u.d.u.buffer.command; 914 915 if (phw->outstream_host_buffer_size[phm->obj_index]) { 916 if (command == HPI_BUFFER_CMD_EXTERNAL 917 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { 918 phw->outstream_host_buffer_size[phm->obj_index] = 0; 919 hw_message(pao, phm, phr); 920 /* Tell adapter to stop using the host buffer. */ 921 } 922 if (command == HPI_BUFFER_CMD_EXTERNAL 923 || command == HPI_BUFFER_CMD_INTERNAL_FREE) 924 hpios_locked_mem_free(&phw->outstream_host_buffers 925 [phm->obj_index]); 926 } 927 /* Should HPI_ERROR_INVALID_OPERATION be returned 928 if no host buffer is allocated? */ 929 else 930 hpi_init_response(phr, HPI_OBJ_OSTREAM, 931 HPI_OSTREAM_HOSTBUFFER_FREE, 0); 932 933 } 934 935 static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status) 936 { 937 return status->size_in_bytes - (status->host_index - 938 status->dSP_index); 939 } 940 941 static void outstream_write(struct hpi_adapter_obj *pao, 942 struct hpi_message *phm, struct hpi_response *phr) 943 { 944 struct hpi_hw_obj *phw = pao->priv; 945 struct bus_master_interface *interface = phw->p_interface_buffer; 946 struct hpi_hostbuffer_status *status; 947 u32 space_available; 948 949 if (!phw->outstream_host_buffer_size[phm->obj_index]) { 950 /* there is no BBM buffer, write via message */ 951 hw_message(pao, phm, phr); 952 return; 953 } 954 955 hpi_init_response(phr, phm->object, phm->function, 0); 956 status = &interface->outstream_host_buffer_status[phm->obj_index]; 957 958 space_available = outstream_get_space_available(status); 959 if (space_available < phm->u.d.u.data.data_size) { 960 phr->error = HPI_ERROR_INVALID_DATASIZE; 961 return; 962 } 963 964 /* HostBuffers is used to indicate host buffer is internally allocated. 965 otherwise, assumed external, data written externally */ 966 if (phm->u.d.u.data.pb_data 967 && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 968 obj_index])) { 969 u8 *p_bbm_data; 970 u32 l_first_write; 971 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; 972 973 if (hpios_locked_mem_get_virt_addr(&phw-> 974 outstream_host_buffers[phm->obj_index], 975 (void *)&p_bbm_data)) { 976 phr->error = HPI_ERROR_INVALID_OPERATION; 977 return; 978 } 979 980 /* either all data, 981 or enough to fit from current to end of BBM buffer */ 982 l_first_write = 983 min(phm->u.d.u.data.data_size, 984 status->size_in_bytes - 985 (status->host_index & (status->size_in_bytes - 1))); 986 987 memcpy(p_bbm_data + 988 (status->host_index & (status->size_in_bytes - 1)), 989 p_app_data, l_first_write); 990 /* remaining data if any */ 991 memcpy(p_bbm_data, p_app_data + l_first_write, 992 phm->u.d.u.data.data_size - l_first_write); 993 } 994 995 /* 996 * This version relies on the DSP code triggering an OStream buffer 997 * update immediately following a SET_FORMAT call. The host has 998 * already written data into the BBM buffer, but the DSP won't know about 999 * it until dwHostIndex is adjusted. 1000 */ 1001 if (phw->flag_outstream_just_reset[phm->obj_index]) { 1002 /* Format can only change after reset. Must tell DSP. */ 1003 u16 function = phm->function; 1004 phw->flag_outstream_just_reset[phm->obj_index] = 0; 1005 phm->function = HPI_OSTREAM_SET_FORMAT; 1006 hw_message(pao, phm, phr); /* send the format to the DSP */ 1007 phm->function = function; 1008 if (phr->error) 1009 return; 1010 } 1011 1012 status->host_index += phm->u.d.u.data.data_size; 1013 } 1014 1015 static void outstream_get_info(struct hpi_adapter_obj *pao, 1016 struct hpi_message *phm, struct hpi_response *phr) 1017 { 1018 struct hpi_hw_obj *phw = pao->priv; 1019 struct bus_master_interface *interface = phw->p_interface_buffer; 1020 struct hpi_hostbuffer_status *status; 1021 1022 if (!phw->outstream_host_buffer_size[phm->obj_index]) { 1023 hw_message(pao, phm, phr); 1024 return; 1025 } 1026 1027 hpi_init_response(phr, phm->object, phm->function, 0); 1028 1029 status = &interface->outstream_host_buffer_status[phm->obj_index]; 1030 1031 phr->u.d.u.stream_info.state = (u16)status->stream_state; 1032 phr->u.d.u.stream_info.samples_transferred = 1033 status->samples_processed; 1034 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; 1035 phr->u.d.u.stream_info.data_available = 1036 status->size_in_bytes - outstream_get_space_available(status); 1037 phr->u.d.u.stream_info.auxiliary_data_available = 1038 status->auxiliary_data_available; 1039 } 1040 1041 static void outstream_start(struct hpi_adapter_obj *pao, 1042 struct hpi_message *phm, struct hpi_response *phr) 1043 { 1044 hw_message(pao, phm, phr); 1045 } 1046 1047 static void outstream_reset(struct hpi_adapter_obj *pao, 1048 struct hpi_message *phm, struct hpi_response *phr) 1049 { 1050 struct hpi_hw_obj *phw = pao->priv; 1051 phw->flag_outstream_just_reset[phm->obj_index] = 1; 1052 hw_message(pao, phm, phr); 1053 } 1054 1055 static void outstream_open(struct hpi_adapter_obj *pao, 1056 struct hpi_message *phm, struct hpi_response *phr) 1057 { 1058 outstream_reset(pao, phm, phr); 1059 } 1060 1061 /*****************************************************************************/ 1062 /* InStream Host buffer functions */ 1063 1064 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, 1065 struct hpi_message *phm, struct hpi_response *phr) 1066 { 1067 u16 err = 0; 1068 u32 command = phm->u.d.u.buffer.command; 1069 struct hpi_hw_obj *phw = pao->priv; 1070 struct bus_master_interface *interface = phw->p_interface_buffer; 1071 1072 hpi_init_response(phr, phm->object, phm->function, 0); 1073 1074 if (command == HPI_BUFFER_CMD_EXTERNAL 1075 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { 1076 1077 phm->u.d.u.buffer.buffer_size = 1078 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); 1079 phr->u.d.u.stream_info.data_available = 1080 phw->instream_host_buffer_size[phm->obj_index]; 1081 phr->u.d.u.stream_info.buffer_size = 1082 phm->u.d.u.buffer.buffer_size; 1083 1084 if (phw->instream_host_buffer_size[phm->obj_index] == 1085 phm->u.d.u.buffer.buffer_size) { 1086 /* Same size, no action required */ 1087 return; 1088 } 1089 1090 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1091 obj_index])) 1092 hpios_locked_mem_free(&phw->instream_host_buffers 1093 [phm->obj_index]); 1094 1095 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm-> 1096 obj_index], phm->u.d.u.buffer.buffer_size, 1097 pao->pci.pci_dev); 1098 1099 if (err) { 1100 phr->error = HPI_ERROR_INVALID_DATASIZE; 1101 phw->instream_host_buffer_size[phm->obj_index] = 0; 1102 return; 1103 } 1104 1105 err = hpios_locked_mem_get_phys_addr 1106 (&phw->instream_host_buffers[phm->obj_index], 1107 &phm->u.d.u.buffer.pci_address); 1108 /* get the phys addr into msg for single call alloc. Caller 1109 needs to do this for split alloc so return the phy address */ 1110 phr->u.d.u.stream_info.auxiliary_data_available = 1111 phm->u.d.u.buffer.pci_address; 1112 if (err) { 1113 hpios_locked_mem_free(&phw->instream_host_buffers 1114 [phm->obj_index]); 1115 phw->instream_host_buffer_size[phm->obj_index] = 0; 1116 phr->error = HPI_ERROR_MEMORY_ALLOC; 1117 return; 1118 } 1119 } 1120 1121 if (command == HPI_BUFFER_CMD_EXTERNAL 1122 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { 1123 struct hpi_hostbuffer_status *status; 1124 1125 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. 1126 buffer_size - 1)) { 1127 HPI_DEBUG_LOG(ERROR, 1128 "Buffer size must be 2^N not %d\n", 1129 phm->u.d.u.buffer.buffer_size); 1130 phr->error = HPI_ERROR_INVALID_DATASIZE; 1131 return; 1132 } 1133 1134 phw->instream_host_buffer_size[phm->obj_index] = 1135 phm->u.d.u.buffer.buffer_size; 1136 status = &interface->instream_host_buffer_status[phm-> 1137 obj_index]; 1138 status->samples_processed = 0; 1139 status->stream_state = HPI_STATE_STOPPED; 1140 status->dSP_index = 0; 1141 status->host_index = status->dSP_index; 1142 status->size_in_bytes = phm->u.d.u.buffer.buffer_size; 1143 1144 hw_message(pao, phm, phr); 1145 if (phr->error 1146 && hpios_locked_mem_valid(&phw-> 1147 instream_host_buffers[phm->obj_index])) { 1148 hpios_locked_mem_free(&phw->instream_host_buffers 1149 [phm->obj_index]); 1150 phw->instream_host_buffer_size[phm->obj_index] = 0; 1151 } 1152 } 1153 } 1154 1155 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, 1156 struct hpi_message *phm, struct hpi_response *phr) 1157 { 1158 struct hpi_hw_obj *phw = pao->priv; 1159 struct bus_master_interface *interface = phw->p_interface_buffer; 1160 struct hpi_hostbuffer_status *status; 1161 u8 *p_bbm_data; 1162 1163 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1164 obj_index])) { 1165 if (hpios_locked_mem_get_virt_addr(&phw-> 1166 instream_host_buffers[phm->obj_index], 1167 (void *)&p_bbm_data)) { 1168 phr->error = HPI_ERROR_INVALID_OPERATION; 1169 return; 1170 } 1171 status = &interface->instream_host_buffer_status[phm-> 1172 obj_index]; 1173 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1174 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0); 1175 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; 1176 phr->u.d.u.hostbuffer_info.p_status = status; 1177 } else { 1178 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1179 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 1180 HPI_ERROR_INVALID_OPERATION); 1181 } 1182 } 1183 1184 static void instream_host_buffer_free(struct hpi_adapter_obj *pao, 1185 struct hpi_message *phm, struct hpi_response *phr) 1186 { 1187 struct hpi_hw_obj *phw = pao->priv; 1188 u32 command = phm->u.d.u.buffer.command; 1189 1190 if (phw->instream_host_buffer_size[phm->obj_index]) { 1191 if (command == HPI_BUFFER_CMD_EXTERNAL 1192 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { 1193 phw->instream_host_buffer_size[phm->obj_index] = 0; 1194 hw_message(pao, phm, phr); 1195 } 1196 1197 if (command == HPI_BUFFER_CMD_EXTERNAL 1198 || command == HPI_BUFFER_CMD_INTERNAL_FREE) 1199 hpios_locked_mem_free(&phw->instream_host_buffers 1200 [phm->obj_index]); 1201 1202 } else { 1203 /* Should HPI_ERROR_INVALID_OPERATION be returned 1204 if no host buffer is allocated? */ 1205 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1206 HPI_ISTREAM_HOSTBUFFER_FREE, 0); 1207 1208 } 1209 1210 } 1211 1212 static void instream_start(struct hpi_adapter_obj *pao, 1213 struct hpi_message *phm, struct hpi_response *phr) 1214 { 1215 hw_message(pao, phm, phr); 1216 } 1217 1218 static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status) 1219 { 1220 return status->dSP_index - status->host_index; 1221 } 1222 1223 static void instream_read(struct hpi_adapter_obj *pao, 1224 struct hpi_message *phm, struct hpi_response *phr) 1225 { 1226 struct hpi_hw_obj *phw = pao->priv; 1227 struct bus_master_interface *interface = phw->p_interface_buffer; 1228 struct hpi_hostbuffer_status *status; 1229 u32 data_available; 1230 u8 *p_bbm_data; 1231 u32 l_first_read; 1232 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; 1233 1234 if (!phw->instream_host_buffer_size[phm->obj_index]) { 1235 hw_message(pao, phm, phr); 1236 return; 1237 } 1238 hpi_init_response(phr, phm->object, phm->function, 0); 1239 1240 status = &interface->instream_host_buffer_status[phm->obj_index]; 1241 data_available = instream_get_bytes_available(status); 1242 if (data_available < phm->u.d.u.data.data_size) { 1243 phr->error = HPI_ERROR_INVALID_DATASIZE; 1244 return; 1245 } 1246 1247 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1248 obj_index])) { 1249 if (hpios_locked_mem_get_virt_addr(&phw-> 1250 instream_host_buffers[phm->obj_index], 1251 (void *)&p_bbm_data)) { 1252 phr->error = HPI_ERROR_INVALID_OPERATION; 1253 return; 1254 } 1255 1256 /* either all data, 1257 or enough to fit from current to end of BBM buffer */ 1258 l_first_read = 1259 min(phm->u.d.u.data.data_size, 1260 status->size_in_bytes - 1261 (status->host_index & (status->size_in_bytes - 1))); 1262 1263 memcpy(p_app_data, 1264 p_bbm_data + 1265 (status->host_index & (status->size_in_bytes - 1)), 1266 l_first_read); 1267 /* remaining data if any */ 1268 memcpy(p_app_data + l_first_read, p_bbm_data, 1269 phm->u.d.u.data.data_size - l_first_read); 1270 } 1271 status->host_index += phm->u.d.u.data.data_size; 1272 } 1273 1274 static void instream_get_info(struct hpi_adapter_obj *pao, 1275 struct hpi_message *phm, struct hpi_response *phr) 1276 { 1277 struct hpi_hw_obj *phw = pao->priv; 1278 struct bus_master_interface *interface = phw->p_interface_buffer; 1279 struct hpi_hostbuffer_status *status; 1280 if (!phw->instream_host_buffer_size[phm->obj_index]) { 1281 hw_message(pao, phm, phr); 1282 return; 1283 } 1284 1285 status = &interface->instream_host_buffer_status[phm->obj_index]; 1286 1287 hpi_init_response(phr, phm->object, phm->function, 0); 1288 1289 phr->u.d.u.stream_info.state = (u16)status->stream_state; 1290 phr->u.d.u.stream_info.samples_transferred = 1291 status->samples_processed; 1292 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; 1293 phr->u.d.u.stream_info.data_available = 1294 instream_get_bytes_available(status); 1295 phr->u.d.u.stream_info.auxiliary_data_available = 1296 status->auxiliary_data_available; 1297 } 1298 1299 /*****************************************************************************/ 1300 /* LOW-LEVEL */ 1301 #define HPI6205_MAX_FILES_TO_LOAD 2 1302 1303 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 1304 u32 *pos_error_code) 1305 { 1306 struct hpi_hw_obj *phw = pao->priv; 1307 struct dsp_code dsp_code; 1308 u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD]; 1309 u16 firmware_id = pao->pci.pci_dev->subsystem_device; 1310 u32 temp; 1311 int dsp = 0, i = 0; 1312 u16 err = 0; 1313 1314 boot_code_id[0] = HPI_ADAPTER_ASI(0x6205); 1315 1316 /* special cases where firmware_id != subsys ID */ 1317 switch (firmware_id) { 1318 case HPI_ADAPTER_FAMILY_ASI(0x5000): 1319 boot_code_id[0] = firmware_id; 1320 firmware_id = 0; 1321 break; 1322 case HPI_ADAPTER_FAMILY_ASI(0x5300): 1323 case HPI_ADAPTER_FAMILY_ASI(0x5400): 1324 case HPI_ADAPTER_FAMILY_ASI(0x6300): 1325 firmware_id = HPI_ADAPTER_FAMILY_ASI(0x6400); 1326 break; 1327 case HPI_ADAPTER_FAMILY_ASI(0x5600): 1328 case HPI_ADAPTER_FAMILY_ASI(0x6500): 1329 firmware_id = HPI_ADAPTER_FAMILY_ASI(0x6600); 1330 break; 1331 case HPI_ADAPTER_FAMILY_ASI(0x8800): 1332 firmware_id = HPI_ADAPTER_FAMILY_ASI(0x8900); 1333 break; 1334 } 1335 boot_code_id[1] = firmware_id; 1336 1337 /* reset DSP by writing a 1 to the WARMRESET bit */ 1338 temp = C6205_HDCR_WARMRESET; 1339 iowrite32(temp, phw->prHDCR); 1340 hpios_delay_micro_seconds(1000); 1341 1342 /* check that PCI i/f was configured by EEPROM */ 1343 temp = ioread32(phw->prHSR); 1344 if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) != 1345 C6205_HSR_EEREAD) 1346 return HPI6205_ERROR_6205_EEPROM; 1347 temp |= 0x04; 1348 /* disable PINTA interrupt */ 1349 iowrite32(temp, phw->prHSR); 1350 1351 /* check control register reports PCI boot mode */ 1352 temp = ioread32(phw->prHDCR); 1353 if (!(temp & C6205_HDCR_PCIBOOT)) 1354 return HPI6205_ERROR_6205_REG; 1355 1356 /* try writing a few numbers to the DSP page register */ 1357 /* and reading them back. */ 1358 temp = 3; 1359 iowrite32(temp, phw->prDSPP); 1360 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1361 return HPI6205_ERROR_6205_DSPPAGE; 1362 temp = 2; 1363 iowrite32(temp, phw->prDSPP); 1364 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1365 return HPI6205_ERROR_6205_DSPPAGE; 1366 temp = 1; 1367 iowrite32(temp, phw->prDSPP); 1368 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1369 return HPI6205_ERROR_6205_DSPPAGE; 1370 /* reset DSP page to the correct number */ 1371 temp = 0; 1372 iowrite32(temp, phw->prDSPP); 1373 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1374 return HPI6205_ERROR_6205_DSPPAGE; 1375 phw->dsp_page = 0; 1376 1377 /* release 6713 from reset before 6205 is bootloaded. 1378 This ensures that the EMIF is inactive, 1379 and the 6713 HPI gets the correct bootmode etc 1380 */ 1381 if (boot_code_id[1] != 0) { 1382 /* DSP 1 is a C6713 */ 1383 /* CLKX0 <- '1' release the C6205 bootmode pulldowns */ 1384 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002202); 1385 hpios_delay_micro_seconds(100); 1386 /* Reset the 6713 #1 - revB */ 1387 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); 1388 1389 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1390 boot_loader_read_mem32(pao, 0, 0); 1391 1392 hpios_delay_micro_seconds(100); 1393 /* Release C6713 from reset - revB */ 1394 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4); 1395 hpios_delay_micro_seconds(100); 1396 } 1397 1398 for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) { 1399 /* is there a DSP to load? */ 1400 if (boot_code_id[dsp] == 0) 1401 continue; 1402 1403 err = boot_loader_config_emif(pao, dsp); 1404 if (err) 1405 return err; 1406 1407 err = boot_loader_test_internal_memory(pao, dsp); 1408 if (err) 1409 return err; 1410 1411 err = boot_loader_test_external_memory(pao, dsp); 1412 if (err) 1413 return err; 1414 1415 err = boot_loader_test_pld(pao, dsp); 1416 if (err) 1417 return err; 1418 1419 /* write the DSP code down into the DSPs memory */ 1420 dsp_code.ps_dev = pao->pci.pci_dev; 1421 err = hpi_dsp_code_open(boot_code_id[dsp], &dsp_code, 1422 pos_error_code); 1423 if (err) 1424 return err; 1425 1426 while (1) { 1427 u32 length; 1428 u32 address; 1429 u32 type; 1430 u32 *pcode; 1431 1432 err = hpi_dsp_code_read_word(&dsp_code, &length); 1433 if (err) 1434 break; 1435 if (length == 0xFFFFFFFF) 1436 break; /* end of code */ 1437 1438 err = hpi_dsp_code_read_word(&dsp_code, &address); 1439 if (err) 1440 break; 1441 err = hpi_dsp_code_read_word(&dsp_code, &type); 1442 if (err) 1443 break; 1444 err = hpi_dsp_code_read_block(length, &dsp_code, 1445 &pcode); 1446 if (err) 1447 break; 1448 for (i = 0; i < (int)length; i++) { 1449 boot_loader_write_mem32(pao, dsp, address, 1450 *pcode); 1451 /* dummy read every 4 words */ 1452 /* for 6205 advisory 1.4.4 */ 1453 if (i % 4 == 0) 1454 boot_loader_read_mem32(pao, dsp, 1455 address); 1456 pcode++; 1457 address += 4; 1458 } 1459 1460 } 1461 if (err) { 1462 hpi_dsp_code_close(&dsp_code); 1463 return err; 1464 } 1465 1466 /* verify code */ 1467 hpi_dsp_code_rewind(&dsp_code); 1468 while (1) { 1469 u32 length = 0; 1470 u32 address = 0; 1471 u32 type = 0; 1472 u32 *pcode = NULL; 1473 u32 data = 0; 1474 1475 hpi_dsp_code_read_word(&dsp_code, &length); 1476 if (length == 0xFFFFFFFF) 1477 break; /* end of code */ 1478 1479 hpi_dsp_code_read_word(&dsp_code, &address); 1480 hpi_dsp_code_read_word(&dsp_code, &type); 1481 hpi_dsp_code_read_block(length, &dsp_code, &pcode); 1482 1483 for (i = 0; i < (int)length; i++) { 1484 data = boot_loader_read_mem32(pao, dsp, 1485 address); 1486 if (data != *pcode) { 1487 err = 0; 1488 break; 1489 } 1490 pcode++; 1491 address += 4; 1492 } 1493 if (err) 1494 break; 1495 } 1496 hpi_dsp_code_close(&dsp_code); 1497 if (err) 1498 return err; 1499 } 1500 1501 /* After bootloading all DSPs, start DSP0 running 1502 * The DSP0 code will handle starting and synchronizing with its slaves 1503 */ 1504 if (phw->p_interface_buffer) { 1505 /* we need to tell the card the physical PCI address */ 1506 u32 physicalPC_iaddress; 1507 struct bus_master_interface *interface = 1508 phw->p_interface_buffer; 1509 u32 host_mailbox_address_on_dsp; 1510 u32 physicalPC_iaddress_verify = 0; 1511 int time_out = 10; 1512 /* set ack so we know when DSP is ready to go */ 1513 /* (dwDspAck will be changed to HIF_RESET) */ 1514 interface->dsp_ack = H620_HIF_UNKNOWN; 1515 wmb(); /* ensure ack is written before dsp writes back */ 1516 1517 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem, 1518 &physicalPC_iaddress); 1519 1520 /* locate the host mailbox on the DSP. */ 1521 host_mailbox_address_on_dsp = 0x80000000; 1522 while ((physicalPC_iaddress != physicalPC_iaddress_verify) 1523 && time_out--) { 1524 boot_loader_write_mem32(pao, 0, 1525 host_mailbox_address_on_dsp, 1526 physicalPC_iaddress); 1527 physicalPC_iaddress_verify = 1528 boot_loader_read_mem32(pao, 0, 1529 host_mailbox_address_on_dsp); 1530 } 1531 } 1532 HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n"); 1533 /* enable interrupts */ 1534 temp = ioread32(phw->prHSR); 1535 temp &= ~(u32)C6205_HSR_INTAM; 1536 iowrite32(temp, phw->prHSR); 1537 1538 /* start code running... */ 1539 temp = ioread32(phw->prHDCR); 1540 temp |= (u32)C6205_HDCR_DSPINT; 1541 iowrite32(temp, phw->prHDCR); 1542 1543 /* give the DSP 10ms to start up */ 1544 hpios_delay_micro_seconds(10000); 1545 return err; 1546 1547 } 1548 1549 /*****************************************************************************/ 1550 /* Bootloader utility functions */ 1551 1552 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, 1553 u32 address) 1554 { 1555 struct hpi_hw_obj *phw = pao->priv; 1556 u32 data = 0; 1557 __iomem u32 *p_data; 1558 1559 if (dsp_index == 0) { 1560 /* DSP 0 is always C6205 */ 1561 if ((address >= 0x01800000) & (address < 0x02000000)) { 1562 /* BAR1 register access */ 1563 p_data = pao->pci.ap_mem_base[1] + 1564 (address & 0x007fffff) / 1565 sizeof(*pao->pci.ap_mem_base[1]); 1566 /* HPI_DEBUG_LOG(WARNING, 1567 "BAR1 access %08x\n", dwAddress); */ 1568 } else { 1569 u32 dw4M_page = address >> 22L; 1570 if (dw4M_page != phw->dsp_page) { 1571 phw->dsp_page = dw4M_page; 1572 /* *INDENT OFF* */ 1573 iowrite32(phw->dsp_page, phw->prDSPP); 1574 /* *INDENT-ON* */ 1575 } 1576 address &= 0x3fffff; /* address within 4M page */ 1577 /* BAR0 memory access */ 1578 p_data = pao->pci.ap_mem_base[0] + 1579 address / sizeof(u32); 1580 } 1581 data = ioread32(p_data); 1582 } else if (dsp_index == 1) { 1583 /* DSP 1 is a C6713 */ 1584 u32 lsb; 1585 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); 1586 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); 1587 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR); 1588 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR); 1589 data = (data << 16) | (lsb & 0xFFFF); 1590 } 1591 return data; 1592 } 1593 1594 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, 1595 int dsp_index, u32 address, u32 data) 1596 { 1597 struct hpi_hw_obj *phw = pao->priv; 1598 __iomem u32 *p_data; 1599 /* u32 dwVerifyData=0; */ 1600 1601 if (dsp_index == 0) { 1602 /* DSP 0 is always C6205 */ 1603 if ((address >= 0x01800000) & (address < 0x02000000)) { 1604 /* BAR1 - DSP register access using */ 1605 /* Non-prefetchable PCI access */ 1606 p_data = pao->pci.ap_mem_base[1] + 1607 (address & 0x007fffff) / 1608 sizeof(*pao->pci.ap_mem_base[1]); 1609 } else { 1610 /* BAR0 access - all of DSP memory using */ 1611 /* pre-fetchable PCI access */ 1612 u32 dw4M_page = address >> 22L; 1613 if (dw4M_page != phw->dsp_page) { 1614 phw->dsp_page = dw4M_page; 1615 /* *INDENT-OFF* */ 1616 iowrite32(phw->dsp_page, phw->prDSPP); 1617 /* *INDENT-ON* */ 1618 } 1619 address &= 0x3fffff; /* address within 4M page */ 1620 p_data = pao->pci.ap_mem_base[0] + 1621 address / sizeof(u32); 1622 } 1623 iowrite32(data, p_data); 1624 } else if (dsp_index == 1) { 1625 /* DSP 1 is a C6713 */ 1626 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); 1627 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); 1628 1629 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1630 boot_loader_read_mem32(pao, 0, 0); 1631 1632 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data); 1633 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16); 1634 1635 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1636 boot_loader_read_mem32(pao, 0, 0); 1637 } 1638 } 1639 1640 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index) 1641 { 1642 if (dsp_index == 0) { 1643 u32 setting; 1644 1645 /* DSP 0 is always C6205 */ 1646 1647 /* Set the EMIF */ 1648 /* memory map of C6205 */ 1649 /* 00000000-0000FFFF 16Kx32 internal program */ 1650 /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */ 1651 1652 /* EMIF config */ 1653 /*------------ */ 1654 /* Global EMIF control */ 1655 boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779); 1656 #define WS_OFS 28 1657 #define WST_OFS 22 1658 #define WH_OFS 20 1659 #define RS_OFS 16 1660 #define RST_OFS 8 1661 #define MTYPE_OFS 4 1662 #define RH_OFS 0 1663 1664 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */ 1665 setting = 0x00000030; 1666 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting); 1667 if (setting != boot_loader_read_mem32(pao, dsp_index, 1668 0x01800008)) 1669 return HPI6205_ERROR_DSP_EMIF; 1670 1671 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */ 1672 /* which occupies D15..0. 6713 starts at 27MHz, so need */ 1673 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */ 1674 /* WST should be 71, but 63 is max possible */ 1675 setting = 1676 (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) | 1677 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | 1678 (2L << MTYPE_OFS); 1679 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting); 1680 if (setting != boot_loader_read_mem32(pao, dsp_index, 1681 0x01800004)) 1682 return HPI6205_ERROR_DSP_EMIF; 1683 1684 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */ 1685 /* which occupies D15..0. 6713 starts at 27MHz, so need */ 1686 /* plenty of wait states */ 1687 setting = 1688 (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) | 1689 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | 1690 (2L << MTYPE_OFS); 1691 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting); 1692 if (setting != boot_loader_read_mem32(pao, dsp_index, 1693 0x01800010)) 1694 return HPI6205_ERROR_DSP_EMIF; 1695 1696 /* EMIF CE3 setup - 32 bit async. */ 1697 /* This is the PLD on the ASI5000 cards only */ 1698 setting = 1699 (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) | 1700 (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) | 1701 (2L << MTYPE_OFS); 1702 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting); 1703 if (setting != boot_loader_read_mem32(pao, dsp_index, 1704 0x01800014)) 1705 return HPI6205_ERROR_DSP_EMIF; 1706 1707 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */ 1708 /* need to use this else DSP code crashes? */ 1709 boot_loader_write_mem32(pao, dsp_index, 0x01800018, 1710 0x07117000); 1711 1712 /* EMIF SDRAM Refresh Timing */ 1713 /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */ 1714 boot_loader_write_mem32(pao, dsp_index, 0x0180001C, 1715 0x00000410); 1716 1717 } else if (dsp_index == 1) { 1718 /* test access to the C6713s HPI registers */ 1719 u32 write_data = 0, read_data = 0, i = 0; 1720 1721 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */ 1722 write_data = 1; 1723 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data); 1724 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data); 1725 /* C67 HPI is on lower 16bits of 32bit EMIF */ 1726 read_data = 1727 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR); 1728 if (write_data != read_data) { 1729 HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data, 1730 read_data); 1731 return HPI6205_ERROR_C6713_HPIC; 1732 } 1733 /* HPIA - walking ones test */ 1734 write_data = 1; 1735 for (i = 0; i < 32; i++) { 1736 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, 1737 write_data); 1738 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, 1739 (write_data >> 16)); 1740 read_data = 1741 0xFFFF & boot_loader_read_mem32(pao, 0, 1742 HPIAL_ADDR); 1743 read_data = 1744 read_data | ((0xFFFF & 1745 boot_loader_read_mem32(pao, 0, 1746 HPIAH_ADDR)) 1747 << 16); 1748 if (read_data != write_data) { 1749 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n", 1750 write_data, read_data); 1751 return HPI6205_ERROR_C6713_HPIA; 1752 } 1753 write_data = write_data << 1; 1754 } 1755 1756 /* setup C67x PLL 1757 * ** C6713 datasheet says we cannot program PLL from HPI, 1758 * and indeed if we try to set the PLL multiply from the HPI, 1759 * the PLL does not seem to lock, so we enable the PLL and 1760 * use the default multiply of x 7, which for a 27MHz clock 1761 * gives a DSP speed of 189MHz 1762 */ 1763 /* bypass PLL */ 1764 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000); 1765 hpios_delay_micro_seconds(1000); 1766 /* EMIF = 189/3=63MHz */ 1767 boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002); 1768 /* peri = 189/2 */ 1769 boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001); 1770 /* cpu = 189/1 */ 1771 boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000); 1772 hpios_delay_micro_seconds(1000); 1773 /* ** SGT test to take GPO3 high when we start the PLL */ 1774 /* and low when the delay is completed */ 1775 /* FSX0 <- '1' (GPO3) */ 1776 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A); 1777 /* PLL not bypassed */ 1778 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001); 1779 hpios_delay_micro_seconds(1000); 1780 /* FSX0 <- '0' (GPO3) */ 1781 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02); 1782 1783 /* 6205 EMIF CE1 resetup - 32 bit async. */ 1784 /* Now 6713 #1 is running at 189MHz can reduce waitstates */ 1785 boot_loader_write_mem32(pao, 0, 0x01800004, /* CE1 */ 1786 (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) | 1787 (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) | 1788 (2L << MTYPE_OFS)); 1789 1790 hpios_delay_micro_seconds(1000); 1791 1792 /* check that we can read one of the PLL registers */ 1793 /* PLL should not be bypassed! */ 1794 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF) 1795 != 0x0001) { 1796 return HPI6205_ERROR_C6713_PLL; 1797 } 1798 /* setup C67x EMIF (note this is the only use of 1799 BAR1 via BootLoader_WriteMem32) */ 1800 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL, 1801 0x000034A8); 1802 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0, 1803 0x00000030); 1804 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT, 1805 0x001BDF29); 1806 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL, 1807 0x47117000); 1808 boot_loader_write_mem32(pao, dsp_index, 1809 C6713_EMIF_SDRAMTIMING, 0x00000410); 1810 1811 hpios_delay_micro_seconds(1000); 1812 } else if (dsp_index == 2) { 1813 /* DSP 2 is a C6713 */ 1814 } 1815 1816 return 0; 1817 } 1818 1819 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, 1820 u32 start_address, u32 length) 1821 { 1822 u32 i = 0, j = 0; 1823 u32 test_addr = 0; 1824 u32 test_data = 0, data = 0; 1825 1826 length = 1000; 1827 1828 /* for 1st word, test each bit in the 32bit word, */ 1829 /* dwLength specifies number of 32bit words to test */ 1830 /*for(i=0; i<dwLength; i++) */ 1831 i = 0; 1832 { 1833 test_addr = start_address + i * 4; 1834 test_data = 0x00000001; 1835 for (j = 0; j < 32; j++) { 1836 boot_loader_write_mem32(pao, dsp_index, test_addr, 1837 test_data); 1838 data = boot_loader_read_mem32(pao, dsp_index, 1839 test_addr); 1840 if (data != test_data) { 1841 HPI_DEBUG_LOG(VERBOSE, 1842 "Memtest error details " 1843 "%08x %08x %08x %i\n", test_addr, 1844 test_data, data, dsp_index); 1845 return 1; /* error */ 1846 } 1847 test_data = test_data << 1; 1848 } /* for(j) */ 1849 } /* for(i) */ 1850 1851 /* for the next 100 locations test each location, leaving it as zero */ 1852 /* write a zero to the next word in memory before we read */ 1853 /* the previous write to make sure every memory location is unique */ 1854 for (i = 0; i < 100; i++) { 1855 test_addr = start_address + i * 4; 1856 test_data = 0xA5A55A5A; 1857 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data); 1858 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0); 1859 data = boot_loader_read_mem32(pao, dsp_index, test_addr); 1860 if (data != test_data) { 1861 HPI_DEBUG_LOG(VERBOSE, 1862 "Memtest error details " 1863 "%08x %08x %08x %i\n", test_addr, test_data, 1864 data, dsp_index); 1865 return 1; /* error */ 1866 } 1867 /* leave location as zero */ 1868 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); 1869 } 1870 1871 /* zero out entire memory block */ 1872 for (i = 0; i < length; i++) { 1873 test_addr = start_address + i * 4; 1874 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); 1875 } 1876 return 0; 1877 } 1878 1879 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, 1880 int dsp_index) 1881 { 1882 int err = 0; 1883 if (dsp_index == 0) { 1884 /* DSP 0 is a C6205 */ 1885 /* 64K prog mem */ 1886 err = boot_loader_test_memory(pao, dsp_index, 0x00000000, 1887 0x10000); 1888 if (!err) 1889 /* 64K data mem */ 1890 err = boot_loader_test_memory(pao, dsp_index, 1891 0x80000000, 0x10000); 1892 } else if (dsp_index == 1) { 1893 /* DSP 1 is a C6713 */ 1894 /* 192K internal mem */ 1895 err = boot_loader_test_memory(pao, dsp_index, 0x00000000, 1896 0x30000); 1897 if (!err) 1898 /* 64K internal mem / L2 cache */ 1899 err = boot_loader_test_memory(pao, dsp_index, 1900 0x00030000, 0x10000); 1901 } 1902 1903 if (err) 1904 return HPI6205_ERROR_DSP_INTMEM; 1905 else 1906 return 0; 1907 } 1908 1909 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, 1910 int dsp_index) 1911 { 1912 u32 dRAM_start_address = 0; 1913 u32 dRAM_size = 0; 1914 1915 if (dsp_index == 0) { 1916 /* only test for SDRAM if an ASI5000 card */ 1917 if (pao->pci.pci_dev->subsystem_device == 0x5000) { 1918 /* DSP 0 is always C6205 */ 1919 dRAM_start_address = 0x00400000; 1920 dRAM_size = 0x200000; 1921 /*dwDRAMinc=1024; */ 1922 } else 1923 return 0; 1924 } else if (dsp_index == 1) { 1925 /* DSP 1 is a C6713 */ 1926 dRAM_start_address = 0x80000000; 1927 dRAM_size = 0x200000; 1928 /*dwDRAMinc=1024; */ 1929 } 1930 1931 if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address, 1932 dRAM_size)) 1933 return HPI6205_ERROR_DSP_EXTMEM; 1934 return 0; 1935 } 1936 1937 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index) 1938 { 1939 u32 data = 0; 1940 if (dsp_index == 0) { 1941 /* only test for DSP0 PLD on ASI5000 card */ 1942 if (pao->pci.pci_dev->subsystem_device == 0x5000) { 1943 /* PLD is located at CE3=0x03000000 */ 1944 data = boot_loader_read_mem32(pao, dsp_index, 1945 0x03000008); 1946 if ((data & 0xF) != 0x5) 1947 return HPI6205_ERROR_DSP_PLD; 1948 data = boot_loader_read_mem32(pao, dsp_index, 1949 0x0300000C); 1950 if ((data & 0xF) != 0xA) 1951 return HPI6205_ERROR_DSP_PLD; 1952 } 1953 } else if (dsp_index == 1) { 1954 /* DSP 1 is a C6713 */ 1955 if (pao->pci.pci_dev->subsystem_device == 0x8700) { 1956 /* PLD is located at CE1=0x90000000 */ 1957 data = boot_loader_read_mem32(pao, dsp_index, 1958 0x90000010); 1959 if ((data & 0xFF) != 0xAA) 1960 return HPI6205_ERROR_DSP_PLD; 1961 /* 8713 - LED on */ 1962 boot_loader_write_mem32(pao, dsp_index, 0x90000000, 1963 0x02); 1964 } 1965 } 1966 return 0; 1967 } 1968 1969 /** Transfer data to or from DSP 1970 nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA 1971 */ 1972 static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data, 1973 u32 data_size, int operation) 1974 { 1975 struct hpi_hw_obj *phw = pao->priv; 1976 u32 data_transferred = 0; 1977 u16 err = 0; 1978 #ifndef HPI6205_NO_HSR_POLL 1979 u32 time_out; 1980 #endif 1981 u32 temp2; 1982 struct bus_master_interface *interface = phw->p_interface_buffer; 1983 1984 if (!p_data) 1985 return HPI_ERROR_INVALID_DATA_TRANSFER; 1986 1987 data_size &= ~3L; /* round data_size down to nearest 4 bytes */ 1988 1989 /* make sure state is IDLE */ 1990 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) 1991 return HPI_ERROR_DSP_HARDWARE; 1992 1993 while (data_transferred < data_size) { 1994 u32 this_copy = data_size - data_transferred; 1995 1996 if (this_copy > HPI6205_SIZEOF_DATA) 1997 this_copy = HPI6205_SIZEOF_DATA; 1998 1999 if (operation == H620_HIF_SEND_DATA) 2000 memcpy((void *)&interface->u.b_data[0], 2001 &p_data[data_transferred], this_copy); 2002 2003 interface->transfer_size_in_bytes = this_copy; 2004 2005 #ifdef HPI6205_NO_HSR_POLL 2006 /* DSP must change this back to nOperation */ 2007 interface->dsp_ack = H620_HIF_IDLE; 2008 #endif 2009 2010 send_dsp_command(phw, operation); 2011 2012 #ifdef HPI6205_NO_HSR_POLL 2013 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT); 2014 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n", 2015 HPI6205_TIMEOUT - temp2, this_copy); 2016 2017 if (!temp2) { 2018 /* timed out */ 2019 HPI_DEBUG_LOG(ERROR, 2020 "Timed out waiting for " "state %d got %d\n", 2021 operation, interface->dsp_ack); 2022 2023 break; 2024 } 2025 #else 2026 /* spin waiting on the result */ 2027 time_out = HPI6205_TIMEOUT; 2028 temp2 = 0; 2029 while ((temp2 == 0) && time_out--) { 2030 /* give 16k bus mastering transfer time to happen */ 2031 /*(16k / 132Mbytes/s = 122usec) */ 2032 hpios_delay_micro_seconds(20); 2033 temp2 = ioread32(phw->prHSR); 2034 temp2 &= C6205_HSR_INTSRC; 2035 } 2036 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n", 2037 HPI6205_TIMEOUT - time_out, this_copy); 2038 if (temp2 == C6205_HSR_INTSRC) { 2039 HPI_DEBUG_LOG(VERBOSE, 2040 "Interrupt from HIF <data> OK\n"); 2041 /* 2042 if(interface->dwDspAck != nOperation) { 2043 HPI_DEBUG_LOG(DEBUG("interface->dwDspAck=%d, 2044 expected %d \n", 2045 interface->dwDspAck,nOperation); 2046 } 2047 */ 2048 } 2049 /* need to handle this differently... */ 2050 else { 2051 HPI_DEBUG_LOG(ERROR, 2052 "Interrupt from HIF <data> BAD\n"); 2053 err = HPI_ERROR_DSP_HARDWARE; 2054 } 2055 2056 /* reset the interrupt from the DSP */ 2057 iowrite32(C6205_HSR_INTSRC, phw->prHSR); 2058 #endif 2059 if (operation == H620_HIF_GET_DATA) 2060 memcpy(&p_data[data_transferred], 2061 (void *)&interface->u.b_data[0], this_copy); 2062 2063 data_transferred += this_copy; 2064 } 2065 if (interface->dsp_ack != operation) 2066 HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n", 2067 interface->dsp_ack, operation); 2068 /* err=HPI_ERROR_DSP_HARDWARE; */ 2069 2070 send_dsp_command(phw, H620_HIF_IDLE); 2071 2072 return err; 2073 } 2074 2075 /* wait for up to timeout_us microseconds for the DSP 2076 to signal state by DMA into dwDspAck 2077 */ 2078 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us) 2079 { 2080 struct bus_master_interface *interface = phw->p_interface_buffer; 2081 int t = timeout_us / 4; 2082 2083 rmb(); /* ensure interface->dsp_ack is up to date */ 2084 while ((interface->dsp_ack != state) && --t) { 2085 hpios_delay_micro_seconds(4); 2086 rmb(); /* DSP changes dsp_ack by DMA */ 2087 } 2088 2089 /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */ 2090 return t * 4; 2091 } 2092 2093 /* set the busmaster interface to cmd, then interrupt the DSP */ 2094 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd) 2095 { 2096 struct bus_master_interface *interface = phw->p_interface_buffer; 2097 2098 u32 r; 2099 2100 interface->host_cmd = cmd; 2101 wmb(); /* DSP gets state by DMA, make sure it is written to memory */ 2102 /* before we interrupt the DSP */ 2103 r = ioread32(phw->prHDCR); 2104 r |= (u32)C6205_HDCR_DSPINT; 2105 iowrite32(r, phw->prHDCR); 2106 r &= ~(u32)C6205_HDCR_DSPINT; 2107 iowrite32(r, phw->prHDCR); 2108 } 2109 2110 static unsigned int message_count; 2111 2112 static u16 message_response_sequence(struct hpi_adapter_obj *pao, 2113 struct hpi_message *phm, struct hpi_response *phr) 2114 { 2115 #ifndef HPI6205_NO_HSR_POLL 2116 u32 temp2; 2117 #endif 2118 u32 time_out, time_out2; 2119 struct hpi_hw_obj *phw = pao->priv; 2120 struct bus_master_interface *interface = phw->p_interface_buffer; 2121 u16 err = 0; 2122 2123 message_count++; 2124 if (phm->size > sizeof(interface->u)) { 2125 /* really MESSAGE buffer too small */ 2126 phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; 2127 phr->specific_error = sizeof(interface->u); 2128 phr->size = sizeof(struct hpi_response_header); 2129 HPI_DEBUG_LOG(ERROR, 2130 "message len %d too big for buffer %ld \n", phm->size, 2131 sizeof(interface->u)); 2132 return 0; 2133 } 2134 2135 /* Assume buffer of type struct bus_master_interface 2136 is allocated "noncacheable" */ 2137 2138 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { 2139 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n"); 2140 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; 2141 } 2142 2143 memcpy(&interface->u.message_buffer, phm, phm->size); 2144 /* signal we want a response */ 2145 send_dsp_command(phw, H620_HIF_GET_RESP); 2146 2147 time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT); 2148 2149 if (!time_out2) { 2150 HPI_DEBUG_LOG(ERROR, 2151 "(%u) Timed out waiting for " "GET_RESP state [%x]\n", 2152 message_count, interface->dsp_ack); 2153 } else { 2154 HPI_DEBUG_LOG(VERBOSE, 2155 "(%u) transition to GET_RESP after %u\n", 2156 message_count, HPI6205_TIMEOUT - time_out2); 2157 } 2158 /* spin waiting on HIF interrupt flag (end of msg process) */ 2159 time_out = HPI6205_TIMEOUT; 2160 2161 #ifndef HPI6205_NO_HSR_POLL 2162 temp2 = 0; 2163 while ((temp2 == 0) && --time_out) { 2164 temp2 = ioread32(phw->prHSR); 2165 temp2 &= C6205_HSR_INTSRC; 2166 hpios_delay_micro_seconds(1); 2167 } 2168 if (temp2 == C6205_HSR_INTSRC) { 2169 rmb(); /* ensure we see latest value for dsp_ack */ 2170 if ((interface->dsp_ack != H620_HIF_GET_RESP)) { 2171 HPI_DEBUG_LOG(DEBUG, 2172 "(%u)interface->dsp_ack(0x%x) != " 2173 "H620_HIF_GET_RESP, t=%u\n", message_count, 2174 interface->dsp_ack, 2175 HPI6205_TIMEOUT - time_out); 2176 } else { 2177 HPI_DEBUG_LOG(VERBOSE, 2178 "(%u)int with GET_RESP after %u\n", 2179 message_count, HPI6205_TIMEOUT - time_out); 2180 } 2181 2182 } else { 2183 /* can we do anything else in response to the error ? */ 2184 HPI_DEBUG_LOG(ERROR, 2185 "Interrupt from HIF module BAD (function %x)\n", 2186 phm->function); 2187 } 2188 2189 /* reset the interrupt from the DSP */ 2190 iowrite32(C6205_HSR_INTSRC, phw->prHSR); 2191 #endif 2192 2193 /* read the result */ 2194 if (time_out) { 2195 if (interface->u.response_buffer.size <= phr->size) 2196 memcpy(phr, &interface->u.response_buffer, 2197 interface->u.response_buffer.size); 2198 else { 2199 HPI_DEBUG_LOG(ERROR, 2200 "response len %d too big for buffer %d\n", 2201 interface->u.response_buffer.size, phr->size); 2202 memcpy(phr, &interface->u.response_buffer, 2203 sizeof(struct hpi_response_header)); 2204 phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; 2205 phr->specific_error = 2206 interface->u.response_buffer.size; 2207 phr->size = sizeof(struct hpi_response_header); 2208 } 2209 } 2210 /* set interface back to idle */ 2211 send_dsp_command(phw, H620_HIF_IDLE); 2212 2213 if (!time_out || !time_out2) { 2214 HPI_DEBUG_LOG(DEBUG, "something timed out!\n"); 2215 return HPI6205_ERROR_MSG_RESP_TIMEOUT; 2216 } 2217 /* special case for adapter close - */ 2218 /* wait for the DSP to indicate it is idle */ 2219 if (phm->function == HPI_ADAPTER_CLOSE) { 2220 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { 2221 HPI_DEBUG_LOG(DEBUG, 2222 "Timeout waiting for idle " 2223 "(on adapter_close)\n"); 2224 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; 2225 } 2226 } 2227 err = hpi_validate_response(phm, phr); 2228 return err; 2229 } 2230 2231 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 2232 struct hpi_response *phr) 2233 { 2234 2235 u16 err = 0; 2236 2237 hpios_dsplock_lock(pao); 2238 2239 err = message_response_sequence(pao, phm, phr); 2240 2241 /* maybe an error response */ 2242 if (err) { 2243 /* something failed in the HPI/DSP interface */ 2244 phr->error = err; 2245 pao->dsp_crashed++; 2246 2247 /* just the header of the response is valid */ 2248 phr->size = sizeof(struct hpi_response_header); 2249 goto err; 2250 } else 2251 pao->dsp_crashed = 0; 2252 2253 if (phr->error != 0) /* something failed in the DSP */ 2254 goto err; 2255 2256 switch (phm->function) { 2257 case HPI_OSTREAM_WRITE: 2258 case HPI_ISTREAM_ANC_WRITE: 2259 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, 2260 phm->u.d.u.data.data_size, H620_HIF_SEND_DATA); 2261 break; 2262 2263 case HPI_ISTREAM_READ: 2264 case HPI_OSTREAM_ANC_READ: 2265 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, 2266 phm->u.d.u.data.data_size, H620_HIF_GET_DATA); 2267 break; 2268 2269 case HPI_CONTROL_SET_STATE: 2270 if (phm->object == HPI_OBJ_CONTROLEX 2271 && phm->u.cx.attribute == HPI_COBRANET_SET_DATA) 2272 err = hpi6205_transfer_data(pao, 2273 phm->u.cx.u.cobranet_bigdata.pb_data, 2274 phm->u.cx.u.cobranet_bigdata.byte_count, 2275 H620_HIF_SEND_DATA); 2276 break; 2277 2278 case HPI_CONTROL_GET_STATE: 2279 if (phm->object == HPI_OBJ_CONTROLEX 2280 && phm->u.cx.attribute == HPI_COBRANET_GET_DATA) 2281 err = hpi6205_transfer_data(pao, 2282 phm->u.cx.u.cobranet_bigdata.pb_data, 2283 phr->u.cx.u.cobranet_data.byte_count, 2284 H620_HIF_GET_DATA); 2285 break; 2286 } 2287 phr->error = err; 2288 2289 err: 2290 hpios_dsplock_unlock(pao); 2291 2292 return; 2293 } 2294