1 /****************************************************************************** 2 3 AudioScience HPI driver 4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of version 2 of the GNU General Public License as 8 published by the Free Software Foundation; 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 19 Hardware Programming Interface (HPI) for AudioScience 20 ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters. 21 These PCI and PCIe bus adapters are based on a 22 TMS320C6205 PCI bus mastering DSP, 23 and (except ASI50xx) TI TMS320C6xxx floating point DSP 24 25 Exported function: 26 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) 27 28 (C) Copyright AudioScience Inc. 1998-2010 29 *******************************************************************************/ 30 #define SOURCEFILE_NAME "hpi6205.c" 31 32 #include "hpi_internal.h" 33 #include "hpimsginit.h" 34 #include "hpidebug.h" 35 #include "hpi6205.h" 36 #include "hpidspcd.h" 37 #include "hpicmn.h" 38 39 /*****************************************************************************/ 40 /* HPI6205 specific error codes */ 41 #define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */ 42 43 /* operational/messaging errors */ 44 #define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015 45 #define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016 46 47 /* initialization/bootload errors */ 48 #define HPI6205_ERROR_6205_NO_IRQ 1002 49 #define HPI6205_ERROR_6205_INIT_FAILED 1003 50 #define HPI6205_ERROR_6205_REG 1006 51 #define HPI6205_ERROR_6205_DSPPAGE 1007 52 #define HPI6205_ERROR_C6713_HPIC 1009 53 #define HPI6205_ERROR_C6713_HPIA 1010 54 #define HPI6205_ERROR_C6713_PLL 1011 55 #define HPI6205_ERROR_DSP_INTMEM 1012 56 #define HPI6205_ERROR_DSP_EXTMEM 1013 57 #define HPI6205_ERROR_DSP_PLD 1014 58 #define HPI6205_ERROR_6205_EEPROM 1017 59 #define HPI6205_ERROR_DSP_EMIF 1018 60 61 /*****************************************************************************/ 62 /* for C6205 PCI i/f */ 63 /* Host Status Register (HSR) bitfields */ 64 #define C6205_HSR_INTSRC 0x01 65 #define C6205_HSR_INTAVAL 0x02 66 #define C6205_HSR_INTAM 0x04 67 #define C6205_HSR_CFGERR 0x08 68 #define C6205_HSR_EEREAD 0x10 69 /* Host-to-DSP Control Register (HDCR) bitfields */ 70 #define C6205_HDCR_WARMRESET 0x01 71 #define C6205_HDCR_DSPINT 0x02 72 #define C6205_HDCR_PCIBOOT 0x04 73 /* DSP Page Register (DSPP) bitfields, */ 74 /* defines 4 Mbyte page that BAR0 points to */ 75 #define C6205_DSPP_MAP1 0x400 76 77 /* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP. 78 * BAR1 maps to non-prefetchable 8 Mbyte memory block 79 * of DSP memory mapped registers (starting at 0x01800000). 80 * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this 81 * needs to be added to the BAR1 base address set in the PCI config reg 82 */ 83 #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L) 84 #define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET) 85 #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4) 86 #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8) 87 88 /* used to control LED (revA) and reset C6713 (revB) */ 89 #define C6205_BAR0_TIMER1_CTL (0x01980000L) 90 91 /* For first 6713 in CE1 space, using DA17,16,2 */ 92 #define HPICL_ADDR 0x01400000L 93 #define HPICH_ADDR 0x01400004L 94 #define HPIAL_ADDR 0x01410000L 95 #define HPIAH_ADDR 0x01410004L 96 #define HPIDIL_ADDR 0x01420000L 97 #define HPIDIH_ADDR 0x01420004L 98 #define HPIDL_ADDR 0x01430000L 99 #define HPIDH_ADDR 0x01430004L 100 101 #define C6713_EMIF_GCTL 0x01800000 102 #define C6713_EMIF_CE1 0x01800004 103 #define C6713_EMIF_CE0 0x01800008 104 #define C6713_EMIF_CE2 0x01800010 105 #define C6713_EMIF_CE3 0x01800014 106 #define C6713_EMIF_SDRAMCTL 0x01800018 107 #define C6713_EMIF_SDRAMTIMING 0x0180001C 108 #define C6713_EMIF_SDRAMEXT 0x01800020 109 110 struct hpi_hw_obj { 111 /* PCI registers */ 112 __iomem u32 *prHSR; 113 __iomem u32 *prHDCR; 114 __iomem u32 *prDSPP; 115 116 u32 dsp_page; 117 118 struct consistent_dma_area h_locked_mem; 119 struct bus_master_interface *p_interface_buffer; 120 121 u16 flag_outstream_just_reset[HPI_MAX_STREAMS]; 122 /* a non-NULL handle means there is an HPI allocated buffer */ 123 struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS]; 124 struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS]; 125 /* non-zero size means a buffer exists, may be external */ 126 u32 instream_host_buffer_size[HPI_MAX_STREAMS]; 127 u32 outstream_host_buffer_size[HPI_MAX_STREAMS]; 128 129 struct consistent_dma_area h_control_cache; 130 struct consistent_dma_area h_async_event_buffer; 131 /* struct hpi_control_cache_single *pControlCache; */ 132 struct hpi_async_event *p_async_event_buffer; 133 struct hpi_control_cache *p_cache; 134 }; 135 136 /*****************************************************************************/ 137 /* local prototypes */ 138 139 #define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write) 140 141 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us); 142 143 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd); 144 145 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 146 u32 *pos_error_code); 147 148 static u16 message_response_sequence(struct hpi_adapter_obj *pao, 149 struct hpi_message *phm, struct hpi_response *phr); 150 151 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 152 struct hpi_response *phr); 153 154 #define HPI6205_TIMEOUT 1000000 155 156 static void subsys_create_adapter(struct hpi_message *phm, 157 struct hpi_response *phr); 158 static void subsys_delete_adapter(struct hpi_message *phm, 159 struct hpi_response *phr); 160 161 static u16 create_adapter_obj(struct hpi_adapter_obj *pao, 162 u32 *pos_error_code); 163 164 static void delete_adapter_obj(struct hpi_adapter_obj *pao); 165 166 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, 167 struct hpi_message *phm, struct hpi_response *phr); 168 169 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, 170 struct hpi_message *phm, struct hpi_response *phr); 171 172 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, 173 struct hpi_message *phm, struct hpi_response *phr); 174 static void outstream_write(struct hpi_adapter_obj *pao, 175 struct hpi_message *phm, struct hpi_response *phr); 176 177 static void outstream_get_info(struct hpi_adapter_obj *pao, 178 struct hpi_message *phm, struct hpi_response *phr); 179 180 static void outstream_start(struct hpi_adapter_obj *pao, 181 struct hpi_message *phm, struct hpi_response *phr); 182 183 static void outstream_open(struct hpi_adapter_obj *pao, 184 struct hpi_message *phm, struct hpi_response *phr); 185 186 static void outstream_reset(struct hpi_adapter_obj *pao, 187 struct hpi_message *phm, struct hpi_response *phr); 188 189 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, 190 struct hpi_message *phm, struct hpi_response *phr); 191 192 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, 193 struct hpi_message *phm, struct hpi_response *phr); 194 195 static void instream_host_buffer_free(struct hpi_adapter_obj *pao, 196 struct hpi_message *phm, struct hpi_response *phr); 197 198 static void instream_read(struct hpi_adapter_obj *pao, 199 struct hpi_message *phm, struct hpi_response *phr); 200 201 static void instream_get_info(struct hpi_adapter_obj *pao, 202 struct hpi_message *phm, struct hpi_response *phr); 203 204 static void instream_start(struct hpi_adapter_obj *pao, 205 struct hpi_message *phm, struct hpi_response *phr); 206 207 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, 208 u32 address); 209 210 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, 211 int dsp_index, u32 address, u32 data); 212 213 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, 214 int dsp_index); 215 216 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, 217 u32 address, u32 length); 218 219 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, 220 int dsp_index); 221 222 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, 223 int dsp_index); 224 225 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index); 226 227 /*****************************************************************************/ 228 229 static void subsys_message(struct hpi_message *phm, struct hpi_response *phr) 230 { 231 switch (phm->function) { 232 case HPI_SUBSYS_CREATE_ADAPTER: 233 subsys_create_adapter(phm, phr); 234 break; 235 case HPI_SUBSYS_DELETE_ADAPTER: 236 subsys_delete_adapter(phm, phr); 237 break; 238 default: 239 phr->error = HPI_ERROR_INVALID_FUNC; 240 break; 241 } 242 } 243 244 static void control_message(struct hpi_adapter_obj *pao, 245 struct hpi_message *phm, struct hpi_response *phr) 246 { 247 248 struct hpi_hw_obj *phw = pao->priv; 249 u16 pending_cache_error = 0; 250 251 switch (phm->function) { 252 case HPI_CONTROL_GET_STATE: 253 if (pao->has_control_cache) { 254 rmb(); /* make sure we see updates DMAed from DSP */ 255 if (hpi_check_control_cache(phw->p_cache, phm, phr)) { 256 break; 257 } else if (phm->u.c.attribute == HPI_METER_PEAK) { 258 pending_cache_error = 259 HPI_ERROR_CONTROL_CACHING; 260 } 261 } 262 hw_message(pao, phm, phr); 263 if (pending_cache_error && !phr->error) 264 phr->error = pending_cache_error; 265 break; 266 case HPI_CONTROL_GET_INFO: 267 hw_message(pao, phm, phr); 268 break; 269 case HPI_CONTROL_SET_STATE: 270 hw_message(pao, phm, phr); 271 if (pao->has_control_cache) 272 hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm, 273 phr); 274 break; 275 default: 276 phr->error = HPI_ERROR_INVALID_FUNC; 277 break; 278 } 279 } 280 281 static void adapter_message(struct hpi_adapter_obj *pao, 282 struct hpi_message *phm, struct hpi_response *phr) 283 { 284 switch (phm->function) { 285 default: 286 hw_message(pao, phm, phr); 287 break; 288 } 289 } 290 291 static void outstream_message(struct hpi_adapter_obj *pao, 292 struct hpi_message *phm, struct hpi_response *phr) 293 { 294 295 if (phm->obj_index >= HPI_MAX_STREAMS) { 296 phr->error = HPI_ERROR_INVALID_OBJ_INDEX; 297 HPI_DEBUG_LOG(WARNING, 298 "Message referencing invalid stream %d " 299 "on adapter index %d\n", phm->obj_index, 300 phm->adapter_index); 301 return; 302 } 303 304 switch (phm->function) { 305 case HPI_OSTREAM_WRITE: 306 outstream_write(pao, phm, phr); 307 break; 308 case HPI_OSTREAM_GET_INFO: 309 outstream_get_info(pao, phm, phr); 310 break; 311 case HPI_OSTREAM_HOSTBUFFER_ALLOC: 312 outstream_host_buffer_allocate(pao, phm, phr); 313 break; 314 case HPI_OSTREAM_HOSTBUFFER_GET_INFO: 315 outstream_host_buffer_get_info(pao, phm, phr); 316 break; 317 case HPI_OSTREAM_HOSTBUFFER_FREE: 318 outstream_host_buffer_free(pao, phm, phr); 319 break; 320 case HPI_OSTREAM_START: 321 outstream_start(pao, phm, phr); 322 break; 323 case HPI_OSTREAM_OPEN: 324 outstream_open(pao, phm, phr); 325 break; 326 case HPI_OSTREAM_RESET: 327 outstream_reset(pao, phm, phr); 328 break; 329 default: 330 hw_message(pao, phm, phr); 331 break; 332 } 333 } 334 335 static void instream_message(struct hpi_adapter_obj *pao, 336 struct hpi_message *phm, struct hpi_response *phr) 337 { 338 339 if (phm->obj_index >= HPI_MAX_STREAMS) { 340 phr->error = HPI_ERROR_INVALID_OBJ_INDEX; 341 HPI_DEBUG_LOG(WARNING, 342 "Message referencing invalid stream %d " 343 "on adapter index %d\n", phm->obj_index, 344 phm->adapter_index); 345 return; 346 } 347 348 switch (phm->function) { 349 case HPI_ISTREAM_READ: 350 instream_read(pao, phm, phr); 351 break; 352 case HPI_ISTREAM_GET_INFO: 353 instream_get_info(pao, phm, phr); 354 break; 355 case HPI_ISTREAM_HOSTBUFFER_ALLOC: 356 instream_host_buffer_allocate(pao, phm, phr); 357 break; 358 case HPI_ISTREAM_HOSTBUFFER_GET_INFO: 359 instream_host_buffer_get_info(pao, phm, phr); 360 break; 361 case HPI_ISTREAM_HOSTBUFFER_FREE: 362 instream_host_buffer_free(pao, phm, phr); 363 break; 364 case HPI_ISTREAM_START: 365 instream_start(pao, phm, phr); 366 break; 367 default: 368 hw_message(pao, phm, phr); 369 break; 370 } 371 } 372 373 /*****************************************************************************/ 374 /** Entry point to this HPI backend 375 * All calls to the HPI start here 376 */ 377 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) 378 { 379 struct hpi_adapter_obj *pao = NULL; 380 381 /* subsytem messages are processed by every HPI. 382 * All other messages are ignored unless the adapter index matches 383 * an adapter in the HPI 384 */ 385 /* HPI_DEBUG_LOG(DEBUG, "HPI Obj=%d, Func=%d\n", phm->wObject, 386 phm->wFunction); */ 387 388 /* if Dsp has crashed then do not communicate with it any more */ 389 if (phm->object != HPI_OBJ_SUBSYSTEM) { 390 pao = hpi_find_adapter(phm->adapter_index); 391 if (!pao) { 392 HPI_DEBUG_LOG(DEBUG, 393 " %d,%d refused, for another HPI?\n", 394 phm->object, phm->function); 395 return; 396 } 397 398 if ((pao->dsp_crashed >= 10) 399 && (phm->function != HPI_ADAPTER_DEBUG_READ)) { 400 /* allow last resort debug read even after crash */ 401 hpi_init_response(phr, phm->object, phm->function, 402 HPI_ERROR_DSP_HARDWARE); 403 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", 404 phm->object, phm->function); 405 return; 406 } 407 } 408 409 /* Init default response */ 410 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER) 411 phr->error = HPI_ERROR_PROCESSING_MESSAGE; 412 413 HPI_DEBUG_LOG(VERBOSE, "start of switch\n"); 414 switch (phm->type) { 415 case HPI_TYPE_MESSAGE: 416 switch (phm->object) { 417 case HPI_OBJ_SUBSYSTEM: 418 subsys_message(phm, phr); 419 break; 420 421 case HPI_OBJ_ADAPTER: 422 adapter_message(pao, phm, phr); 423 break; 424 425 case HPI_OBJ_CONTROLEX: 426 case HPI_OBJ_CONTROL: 427 control_message(pao, phm, phr); 428 break; 429 430 case HPI_OBJ_OSTREAM: 431 outstream_message(pao, phm, phr); 432 break; 433 434 case HPI_OBJ_ISTREAM: 435 instream_message(pao, phm, phr); 436 break; 437 438 default: 439 hw_message(pao, phm, phr); 440 break; 441 } 442 break; 443 444 default: 445 phr->error = HPI_ERROR_INVALID_TYPE; 446 break; 447 } 448 } 449 450 /*****************************************************************************/ 451 /* SUBSYSTEM */ 452 453 /** Create an adapter object and initialise it based on resource information 454 * passed in in the message 455 * *** NOTE - you cannot use this function AND the FindAdapters function at the 456 * same time, the application must use only one of them to get the adapters *** 457 */ 458 static void subsys_create_adapter(struct hpi_message *phm, 459 struct hpi_response *phr) 460 { 461 /* create temp adapter obj, because we don't know what index yet */ 462 struct hpi_adapter_obj ao; 463 u32 os_error_code; 464 u16 err; 465 466 HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n"); 467 468 memset(&ao, 0, sizeof(ao)); 469 470 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL); 471 if (!ao.priv) { 472 HPI_DEBUG_LOG(ERROR, "cant get mem for adapter object\n"); 473 phr->error = HPI_ERROR_MEMORY_ALLOC; 474 return; 475 } 476 477 ao.pci = *phm->u.s.resource.r.pci; 478 err = create_adapter_obj(&ao, &os_error_code); 479 if (err) { 480 delete_adapter_obj(&ao); 481 if (err >= HPI_ERROR_BACKEND_BASE) { 482 phr->error = HPI_ERROR_DSP_BOOTLOAD; 483 phr->specific_error = err; 484 } else { 485 phr->error = err; 486 } 487 phr->u.s.data = os_error_code; 488 return; 489 } 490 491 phr->u.s.adapter_type = ao.adapter_type; 492 phr->u.s.adapter_index = ao.index; 493 phr->error = 0; 494 } 495 496 /** delete an adapter - required by WDM driver */ 497 static void subsys_delete_adapter(struct hpi_message *phm, 498 struct hpi_response *phr) 499 { 500 struct hpi_adapter_obj *pao; 501 struct hpi_hw_obj *phw; 502 503 pao = hpi_find_adapter(phm->obj_index); 504 if (!pao) { 505 phr->error = HPI_ERROR_INVALID_OBJ_INDEX; 506 return; 507 } 508 phw = (struct hpi_hw_obj *)pao->priv; 509 /* reset adapter h/w */ 510 /* Reset C6713 #1 */ 511 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); 512 /* reset C6205 */ 513 iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR); 514 515 delete_adapter_obj(pao); 516 hpi_delete_adapter(pao); 517 phr->error = 0; 518 } 519 520 /** Create adapter object 521 allocate buffers, bootload DSPs, initialise control cache 522 */ 523 static u16 create_adapter_obj(struct hpi_adapter_obj *pao, 524 u32 *pos_error_code) 525 { 526 struct hpi_hw_obj *phw = pao->priv; 527 struct bus_master_interface *interface; 528 u32 phys_addr; 529 int i; 530 u16 err; 531 532 /* init error reporting */ 533 pao->dsp_crashed = 0; 534 535 for (i = 0; i < HPI_MAX_STREAMS; i++) 536 phw->flag_outstream_just_reset[i] = 1; 537 538 /* The C6205 memory area 1 is 8Mbyte window into DSP registers */ 539 phw->prHSR = 540 pao->pci.ap_mem_base[1] + 541 C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]); 542 phw->prHDCR = 543 pao->pci.ap_mem_base[1] + 544 C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]); 545 phw->prDSPP = 546 pao->pci.ap_mem_base[1] + 547 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]); 548 549 pao->has_control_cache = 0; 550 551 if (hpios_locked_mem_alloc(&phw->h_locked_mem, 552 sizeof(struct bus_master_interface), 553 pao->pci.pci_dev)) 554 phw->p_interface_buffer = NULL; 555 else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem, 556 (void *)&phw->p_interface_buffer)) 557 phw->p_interface_buffer = NULL; 558 559 HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n", 560 phw->p_interface_buffer); 561 562 if (phw->p_interface_buffer) { 563 memset((void *)phw->p_interface_buffer, 0, 564 sizeof(struct bus_master_interface)); 565 phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN; 566 } 567 568 err = adapter_boot_load_dsp(pao, pos_error_code); 569 if (err) 570 /* no need to clean up as SubSysCreateAdapter */ 571 /* calls DeleteAdapter on error. */ 572 return err; 573 574 HPI_DEBUG_LOG(INFO, "load DSP code OK\n"); 575 576 /* allow boot load even if mem alloc wont work */ 577 if (!phw->p_interface_buffer) 578 return HPI_ERROR_MEMORY_ALLOC; 579 580 interface = phw->p_interface_buffer; 581 582 /* make sure the DSP has started ok */ 583 if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) { 584 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n"); 585 return HPI6205_ERROR_6205_INIT_FAILED; 586 } 587 /* Note that *pao, *phw are zeroed after allocation, 588 * so pointers and flags are NULL by default. 589 * Allocate bus mastering control cache buffer and tell the DSP about it 590 */ 591 if (interface->control_cache.number_of_controls) { 592 u8 *p_control_cache_virtual; 593 594 err = hpios_locked_mem_alloc(&phw->h_control_cache, 595 interface->control_cache.size_in_bytes, 596 pao->pci.pci_dev); 597 if (!err) 598 err = hpios_locked_mem_get_virt_addr(&phw-> 599 h_control_cache, 600 (void *)&p_control_cache_virtual); 601 if (!err) { 602 memset(p_control_cache_virtual, 0, 603 interface->control_cache.size_in_bytes); 604 605 phw->p_cache = 606 hpi_alloc_control_cache(interface-> 607 control_cache.number_of_controls, 608 interface->control_cache.size_in_bytes, 609 p_control_cache_virtual); 610 if (!phw->p_cache) 611 err = HPI_ERROR_MEMORY_ALLOC; 612 } 613 if (!err) { 614 err = hpios_locked_mem_get_phys_addr(&phw-> 615 h_control_cache, &phys_addr); 616 interface->control_cache.physical_address32 = 617 phys_addr; 618 } 619 620 if (!err) 621 pao->has_control_cache = 1; 622 else { 623 if (hpios_locked_mem_valid(&phw->h_control_cache)) 624 hpios_locked_mem_free(&phw->h_control_cache); 625 pao->has_control_cache = 0; 626 } 627 } 628 /* allocate bus mastering async buffer and tell the DSP about it */ 629 if (interface->async_buffer.b.size) { 630 err = hpios_locked_mem_alloc(&phw->h_async_event_buffer, 631 interface->async_buffer.b.size * 632 sizeof(struct hpi_async_event), pao->pci.pci_dev); 633 if (!err) 634 err = hpios_locked_mem_get_virt_addr 635 (&phw->h_async_event_buffer, (void *) 636 &phw->p_async_event_buffer); 637 if (!err) 638 memset((void *)phw->p_async_event_buffer, 0, 639 interface->async_buffer.b.size * 640 sizeof(struct hpi_async_event)); 641 if (!err) { 642 err = hpios_locked_mem_get_phys_addr 643 (&phw->h_async_event_buffer, &phys_addr); 644 interface->async_buffer.physical_address32 = 645 phys_addr; 646 } 647 if (err) { 648 if (hpios_locked_mem_valid(&phw-> 649 h_async_event_buffer)) { 650 hpios_locked_mem_free 651 (&phw->h_async_event_buffer); 652 phw->p_async_event_buffer = NULL; 653 } 654 } 655 } 656 send_dsp_command(phw, H620_HIF_IDLE); 657 658 { 659 struct hpi_message hm; 660 struct hpi_response hr; 661 u32 max_streams; 662 663 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n"); 664 memset(&hm, 0, sizeof(hm)); 665 hm.type = HPI_TYPE_MESSAGE; 666 hm.size = sizeof(hm); 667 hm.object = HPI_OBJ_ADAPTER; 668 hm.function = HPI_ADAPTER_GET_INFO; 669 hm.adapter_index = 0; 670 memset(&hr, 0, sizeof(hr)); 671 hr.size = sizeof(hr); 672 673 err = message_response_sequence(pao, &hm, &hr); 674 if (err) { 675 HPI_DEBUG_LOG(ERROR, "message transport error %d\n", 676 err); 677 return err; 678 } 679 if (hr.error) 680 return hr.error; 681 682 pao->adapter_type = hr.u.ax.info.adapter_type; 683 pao->index = hr.u.ax.info.adapter_index; 684 685 max_streams = 686 hr.u.ax.info.num_outstreams + 687 hr.u.ax.info.num_instreams; 688 689 hpios_locked_mem_prepare((max_streams * 6) / 10, max_streams, 690 65536, pao->pci.pci_dev); 691 692 HPI_DEBUG_LOG(VERBOSE, 693 "got adapter info type %x index %d serial %d\n", 694 hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index, 695 hr.u.ax.info.serial_number); 696 } 697 698 pao->open = 0; /* upon creation the adapter is closed */ 699 700 if (phw->p_cache) 701 phw->p_cache->adap_idx = pao->index; 702 703 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n"); 704 705 return hpi_add_adapter(pao); 706 } 707 708 /** Free memory areas allocated by adapter 709 * this routine is called from SubSysDeleteAdapter, 710 * and SubSysCreateAdapter if duplicate index 711 */ 712 static void delete_adapter_obj(struct hpi_adapter_obj *pao) 713 { 714 struct hpi_hw_obj *phw; 715 int i; 716 717 phw = pao->priv; 718 719 if (hpios_locked_mem_valid(&phw->h_async_event_buffer)) { 720 hpios_locked_mem_free(&phw->h_async_event_buffer); 721 phw->p_async_event_buffer = NULL; 722 } 723 724 if (hpios_locked_mem_valid(&phw->h_control_cache)) { 725 hpios_locked_mem_free(&phw->h_control_cache); 726 hpi_free_control_cache(phw->p_cache); 727 } 728 729 if (hpios_locked_mem_valid(&phw->h_locked_mem)) { 730 hpios_locked_mem_free(&phw->h_locked_mem); 731 phw->p_interface_buffer = NULL; 732 } 733 734 for (i = 0; i < HPI_MAX_STREAMS; i++) 735 if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) { 736 hpios_locked_mem_free(&phw->instream_host_buffers[i]); 737 /*?phw->InStreamHostBuffers[i] = NULL; */ 738 phw->instream_host_buffer_size[i] = 0; 739 } 740 741 for (i = 0; i < HPI_MAX_STREAMS; i++) 742 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) { 743 hpios_locked_mem_free(&phw->outstream_host_buffers 744 [i]); 745 phw->outstream_host_buffer_size[i] = 0; 746 } 747 748 hpios_locked_mem_unprepare(pao->pci.pci_dev); 749 750 kfree(phw); 751 } 752 753 /*****************************************************************************/ 754 /* Adapter functions */ 755 756 /*****************************************************************************/ 757 /* OutStream Host buffer functions */ 758 759 /** Allocate or attach buffer for busmastering 760 */ 761 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, 762 struct hpi_message *phm, struct hpi_response *phr) 763 { 764 u16 err = 0; 765 u32 command = phm->u.d.u.buffer.command; 766 struct hpi_hw_obj *phw = pao->priv; 767 struct bus_master_interface *interface = phw->p_interface_buffer; 768 769 hpi_init_response(phr, phm->object, phm->function, 0); 770 771 if (command == HPI_BUFFER_CMD_EXTERNAL 772 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { 773 /* ALLOC phase, allocate a buffer with power of 2 size, 774 get its bus address for PCI bus mastering 775 */ 776 phm->u.d.u.buffer.buffer_size = 777 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); 778 /* return old size and allocated size, 779 so caller can detect change */ 780 phr->u.d.u.stream_info.data_available = 781 phw->outstream_host_buffer_size[phm->obj_index]; 782 phr->u.d.u.stream_info.buffer_size = 783 phm->u.d.u.buffer.buffer_size; 784 785 if (phw->outstream_host_buffer_size[phm->obj_index] == 786 phm->u.d.u.buffer.buffer_size) { 787 /* Same size, no action required */ 788 return; 789 } 790 791 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 792 obj_index])) 793 hpios_locked_mem_free(&phw->outstream_host_buffers 794 [phm->obj_index]); 795 796 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers 797 [phm->obj_index], phm->u.d.u.buffer.buffer_size, 798 pao->pci.pci_dev); 799 800 if (err) { 801 phr->error = HPI_ERROR_INVALID_DATASIZE; 802 phw->outstream_host_buffer_size[phm->obj_index] = 0; 803 return; 804 } 805 806 err = hpios_locked_mem_get_phys_addr 807 (&phw->outstream_host_buffers[phm->obj_index], 808 &phm->u.d.u.buffer.pci_address); 809 /* get the phys addr into msg for single call alloc caller 810 * needs to do this for split alloc (or use the same message) 811 * return the phy address for split alloc in the respose too 812 */ 813 phr->u.d.u.stream_info.auxiliary_data_available = 814 phm->u.d.u.buffer.pci_address; 815 816 if (err) { 817 hpios_locked_mem_free(&phw->outstream_host_buffers 818 [phm->obj_index]); 819 phw->outstream_host_buffer_size[phm->obj_index] = 0; 820 phr->error = HPI_ERROR_MEMORY_ALLOC; 821 return; 822 } 823 } 824 825 if (command == HPI_BUFFER_CMD_EXTERNAL 826 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { 827 /* GRANT phase. Set up the BBM status, tell the DSP about 828 the buffer so it can start using BBM. 829 */ 830 struct hpi_hostbuffer_status *status; 831 832 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. 833 buffer_size - 1)) { 834 HPI_DEBUG_LOG(ERROR, 835 "Buffer size must be 2^N not %d\n", 836 phm->u.d.u.buffer.buffer_size); 837 phr->error = HPI_ERROR_INVALID_DATASIZE; 838 return; 839 } 840 phw->outstream_host_buffer_size[phm->obj_index] = 841 phm->u.d.u.buffer.buffer_size; 842 status = &interface->outstream_host_buffer_status[phm-> 843 obj_index]; 844 status->samples_processed = 0; 845 status->stream_state = HPI_STATE_STOPPED; 846 status->dSP_index = 0; 847 status->host_index = status->dSP_index; 848 status->size_in_bytes = phm->u.d.u.buffer.buffer_size; 849 status->auxiliary_data_available = 0; 850 851 hw_message(pao, phm, phr); 852 853 if (phr->error 854 && hpios_locked_mem_valid(&phw-> 855 outstream_host_buffers[phm->obj_index])) { 856 hpios_locked_mem_free(&phw->outstream_host_buffers 857 [phm->obj_index]); 858 phw->outstream_host_buffer_size[phm->obj_index] = 0; 859 } 860 } 861 } 862 863 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, 864 struct hpi_message *phm, struct hpi_response *phr) 865 { 866 struct hpi_hw_obj *phw = pao->priv; 867 struct bus_master_interface *interface = phw->p_interface_buffer; 868 struct hpi_hostbuffer_status *status; 869 u8 *p_bbm_data; 870 871 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 872 obj_index])) { 873 if (hpios_locked_mem_get_virt_addr(&phw-> 874 outstream_host_buffers[phm->obj_index], 875 (void *)&p_bbm_data)) { 876 phr->error = HPI_ERROR_INVALID_OPERATION; 877 return; 878 } 879 status = &interface->outstream_host_buffer_status[phm-> 880 obj_index]; 881 hpi_init_response(phr, HPI_OBJ_OSTREAM, 882 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0); 883 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; 884 phr->u.d.u.hostbuffer_info.p_status = status; 885 } else { 886 hpi_init_response(phr, HPI_OBJ_OSTREAM, 887 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 888 HPI_ERROR_INVALID_OPERATION); 889 } 890 } 891 892 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, 893 struct hpi_message *phm, struct hpi_response *phr) 894 { 895 struct hpi_hw_obj *phw = pao->priv; 896 u32 command = phm->u.d.u.buffer.command; 897 898 if (phw->outstream_host_buffer_size[phm->obj_index]) { 899 if (command == HPI_BUFFER_CMD_EXTERNAL 900 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { 901 phw->outstream_host_buffer_size[phm->obj_index] = 0; 902 hw_message(pao, phm, phr); 903 /* Tell adapter to stop using the host buffer. */ 904 } 905 if (command == HPI_BUFFER_CMD_EXTERNAL 906 || command == HPI_BUFFER_CMD_INTERNAL_FREE) 907 hpios_locked_mem_free(&phw->outstream_host_buffers 908 [phm->obj_index]); 909 } 910 /* Should HPI_ERROR_INVALID_OPERATION be returned 911 if no host buffer is allocated? */ 912 else 913 hpi_init_response(phr, HPI_OBJ_OSTREAM, 914 HPI_OSTREAM_HOSTBUFFER_FREE, 0); 915 916 } 917 918 static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status) 919 { 920 return status->size_in_bytes - (status->host_index - 921 status->dSP_index); 922 } 923 924 static void outstream_write(struct hpi_adapter_obj *pao, 925 struct hpi_message *phm, struct hpi_response *phr) 926 { 927 struct hpi_hw_obj *phw = pao->priv; 928 struct bus_master_interface *interface = phw->p_interface_buffer; 929 struct hpi_hostbuffer_status *status; 930 u32 space_available; 931 932 if (!phw->outstream_host_buffer_size[phm->obj_index]) { 933 /* there is no BBM buffer, write via message */ 934 hw_message(pao, phm, phr); 935 return; 936 } 937 938 hpi_init_response(phr, phm->object, phm->function, 0); 939 status = &interface->outstream_host_buffer_status[phm->obj_index]; 940 941 space_available = outstream_get_space_available(status); 942 if (space_available < phm->u.d.u.data.data_size) { 943 phr->error = HPI_ERROR_INVALID_DATASIZE; 944 return; 945 } 946 947 /* HostBuffers is used to indicate host buffer is internally allocated. 948 otherwise, assumed external, data written externally */ 949 if (phm->u.d.u.data.pb_data 950 && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 951 obj_index])) { 952 u8 *p_bbm_data; 953 u32 l_first_write; 954 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; 955 956 if (hpios_locked_mem_get_virt_addr(&phw-> 957 outstream_host_buffers[phm->obj_index], 958 (void *)&p_bbm_data)) { 959 phr->error = HPI_ERROR_INVALID_OPERATION; 960 return; 961 } 962 963 /* either all data, 964 or enough to fit from current to end of BBM buffer */ 965 l_first_write = 966 min(phm->u.d.u.data.data_size, 967 status->size_in_bytes - 968 (status->host_index & (status->size_in_bytes - 1))); 969 970 memcpy(p_bbm_data + 971 (status->host_index & (status->size_in_bytes - 1)), 972 p_app_data, l_first_write); 973 /* remaining data if any */ 974 memcpy(p_bbm_data, p_app_data + l_first_write, 975 phm->u.d.u.data.data_size - l_first_write); 976 } 977 978 /* 979 * This version relies on the DSP code triggering an OStream buffer 980 * update immediately following a SET_FORMAT call. The host has 981 * already written data into the BBM buffer, but the DSP won't know 982 * about it until dwHostIndex is adjusted. 983 */ 984 if (phw->flag_outstream_just_reset[phm->obj_index]) { 985 /* Format can only change after reset. Must tell DSP. */ 986 u16 function = phm->function; 987 phw->flag_outstream_just_reset[phm->obj_index] = 0; 988 phm->function = HPI_OSTREAM_SET_FORMAT; 989 hw_message(pao, phm, phr); /* send the format to the DSP */ 990 phm->function = function; 991 if (phr->error) 992 return; 993 } 994 995 status->host_index += phm->u.d.u.data.data_size; 996 } 997 998 static void outstream_get_info(struct hpi_adapter_obj *pao, 999 struct hpi_message *phm, struct hpi_response *phr) 1000 { 1001 struct hpi_hw_obj *phw = pao->priv; 1002 struct bus_master_interface *interface = phw->p_interface_buffer; 1003 struct hpi_hostbuffer_status *status; 1004 1005 if (!phw->outstream_host_buffer_size[phm->obj_index]) { 1006 hw_message(pao, phm, phr); 1007 return; 1008 } 1009 1010 hpi_init_response(phr, phm->object, phm->function, 0); 1011 1012 status = &interface->outstream_host_buffer_status[phm->obj_index]; 1013 1014 phr->u.d.u.stream_info.state = (u16)status->stream_state; 1015 phr->u.d.u.stream_info.samples_transferred = 1016 status->samples_processed; 1017 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; 1018 phr->u.d.u.stream_info.data_available = 1019 status->size_in_bytes - outstream_get_space_available(status); 1020 phr->u.d.u.stream_info.auxiliary_data_available = 1021 status->auxiliary_data_available; 1022 } 1023 1024 static void outstream_start(struct hpi_adapter_obj *pao, 1025 struct hpi_message *phm, struct hpi_response *phr) 1026 { 1027 hw_message(pao, phm, phr); 1028 } 1029 1030 static void outstream_reset(struct hpi_adapter_obj *pao, 1031 struct hpi_message *phm, struct hpi_response *phr) 1032 { 1033 struct hpi_hw_obj *phw = pao->priv; 1034 phw->flag_outstream_just_reset[phm->obj_index] = 1; 1035 hw_message(pao, phm, phr); 1036 } 1037 1038 static void outstream_open(struct hpi_adapter_obj *pao, 1039 struct hpi_message *phm, struct hpi_response *phr) 1040 { 1041 outstream_reset(pao, phm, phr); 1042 } 1043 1044 /*****************************************************************************/ 1045 /* InStream Host buffer functions */ 1046 1047 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, 1048 struct hpi_message *phm, struct hpi_response *phr) 1049 { 1050 u16 err = 0; 1051 u32 command = phm->u.d.u.buffer.command; 1052 struct hpi_hw_obj *phw = pao->priv; 1053 struct bus_master_interface *interface = phw->p_interface_buffer; 1054 1055 hpi_init_response(phr, phm->object, phm->function, 0); 1056 1057 if (command == HPI_BUFFER_CMD_EXTERNAL 1058 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { 1059 1060 phm->u.d.u.buffer.buffer_size = 1061 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); 1062 phr->u.d.u.stream_info.data_available = 1063 phw->instream_host_buffer_size[phm->obj_index]; 1064 phr->u.d.u.stream_info.buffer_size = 1065 phm->u.d.u.buffer.buffer_size; 1066 1067 if (phw->instream_host_buffer_size[phm->obj_index] == 1068 phm->u.d.u.buffer.buffer_size) { 1069 /* Same size, no action required */ 1070 return; 1071 } 1072 1073 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1074 obj_index])) 1075 hpios_locked_mem_free(&phw->instream_host_buffers 1076 [phm->obj_index]); 1077 1078 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm-> 1079 obj_index], phm->u.d.u.buffer.buffer_size, 1080 pao->pci.pci_dev); 1081 1082 if (err) { 1083 phr->error = HPI_ERROR_INVALID_DATASIZE; 1084 phw->instream_host_buffer_size[phm->obj_index] = 0; 1085 return; 1086 } 1087 1088 err = hpios_locked_mem_get_phys_addr 1089 (&phw->instream_host_buffers[phm->obj_index], 1090 &phm->u.d.u.buffer.pci_address); 1091 /* get the phys addr into msg for single call alloc. Caller 1092 needs to do this for split alloc so return the phy address */ 1093 phr->u.d.u.stream_info.auxiliary_data_available = 1094 phm->u.d.u.buffer.pci_address; 1095 if (err) { 1096 hpios_locked_mem_free(&phw->instream_host_buffers 1097 [phm->obj_index]); 1098 phw->instream_host_buffer_size[phm->obj_index] = 0; 1099 phr->error = HPI_ERROR_MEMORY_ALLOC; 1100 return; 1101 } 1102 } 1103 1104 if (command == HPI_BUFFER_CMD_EXTERNAL 1105 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { 1106 struct hpi_hostbuffer_status *status; 1107 1108 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. 1109 buffer_size - 1)) { 1110 HPI_DEBUG_LOG(ERROR, 1111 "Buffer size must be 2^N not %d\n", 1112 phm->u.d.u.buffer.buffer_size); 1113 phr->error = HPI_ERROR_INVALID_DATASIZE; 1114 return; 1115 } 1116 1117 phw->instream_host_buffer_size[phm->obj_index] = 1118 phm->u.d.u.buffer.buffer_size; 1119 status = &interface->instream_host_buffer_status[phm-> 1120 obj_index]; 1121 status->samples_processed = 0; 1122 status->stream_state = HPI_STATE_STOPPED; 1123 status->dSP_index = 0; 1124 status->host_index = status->dSP_index; 1125 status->size_in_bytes = phm->u.d.u.buffer.buffer_size; 1126 status->auxiliary_data_available = 0; 1127 1128 hw_message(pao, phm, phr); 1129 if (phr->error 1130 && hpios_locked_mem_valid(&phw-> 1131 instream_host_buffers[phm->obj_index])) { 1132 hpios_locked_mem_free(&phw->instream_host_buffers 1133 [phm->obj_index]); 1134 phw->instream_host_buffer_size[phm->obj_index] = 0; 1135 } 1136 } 1137 } 1138 1139 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, 1140 struct hpi_message *phm, struct hpi_response *phr) 1141 { 1142 struct hpi_hw_obj *phw = pao->priv; 1143 struct bus_master_interface *interface = phw->p_interface_buffer; 1144 struct hpi_hostbuffer_status *status; 1145 u8 *p_bbm_data; 1146 1147 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1148 obj_index])) { 1149 if (hpios_locked_mem_get_virt_addr(&phw-> 1150 instream_host_buffers[phm->obj_index], 1151 (void *)&p_bbm_data)) { 1152 phr->error = HPI_ERROR_INVALID_OPERATION; 1153 return; 1154 } 1155 status = &interface->instream_host_buffer_status[phm-> 1156 obj_index]; 1157 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1158 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0); 1159 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; 1160 phr->u.d.u.hostbuffer_info.p_status = status; 1161 } else { 1162 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1163 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 1164 HPI_ERROR_INVALID_OPERATION); 1165 } 1166 } 1167 1168 static void instream_host_buffer_free(struct hpi_adapter_obj *pao, 1169 struct hpi_message *phm, struct hpi_response *phr) 1170 { 1171 struct hpi_hw_obj *phw = pao->priv; 1172 u32 command = phm->u.d.u.buffer.command; 1173 1174 if (phw->instream_host_buffer_size[phm->obj_index]) { 1175 if (command == HPI_BUFFER_CMD_EXTERNAL 1176 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { 1177 phw->instream_host_buffer_size[phm->obj_index] = 0; 1178 hw_message(pao, phm, phr); 1179 } 1180 1181 if (command == HPI_BUFFER_CMD_EXTERNAL 1182 || command == HPI_BUFFER_CMD_INTERNAL_FREE) 1183 hpios_locked_mem_free(&phw->instream_host_buffers 1184 [phm->obj_index]); 1185 1186 } else { 1187 /* Should HPI_ERROR_INVALID_OPERATION be returned 1188 if no host buffer is allocated? */ 1189 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1190 HPI_ISTREAM_HOSTBUFFER_FREE, 0); 1191 1192 } 1193 1194 } 1195 1196 static void instream_start(struct hpi_adapter_obj *pao, 1197 struct hpi_message *phm, struct hpi_response *phr) 1198 { 1199 hw_message(pao, phm, phr); 1200 } 1201 1202 static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status) 1203 { 1204 return status->dSP_index - status->host_index; 1205 } 1206 1207 static void instream_read(struct hpi_adapter_obj *pao, 1208 struct hpi_message *phm, struct hpi_response *phr) 1209 { 1210 struct hpi_hw_obj *phw = pao->priv; 1211 struct bus_master_interface *interface = phw->p_interface_buffer; 1212 struct hpi_hostbuffer_status *status; 1213 u32 data_available; 1214 u8 *p_bbm_data; 1215 u32 l_first_read; 1216 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; 1217 1218 if (!phw->instream_host_buffer_size[phm->obj_index]) { 1219 hw_message(pao, phm, phr); 1220 return; 1221 } 1222 hpi_init_response(phr, phm->object, phm->function, 0); 1223 1224 status = &interface->instream_host_buffer_status[phm->obj_index]; 1225 data_available = instream_get_bytes_available(status); 1226 if (data_available < phm->u.d.u.data.data_size) { 1227 phr->error = HPI_ERROR_INVALID_DATASIZE; 1228 return; 1229 } 1230 1231 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1232 obj_index])) { 1233 if (hpios_locked_mem_get_virt_addr(&phw-> 1234 instream_host_buffers[phm->obj_index], 1235 (void *)&p_bbm_data)) { 1236 phr->error = HPI_ERROR_INVALID_OPERATION; 1237 return; 1238 } 1239 1240 /* either all data, 1241 or enough to fit from current to end of BBM buffer */ 1242 l_first_read = 1243 min(phm->u.d.u.data.data_size, 1244 status->size_in_bytes - 1245 (status->host_index & (status->size_in_bytes - 1))); 1246 1247 memcpy(p_app_data, 1248 p_bbm_data + 1249 (status->host_index & (status->size_in_bytes - 1)), 1250 l_first_read); 1251 /* remaining data if any */ 1252 memcpy(p_app_data + l_first_read, p_bbm_data, 1253 phm->u.d.u.data.data_size - l_first_read); 1254 } 1255 status->host_index += phm->u.d.u.data.data_size; 1256 } 1257 1258 static void instream_get_info(struct hpi_adapter_obj *pao, 1259 struct hpi_message *phm, struct hpi_response *phr) 1260 { 1261 struct hpi_hw_obj *phw = pao->priv; 1262 struct bus_master_interface *interface = phw->p_interface_buffer; 1263 struct hpi_hostbuffer_status *status; 1264 if (!phw->instream_host_buffer_size[phm->obj_index]) { 1265 hw_message(pao, phm, phr); 1266 return; 1267 } 1268 1269 status = &interface->instream_host_buffer_status[phm->obj_index]; 1270 1271 hpi_init_response(phr, phm->object, phm->function, 0); 1272 1273 phr->u.d.u.stream_info.state = (u16)status->stream_state; 1274 phr->u.d.u.stream_info.samples_transferred = 1275 status->samples_processed; 1276 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; 1277 phr->u.d.u.stream_info.data_available = 1278 instream_get_bytes_available(status); 1279 phr->u.d.u.stream_info.auxiliary_data_available = 1280 status->auxiliary_data_available; 1281 } 1282 1283 /*****************************************************************************/ 1284 /* LOW-LEVEL */ 1285 #define HPI6205_MAX_FILES_TO_LOAD 2 1286 1287 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 1288 u32 *pos_error_code) 1289 { 1290 struct hpi_hw_obj *phw = pao->priv; 1291 struct dsp_code dsp_code; 1292 u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD]; 1293 u32 temp; 1294 int dsp = 0, i = 0; 1295 u16 err = 0; 1296 1297 boot_code_id[0] = HPI_ADAPTER_ASI(0x6205); 1298 1299 boot_code_id[1] = pao->pci.pci_dev->subsystem_device; 1300 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(boot_code_id[1]); 1301 1302 /* fix up cases where bootcode id[1] != subsys id */ 1303 switch (boot_code_id[1]) { 1304 case HPI_ADAPTER_FAMILY_ASI(0x5000): 1305 boot_code_id[0] = boot_code_id[1]; 1306 boot_code_id[1] = 0; 1307 break; 1308 case HPI_ADAPTER_FAMILY_ASI(0x5300): 1309 case HPI_ADAPTER_FAMILY_ASI(0x5400): 1310 case HPI_ADAPTER_FAMILY_ASI(0x6300): 1311 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400); 1312 break; 1313 case HPI_ADAPTER_FAMILY_ASI(0x5600): 1314 case HPI_ADAPTER_FAMILY_ASI(0x6500): 1315 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600); 1316 break; 1317 case HPI_ADAPTER_FAMILY_ASI(0x8800): 1318 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900); 1319 break; 1320 default: 1321 break; 1322 } 1323 1324 /* reset DSP by writing a 1 to the WARMRESET bit */ 1325 temp = C6205_HDCR_WARMRESET; 1326 iowrite32(temp, phw->prHDCR); 1327 hpios_delay_micro_seconds(1000); 1328 1329 /* check that PCI i/f was configured by EEPROM */ 1330 temp = ioread32(phw->prHSR); 1331 if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) != 1332 C6205_HSR_EEREAD) 1333 return HPI6205_ERROR_6205_EEPROM; 1334 temp |= 0x04; 1335 /* disable PINTA interrupt */ 1336 iowrite32(temp, phw->prHSR); 1337 1338 /* check control register reports PCI boot mode */ 1339 temp = ioread32(phw->prHDCR); 1340 if (!(temp & C6205_HDCR_PCIBOOT)) 1341 return HPI6205_ERROR_6205_REG; 1342 1343 /* try writing a few numbers to the DSP page register */ 1344 /* and reading them back. */ 1345 temp = 3; 1346 iowrite32(temp, phw->prDSPP); 1347 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1348 return HPI6205_ERROR_6205_DSPPAGE; 1349 temp = 2; 1350 iowrite32(temp, phw->prDSPP); 1351 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1352 return HPI6205_ERROR_6205_DSPPAGE; 1353 temp = 1; 1354 iowrite32(temp, phw->prDSPP); 1355 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1356 return HPI6205_ERROR_6205_DSPPAGE; 1357 /* reset DSP page to the correct number */ 1358 temp = 0; 1359 iowrite32(temp, phw->prDSPP); 1360 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1361 return HPI6205_ERROR_6205_DSPPAGE; 1362 phw->dsp_page = 0; 1363 1364 /* release 6713 from reset before 6205 is bootloaded. 1365 This ensures that the EMIF is inactive, 1366 and the 6713 HPI gets the correct bootmode etc 1367 */ 1368 if (boot_code_id[1] != 0) { 1369 /* DSP 1 is a C6713 */ 1370 /* CLKX0 <- '1' release the C6205 bootmode pulldowns */ 1371 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002202); 1372 hpios_delay_micro_seconds(100); 1373 /* Reset the 6713 #1 - revB */ 1374 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); 1375 1376 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1377 boot_loader_read_mem32(pao, 0, 0); 1378 1379 hpios_delay_micro_seconds(100); 1380 /* Release C6713 from reset - revB */ 1381 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4); 1382 hpios_delay_micro_seconds(100); 1383 } 1384 1385 for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) { 1386 /* is there a DSP to load? */ 1387 if (boot_code_id[dsp] == 0) 1388 continue; 1389 1390 err = boot_loader_config_emif(pao, dsp); 1391 if (err) 1392 return err; 1393 1394 err = boot_loader_test_internal_memory(pao, dsp); 1395 if (err) 1396 return err; 1397 1398 err = boot_loader_test_external_memory(pao, dsp); 1399 if (err) 1400 return err; 1401 1402 err = boot_loader_test_pld(pao, dsp); 1403 if (err) 1404 return err; 1405 1406 /* write the DSP code down into the DSPs memory */ 1407 dsp_code.ps_dev = pao->pci.pci_dev; 1408 err = hpi_dsp_code_open(boot_code_id[dsp], &dsp_code, 1409 pos_error_code); 1410 if (err) 1411 return err; 1412 1413 while (1) { 1414 u32 length; 1415 u32 address; 1416 u32 type; 1417 u32 *pcode; 1418 1419 err = hpi_dsp_code_read_word(&dsp_code, &length); 1420 if (err) 1421 break; 1422 if (length == 0xFFFFFFFF) 1423 break; /* end of code */ 1424 1425 err = hpi_dsp_code_read_word(&dsp_code, &address); 1426 if (err) 1427 break; 1428 err = hpi_dsp_code_read_word(&dsp_code, &type); 1429 if (err) 1430 break; 1431 err = hpi_dsp_code_read_block(length, &dsp_code, 1432 &pcode); 1433 if (err) 1434 break; 1435 for (i = 0; i < (int)length; i++) { 1436 boot_loader_write_mem32(pao, dsp, address, 1437 *pcode); 1438 /* dummy read every 4 words */ 1439 /* for 6205 advisory 1.4.4 */ 1440 if (i % 4 == 0) 1441 boot_loader_read_mem32(pao, dsp, 1442 address); 1443 pcode++; 1444 address += 4; 1445 } 1446 1447 } 1448 if (err) { 1449 hpi_dsp_code_close(&dsp_code); 1450 return err; 1451 } 1452 1453 /* verify code */ 1454 hpi_dsp_code_rewind(&dsp_code); 1455 while (1) { 1456 u32 length = 0; 1457 u32 address = 0; 1458 u32 type = 0; 1459 u32 *pcode = NULL; 1460 u32 data = 0; 1461 1462 hpi_dsp_code_read_word(&dsp_code, &length); 1463 if (length == 0xFFFFFFFF) 1464 break; /* end of code */ 1465 1466 hpi_dsp_code_read_word(&dsp_code, &address); 1467 hpi_dsp_code_read_word(&dsp_code, &type); 1468 hpi_dsp_code_read_block(length, &dsp_code, &pcode); 1469 1470 for (i = 0; i < (int)length; i++) { 1471 data = boot_loader_read_mem32(pao, dsp, 1472 address); 1473 if (data != *pcode) { 1474 err = 0; 1475 break; 1476 } 1477 pcode++; 1478 address += 4; 1479 } 1480 if (err) 1481 break; 1482 } 1483 hpi_dsp_code_close(&dsp_code); 1484 if (err) 1485 return err; 1486 } 1487 1488 /* After bootloading all DSPs, start DSP0 running 1489 * The DSP0 code will handle starting and synchronizing with its slaves 1490 */ 1491 if (phw->p_interface_buffer) { 1492 /* we need to tell the card the physical PCI address */ 1493 u32 physicalPC_iaddress; 1494 struct bus_master_interface *interface = 1495 phw->p_interface_buffer; 1496 u32 host_mailbox_address_on_dsp; 1497 u32 physicalPC_iaddress_verify = 0; 1498 int time_out = 10; 1499 /* set ack so we know when DSP is ready to go */ 1500 /* (dwDspAck will be changed to HIF_RESET) */ 1501 interface->dsp_ack = H620_HIF_UNKNOWN; 1502 wmb(); /* ensure ack is written before dsp writes back */ 1503 1504 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem, 1505 &physicalPC_iaddress); 1506 1507 /* locate the host mailbox on the DSP. */ 1508 host_mailbox_address_on_dsp = 0x80000000; 1509 while ((physicalPC_iaddress != physicalPC_iaddress_verify) 1510 && time_out--) { 1511 boot_loader_write_mem32(pao, 0, 1512 host_mailbox_address_on_dsp, 1513 physicalPC_iaddress); 1514 physicalPC_iaddress_verify = 1515 boot_loader_read_mem32(pao, 0, 1516 host_mailbox_address_on_dsp); 1517 } 1518 } 1519 HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n"); 1520 /* enable interrupts */ 1521 temp = ioread32(phw->prHSR); 1522 temp &= ~(u32)C6205_HSR_INTAM; 1523 iowrite32(temp, phw->prHSR); 1524 1525 /* start code running... */ 1526 temp = ioread32(phw->prHDCR); 1527 temp |= (u32)C6205_HDCR_DSPINT; 1528 iowrite32(temp, phw->prHDCR); 1529 1530 /* give the DSP 10ms to start up */ 1531 hpios_delay_micro_seconds(10000); 1532 return err; 1533 1534 } 1535 1536 /*****************************************************************************/ 1537 /* Bootloader utility functions */ 1538 1539 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, 1540 u32 address) 1541 { 1542 struct hpi_hw_obj *phw = pao->priv; 1543 u32 data = 0; 1544 __iomem u32 *p_data; 1545 1546 if (dsp_index == 0) { 1547 /* DSP 0 is always C6205 */ 1548 if ((address >= 0x01800000) & (address < 0x02000000)) { 1549 /* BAR1 register access */ 1550 p_data = pao->pci.ap_mem_base[1] + 1551 (address & 0x007fffff) / 1552 sizeof(*pao->pci.ap_mem_base[1]); 1553 /* HPI_DEBUG_LOG(WARNING, 1554 "BAR1 access %08x\n", dwAddress); */ 1555 } else { 1556 u32 dw4M_page = address >> 22L; 1557 if (dw4M_page != phw->dsp_page) { 1558 phw->dsp_page = dw4M_page; 1559 /* *INDENT OFF* */ 1560 iowrite32(phw->dsp_page, phw->prDSPP); 1561 /* *INDENT-ON* */ 1562 } 1563 address &= 0x3fffff; /* address within 4M page */ 1564 /* BAR0 memory access */ 1565 p_data = pao->pci.ap_mem_base[0] + 1566 address / sizeof(u32); 1567 } 1568 data = ioread32(p_data); 1569 } else if (dsp_index == 1) { 1570 /* DSP 1 is a C6713 */ 1571 u32 lsb; 1572 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); 1573 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); 1574 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR); 1575 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR); 1576 data = (data << 16) | (lsb & 0xFFFF); 1577 } 1578 return data; 1579 } 1580 1581 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, 1582 int dsp_index, u32 address, u32 data) 1583 { 1584 struct hpi_hw_obj *phw = pao->priv; 1585 __iomem u32 *p_data; 1586 /* u32 dwVerifyData=0; */ 1587 1588 if (dsp_index == 0) { 1589 /* DSP 0 is always C6205 */ 1590 if ((address >= 0x01800000) & (address < 0x02000000)) { 1591 /* BAR1 - DSP register access using */ 1592 /* Non-prefetchable PCI access */ 1593 p_data = pao->pci.ap_mem_base[1] + 1594 (address & 0x007fffff) / 1595 sizeof(*pao->pci.ap_mem_base[1]); 1596 } else { 1597 /* BAR0 access - all of DSP memory using */ 1598 /* pre-fetchable PCI access */ 1599 u32 dw4M_page = address >> 22L; 1600 if (dw4M_page != phw->dsp_page) { 1601 phw->dsp_page = dw4M_page; 1602 /* *INDENT-OFF* */ 1603 iowrite32(phw->dsp_page, phw->prDSPP); 1604 /* *INDENT-ON* */ 1605 } 1606 address &= 0x3fffff; /* address within 4M page */ 1607 p_data = pao->pci.ap_mem_base[0] + 1608 address / sizeof(u32); 1609 } 1610 iowrite32(data, p_data); 1611 } else if (dsp_index == 1) { 1612 /* DSP 1 is a C6713 */ 1613 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); 1614 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); 1615 1616 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1617 boot_loader_read_mem32(pao, 0, 0); 1618 1619 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data); 1620 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16); 1621 1622 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1623 boot_loader_read_mem32(pao, 0, 0); 1624 } 1625 } 1626 1627 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index) 1628 { 1629 if (dsp_index == 0) { 1630 u32 setting; 1631 1632 /* DSP 0 is always C6205 */ 1633 1634 /* Set the EMIF */ 1635 /* memory map of C6205 */ 1636 /* 00000000-0000FFFF 16Kx32 internal program */ 1637 /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */ 1638 1639 /* EMIF config */ 1640 /*------------ */ 1641 /* Global EMIF control */ 1642 boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779); 1643 #define WS_OFS 28 1644 #define WST_OFS 22 1645 #define WH_OFS 20 1646 #define RS_OFS 16 1647 #define RST_OFS 8 1648 #define MTYPE_OFS 4 1649 #define RH_OFS 0 1650 1651 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */ 1652 setting = 0x00000030; 1653 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting); 1654 if (setting != boot_loader_read_mem32(pao, dsp_index, 1655 0x01800008)) 1656 return HPI6205_ERROR_DSP_EMIF; 1657 1658 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */ 1659 /* which occupies D15..0. 6713 starts at 27MHz, so need */ 1660 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */ 1661 /* WST should be 71, but 63 is max possible */ 1662 setting = 1663 (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) | 1664 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | 1665 (2L << MTYPE_OFS); 1666 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting); 1667 if (setting != boot_loader_read_mem32(pao, dsp_index, 1668 0x01800004)) 1669 return HPI6205_ERROR_DSP_EMIF; 1670 1671 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */ 1672 /* which occupies D15..0. 6713 starts at 27MHz, so need */ 1673 /* plenty of wait states */ 1674 setting = 1675 (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) | 1676 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | 1677 (2L << MTYPE_OFS); 1678 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting); 1679 if (setting != boot_loader_read_mem32(pao, dsp_index, 1680 0x01800010)) 1681 return HPI6205_ERROR_DSP_EMIF; 1682 1683 /* EMIF CE3 setup - 32 bit async. */ 1684 /* This is the PLD on the ASI5000 cards only */ 1685 setting = 1686 (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) | 1687 (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) | 1688 (2L << MTYPE_OFS); 1689 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting); 1690 if (setting != boot_loader_read_mem32(pao, dsp_index, 1691 0x01800014)) 1692 return HPI6205_ERROR_DSP_EMIF; 1693 1694 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */ 1695 /* need to use this else DSP code crashes? */ 1696 boot_loader_write_mem32(pao, dsp_index, 0x01800018, 1697 0x07117000); 1698 1699 /* EMIF SDRAM Refresh Timing */ 1700 /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */ 1701 boot_loader_write_mem32(pao, dsp_index, 0x0180001C, 1702 0x00000410); 1703 1704 } else if (dsp_index == 1) { 1705 /* test access to the C6713s HPI registers */ 1706 u32 write_data = 0, read_data = 0, i = 0; 1707 1708 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */ 1709 write_data = 1; 1710 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data); 1711 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data); 1712 /* C67 HPI is on lower 16bits of 32bit EMIF */ 1713 read_data = 1714 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR); 1715 if (write_data != read_data) { 1716 HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data, 1717 read_data); 1718 return HPI6205_ERROR_C6713_HPIC; 1719 } 1720 /* HPIA - walking ones test */ 1721 write_data = 1; 1722 for (i = 0; i < 32; i++) { 1723 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, 1724 write_data); 1725 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, 1726 (write_data >> 16)); 1727 read_data = 1728 0xFFFF & boot_loader_read_mem32(pao, 0, 1729 HPIAL_ADDR); 1730 read_data = 1731 read_data | ((0xFFFF & 1732 boot_loader_read_mem32(pao, 0, 1733 HPIAH_ADDR)) 1734 << 16); 1735 if (read_data != write_data) { 1736 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n", 1737 write_data, read_data); 1738 return HPI6205_ERROR_C6713_HPIA; 1739 } 1740 write_data = write_data << 1; 1741 } 1742 1743 /* setup C67x PLL 1744 * ** C6713 datasheet says we cannot program PLL from HPI, 1745 * and indeed if we try to set the PLL multiply from the HPI, 1746 * the PLL does not seem to lock, so we enable the PLL and 1747 * use the default multiply of x 7, which for a 27MHz clock 1748 * gives a DSP speed of 189MHz 1749 */ 1750 /* bypass PLL */ 1751 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000); 1752 hpios_delay_micro_seconds(1000); 1753 /* EMIF = 189/3=63MHz */ 1754 boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002); 1755 /* peri = 189/2 */ 1756 boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001); 1757 /* cpu = 189/1 */ 1758 boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000); 1759 hpios_delay_micro_seconds(1000); 1760 /* ** SGT test to take GPO3 high when we start the PLL */ 1761 /* and low when the delay is completed */ 1762 /* FSX0 <- '1' (GPO3) */ 1763 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A); 1764 /* PLL not bypassed */ 1765 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001); 1766 hpios_delay_micro_seconds(1000); 1767 /* FSX0 <- '0' (GPO3) */ 1768 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02); 1769 1770 /* 6205 EMIF CE1 resetup - 32 bit async. */ 1771 /* Now 6713 #1 is running at 189MHz can reduce waitstates */ 1772 boot_loader_write_mem32(pao, 0, 0x01800004, /* CE1 */ 1773 (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) | 1774 (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) | 1775 (2L << MTYPE_OFS)); 1776 1777 hpios_delay_micro_seconds(1000); 1778 1779 /* check that we can read one of the PLL registers */ 1780 /* PLL should not be bypassed! */ 1781 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF) 1782 != 0x0001) { 1783 return HPI6205_ERROR_C6713_PLL; 1784 } 1785 /* setup C67x EMIF (note this is the only use of 1786 BAR1 via BootLoader_WriteMem32) */ 1787 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL, 1788 0x000034A8); 1789 1790 /* EMIF CE0 setup - 2Mx32 Sync DRAM 1791 31..28 Wr setup 1792 27..22 Wr strobe 1793 21..20 Wr hold 1794 19..16 Rd setup 1795 15..14 - 1796 13..8 Rd strobe 1797 7..4 MTYPE 0011 Sync DRAM 32bits 1798 3 Wr hold MSB 1799 2..0 Rd hold 1800 */ 1801 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0, 1802 0x00000030); 1803 1804 /* EMIF SDRAM Extension 1805 0x00 1806 31-21 0000b 0000b 000b 1807 20 WR2RD = 2cycles-1 = 1b 1808 1809 19-18 WR2DEAC = 3cycle-1 = 10b 1810 17 WR2WR = 2cycle-1 = 1b 1811 16-15 R2WDQM = 4cycle-1 = 11b 1812 14-12 RD2WR = 6cycles-1 = 101b 1813 1814 11-10 RD2DEAC = 4cycle-1 = 11b 1815 9 RD2RD = 2cycle-1 = 1b 1816 8-7 THZP = 3cycle-1 = 10b 1817 6-5 TWR = 2cycle-1 = 01b (tWR = 17ns) 1818 4 TRRD = 2cycle = 0b (tRRD = 14ns) 1819 3-1 TRAS = 5cycle-1 = 100b (Tras=42ns) 1820 1 CAS latency = 3cyc = 1b 1821 (for Micron 2M32-7 operating at 100MHz) 1822 */ 1823 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT, 1824 0x001BDF29); 1825 1826 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank) 1827 31 - 0b - 1828 30 SDBSZ 1b 4 bank 1829 29..28 SDRSZ 00b 11 row address pins 1830 1831 27..26 SDCSZ 01b 8 column address pins 1832 25 RFEN 1b refersh enabled 1833 24 INIT 1b init SDRAM! 1834 1835 23..20 TRCD 0001b (Trcd/Tcyc)-1 = (20/10)-1 = 1 1836 1837 19..16 TRP 0001b (Trp/Tcyc)-1 = (20/10)-1 = 1 1838 1839 15..12 TRC 0110b (Trc/Tcyc)-1 = (70/10)-1 = 6 1840 1841 11..0 - 0000b 0000b 0000b 1842 */ 1843 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL, 1844 0x47116000); 1845 1846 /* SDRAM refresh timing 1847 Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A 1848 */ 1849 boot_loader_write_mem32(pao, dsp_index, 1850 C6713_EMIF_SDRAMTIMING, 0x00000410); 1851 1852 hpios_delay_micro_seconds(1000); 1853 } else if (dsp_index == 2) { 1854 /* DSP 2 is a C6713 */ 1855 } 1856 1857 return 0; 1858 } 1859 1860 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, 1861 u32 start_address, u32 length) 1862 { 1863 u32 i = 0, j = 0; 1864 u32 test_addr = 0; 1865 u32 test_data = 0, data = 0; 1866 1867 length = 1000; 1868 1869 /* for 1st word, test each bit in the 32bit word, */ 1870 /* dwLength specifies number of 32bit words to test */ 1871 /*for(i=0; i<dwLength; i++) */ 1872 i = 0; 1873 { 1874 test_addr = start_address + i * 4; 1875 test_data = 0x00000001; 1876 for (j = 0; j < 32; j++) { 1877 boot_loader_write_mem32(pao, dsp_index, test_addr, 1878 test_data); 1879 data = boot_loader_read_mem32(pao, dsp_index, 1880 test_addr); 1881 if (data != test_data) { 1882 HPI_DEBUG_LOG(VERBOSE, 1883 "Memtest error details " 1884 "%08x %08x %08x %i\n", test_addr, 1885 test_data, data, dsp_index); 1886 return 1; /* error */ 1887 } 1888 test_data = test_data << 1; 1889 } /* for(j) */ 1890 } /* for(i) */ 1891 1892 /* for the next 100 locations test each location, leaving it as zero */ 1893 /* write a zero to the next word in memory before we read */ 1894 /* the previous write to make sure every memory location is unique */ 1895 for (i = 0; i < 100; i++) { 1896 test_addr = start_address + i * 4; 1897 test_data = 0xA5A55A5A; 1898 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data); 1899 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0); 1900 data = boot_loader_read_mem32(pao, dsp_index, test_addr); 1901 if (data != test_data) { 1902 HPI_DEBUG_LOG(VERBOSE, 1903 "Memtest error details " 1904 "%08x %08x %08x %i\n", test_addr, test_data, 1905 data, dsp_index); 1906 return 1; /* error */ 1907 } 1908 /* leave location as zero */ 1909 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); 1910 } 1911 1912 /* zero out entire memory block */ 1913 for (i = 0; i < length; i++) { 1914 test_addr = start_address + i * 4; 1915 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); 1916 } 1917 return 0; 1918 } 1919 1920 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, 1921 int dsp_index) 1922 { 1923 int err = 0; 1924 if (dsp_index == 0) { 1925 /* DSP 0 is a C6205 */ 1926 /* 64K prog mem */ 1927 err = boot_loader_test_memory(pao, dsp_index, 0x00000000, 1928 0x10000); 1929 if (!err) 1930 /* 64K data mem */ 1931 err = boot_loader_test_memory(pao, dsp_index, 1932 0x80000000, 0x10000); 1933 } else if (dsp_index == 1) { 1934 /* DSP 1 is a C6713 */ 1935 /* 192K internal mem */ 1936 err = boot_loader_test_memory(pao, dsp_index, 0x00000000, 1937 0x30000); 1938 if (!err) 1939 /* 64K internal mem / L2 cache */ 1940 err = boot_loader_test_memory(pao, dsp_index, 1941 0x00030000, 0x10000); 1942 } 1943 1944 if (err) 1945 return HPI6205_ERROR_DSP_INTMEM; 1946 else 1947 return 0; 1948 } 1949 1950 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, 1951 int dsp_index) 1952 { 1953 u32 dRAM_start_address = 0; 1954 u32 dRAM_size = 0; 1955 1956 if (dsp_index == 0) { 1957 /* only test for SDRAM if an ASI5000 card */ 1958 if (pao->pci.pci_dev->subsystem_device == 0x5000) { 1959 /* DSP 0 is always C6205 */ 1960 dRAM_start_address = 0x00400000; 1961 dRAM_size = 0x200000; 1962 /*dwDRAMinc=1024; */ 1963 } else 1964 return 0; 1965 } else if (dsp_index == 1) { 1966 /* DSP 1 is a C6713 */ 1967 dRAM_start_address = 0x80000000; 1968 dRAM_size = 0x200000; 1969 /*dwDRAMinc=1024; */ 1970 } 1971 1972 if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address, 1973 dRAM_size)) 1974 return HPI6205_ERROR_DSP_EXTMEM; 1975 return 0; 1976 } 1977 1978 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index) 1979 { 1980 u32 data = 0; 1981 if (dsp_index == 0) { 1982 /* only test for DSP0 PLD on ASI5000 card */ 1983 if (pao->pci.pci_dev->subsystem_device == 0x5000) { 1984 /* PLD is located at CE3=0x03000000 */ 1985 data = boot_loader_read_mem32(pao, dsp_index, 1986 0x03000008); 1987 if ((data & 0xF) != 0x5) 1988 return HPI6205_ERROR_DSP_PLD; 1989 data = boot_loader_read_mem32(pao, dsp_index, 1990 0x0300000C); 1991 if ((data & 0xF) != 0xA) 1992 return HPI6205_ERROR_DSP_PLD; 1993 } 1994 } else if (dsp_index == 1) { 1995 /* DSP 1 is a C6713 */ 1996 if (pao->pci.pci_dev->subsystem_device == 0x8700) { 1997 /* PLD is located at CE1=0x90000000 */ 1998 data = boot_loader_read_mem32(pao, dsp_index, 1999 0x90000010); 2000 if ((data & 0xFF) != 0xAA) 2001 return HPI6205_ERROR_DSP_PLD; 2002 /* 8713 - LED on */ 2003 boot_loader_write_mem32(pao, dsp_index, 0x90000000, 2004 0x02); 2005 } 2006 } 2007 return 0; 2008 } 2009 2010 /** Transfer data to or from DSP 2011 nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA 2012 */ 2013 static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data, 2014 u32 data_size, int operation) 2015 { 2016 struct hpi_hw_obj *phw = pao->priv; 2017 u32 data_transferred = 0; 2018 u16 err = 0; 2019 u32 temp2; 2020 struct bus_master_interface *interface = phw->p_interface_buffer; 2021 2022 if (!p_data) 2023 return HPI_ERROR_INVALID_DATA_POINTER; 2024 2025 data_size &= ~3L; /* round data_size down to nearest 4 bytes */ 2026 2027 /* make sure state is IDLE */ 2028 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) 2029 return HPI_ERROR_DSP_HARDWARE; 2030 2031 while (data_transferred < data_size) { 2032 u32 this_copy = data_size - data_transferred; 2033 2034 if (this_copy > HPI6205_SIZEOF_DATA) 2035 this_copy = HPI6205_SIZEOF_DATA; 2036 2037 if (operation == H620_HIF_SEND_DATA) 2038 memcpy((void *)&interface->u.b_data[0], 2039 &p_data[data_transferred], this_copy); 2040 2041 interface->transfer_size_in_bytes = this_copy; 2042 2043 /* DSP must change this back to nOperation */ 2044 interface->dsp_ack = H620_HIF_IDLE; 2045 send_dsp_command(phw, operation); 2046 2047 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT); 2048 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n", 2049 HPI6205_TIMEOUT - temp2, this_copy); 2050 2051 if (!temp2) { 2052 /* timed out */ 2053 HPI_DEBUG_LOG(ERROR, 2054 "Timed out waiting for " "state %d got %d\n", 2055 operation, interface->dsp_ack); 2056 2057 break; 2058 } 2059 if (operation == H620_HIF_GET_DATA) 2060 memcpy(&p_data[data_transferred], 2061 (void *)&interface->u.b_data[0], this_copy); 2062 2063 data_transferred += this_copy; 2064 } 2065 if (interface->dsp_ack != operation) 2066 HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n", 2067 interface->dsp_ack, operation); 2068 /* err=HPI_ERROR_DSP_HARDWARE; */ 2069 2070 send_dsp_command(phw, H620_HIF_IDLE); 2071 2072 return err; 2073 } 2074 2075 /* wait for up to timeout_us microseconds for the DSP 2076 to signal state by DMA into dwDspAck 2077 */ 2078 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us) 2079 { 2080 struct bus_master_interface *interface = phw->p_interface_buffer; 2081 int t = timeout_us / 4; 2082 2083 rmb(); /* ensure interface->dsp_ack is up to date */ 2084 while ((interface->dsp_ack != state) && --t) { 2085 hpios_delay_micro_seconds(4); 2086 rmb(); /* DSP changes dsp_ack by DMA */ 2087 } 2088 2089 /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */ 2090 return t * 4; 2091 } 2092 2093 /* set the busmaster interface to cmd, then interrupt the DSP */ 2094 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd) 2095 { 2096 struct bus_master_interface *interface = phw->p_interface_buffer; 2097 2098 u32 r; 2099 2100 interface->host_cmd = cmd; 2101 wmb(); /* DSP gets state by DMA, make sure it is written to memory */ 2102 /* before we interrupt the DSP */ 2103 r = ioread32(phw->prHDCR); 2104 r |= (u32)C6205_HDCR_DSPINT; 2105 iowrite32(r, phw->prHDCR); 2106 r &= ~(u32)C6205_HDCR_DSPINT; 2107 iowrite32(r, phw->prHDCR); 2108 } 2109 2110 static unsigned int message_count; 2111 2112 static u16 message_response_sequence(struct hpi_adapter_obj *pao, 2113 struct hpi_message *phm, struct hpi_response *phr) 2114 { 2115 u32 time_out, time_out2; 2116 struct hpi_hw_obj *phw = pao->priv; 2117 struct bus_master_interface *interface = phw->p_interface_buffer; 2118 u16 err = 0; 2119 2120 message_count++; 2121 if (phm->size > sizeof(interface->u)) { 2122 phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL; 2123 phr->specific_error = sizeof(interface->u); 2124 phr->size = sizeof(struct hpi_response_header); 2125 HPI_DEBUG_LOG(ERROR, 2126 "message len %d too big for buffer %ld \n", phm->size, 2127 sizeof(interface->u)); 2128 return 0; 2129 } 2130 2131 /* Assume buffer of type struct bus_master_interface 2132 is allocated "noncacheable" */ 2133 2134 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { 2135 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n"); 2136 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; 2137 } 2138 2139 memcpy(&interface->u.message_buffer, phm, phm->size); 2140 /* signal we want a response */ 2141 send_dsp_command(phw, H620_HIF_GET_RESP); 2142 2143 time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT); 2144 2145 if (!time_out2) { 2146 HPI_DEBUG_LOG(ERROR, 2147 "(%u) Timed out waiting for " "GET_RESP state [%x]\n", 2148 message_count, interface->dsp_ack); 2149 } else { 2150 HPI_DEBUG_LOG(VERBOSE, 2151 "(%u) transition to GET_RESP after %u\n", 2152 message_count, HPI6205_TIMEOUT - time_out2); 2153 } 2154 /* spin waiting on HIF interrupt flag (end of msg process) */ 2155 time_out = HPI6205_TIMEOUT; 2156 2157 /* read the result */ 2158 if (time_out) { 2159 if (interface->u.response_buffer.size <= phr->size) 2160 memcpy(phr, &interface->u.response_buffer, 2161 interface->u.response_buffer.size); 2162 else { 2163 HPI_DEBUG_LOG(ERROR, 2164 "response len %d too big for buffer %d\n", 2165 interface->u.response_buffer.size, phr->size); 2166 memcpy(phr, &interface->u.response_buffer, 2167 sizeof(struct hpi_response_header)); 2168 phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; 2169 phr->specific_error = 2170 interface->u.response_buffer.size; 2171 phr->size = sizeof(struct hpi_response_header); 2172 } 2173 } 2174 /* set interface back to idle */ 2175 send_dsp_command(phw, H620_HIF_IDLE); 2176 2177 if (!time_out || !time_out2) { 2178 HPI_DEBUG_LOG(DEBUG, "something timed out!\n"); 2179 return HPI6205_ERROR_MSG_RESP_TIMEOUT; 2180 } 2181 /* special case for adapter close - */ 2182 /* wait for the DSP to indicate it is idle */ 2183 if (phm->function == HPI_ADAPTER_CLOSE) { 2184 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { 2185 HPI_DEBUG_LOG(DEBUG, 2186 "Timeout waiting for idle " 2187 "(on adapter_close)\n"); 2188 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; 2189 } 2190 } 2191 err = hpi_validate_response(phm, phr); 2192 return err; 2193 } 2194 2195 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 2196 struct hpi_response *phr) 2197 { 2198 2199 u16 err = 0; 2200 2201 hpios_dsplock_lock(pao); 2202 2203 err = message_response_sequence(pao, phm, phr); 2204 2205 /* maybe an error response */ 2206 if (err) { 2207 /* something failed in the HPI/DSP interface */ 2208 if (err >= HPI_ERROR_BACKEND_BASE) { 2209 phr->error = HPI_ERROR_DSP_COMMUNICATION; 2210 phr->specific_error = err; 2211 } else { 2212 phr->error = err; 2213 } 2214 2215 pao->dsp_crashed++; 2216 2217 /* just the header of the response is valid */ 2218 phr->size = sizeof(struct hpi_response_header); 2219 goto err; 2220 } else 2221 pao->dsp_crashed = 0; 2222 2223 if (phr->error != 0) /* something failed in the DSP */ 2224 goto err; 2225 2226 switch (phm->function) { 2227 case HPI_OSTREAM_WRITE: 2228 case HPI_ISTREAM_ANC_WRITE: 2229 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, 2230 phm->u.d.u.data.data_size, H620_HIF_SEND_DATA); 2231 break; 2232 2233 case HPI_ISTREAM_READ: 2234 case HPI_OSTREAM_ANC_READ: 2235 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, 2236 phm->u.d.u.data.data_size, H620_HIF_GET_DATA); 2237 break; 2238 2239 case HPI_CONTROL_SET_STATE: 2240 if (phm->object == HPI_OBJ_CONTROLEX 2241 && phm->u.cx.attribute == HPI_COBRANET_SET_DATA) 2242 err = hpi6205_transfer_data(pao, 2243 phm->u.cx.u.cobranet_bigdata.pb_data, 2244 phm->u.cx.u.cobranet_bigdata.byte_count, 2245 H620_HIF_SEND_DATA); 2246 break; 2247 2248 case HPI_CONTROL_GET_STATE: 2249 if (phm->object == HPI_OBJ_CONTROLEX 2250 && phm->u.cx.attribute == HPI_COBRANET_GET_DATA) 2251 err = hpi6205_transfer_data(pao, 2252 phm->u.cx.u.cobranet_bigdata.pb_data, 2253 phr->u.cx.u.cobranet_data.byte_count, 2254 H620_HIF_GET_DATA); 2255 break; 2256 } 2257 phr->error = err; 2258 2259 err: 2260 hpios_dsplock_unlock(pao); 2261 2262 return; 2263 } 2264