1*74ba9207SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2f6c63835SKrzysztof Helt /********************************************************************* 3f6c63835SKrzysztof Helt * 4f6c63835SKrzysztof Helt * msnd.h 5f6c63835SKrzysztof Helt * 6f6c63835SKrzysztof Helt * Turtle Beach MultiSound Sound Card Driver for Linux 7f6c63835SKrzysztof Helt * 8f6c63835SKrzysztof Helt * Some parts of this header file were derived from the Turtle Beach 9f6c63835SKrzysztof Helt * MultiSound Driver Development Kit. 10f6c63835SKrzysztof Helt * 11f6c63835SKrzysztof Helt * Copyright (C) 1998 Andrew Veliath 12f6c63835SKrzysztof Helt * Copyright (C) 1993 Turtle Beach Systems, Inc. 13f6c63835SKrzysztof Helt * 14f6c63835SKrzysztof Helt ********************************************************************/ 15f6c63835SKrzysztof Helt #ifndef __MSND_H 16f6c63835SKrzysztof Helt #define __MSND_H 17f6c63835SKrzysztof Helt 18f6c63835SKrzysztof Helt #define DEFSAMPLERATE 44100 19f6c63835SKrzysztof Helt #define DEFSAMPLESIZE SNDRV_PCM_FORMAT_S16 20f6c63835SKrzysztof Helt #define DEFCHANNELS 1 21f6c63835SKrzysztof Helt 22f6c63835SKrzysztof Helt #define SRAM_BANK_SIZE 0x8000 23f6c63835SKrzysztof Helt #define SRAM_CNTL_START 0x7F00 24f6c63835SKrzysztof Helt #define SMA_STRUCT_START 0x7F40 25f6c63835SKrzysztof Helt 26f6c63835SKrzysztof Helt #define DSP_BASE_ADDR 0x4000 27f6c63835SKrzysztof Helt #define DSP_BANK_BASE 0x4000 28f6c63835SKrzysztof Helt 29f6c63835SKrzysztof Helt #define AGND 0x01 30f6c63835SKrzysztof Helt #define SIGNAL 0x02 31f6c63835SKrzysztof Helt 32f6c63835SKrzysztof Helt #define EXT_DSP_BIT_DCAL 0x0001 33f6c63835SKrzysztof Helt #define EXT_DSP_BIT_MIDI_CON 0x0002 34f6c63835SKrzysztof Helt 35f6c63835SKrzysztof Helt #define BUFFSIZE 0x8000 36f6c63835SKrzysztof Helt #define HOSTQ_SIZE 0x40 37f6c63835SKrzysztof Helt 38f6c63835SKrzysztof Helt #define DAP_BUFF_SIZE 0x2400 39f6c63835SKrzysztof Helt 40f6c63835SKrzysztof Helt #define DAPQ_STRUCT_SIZE 0x10 41f6c63835SKrzysztof Helt #define DARQ_STRUCT_SIZE 0x10 42f6c63835SKrzysztof Helt #define DAPQ_BUFF_SIZE (3 * 0x10) 43f6c63835SKrzysztof Helt #define DARQ_BUFF_SIZE (3 * 0x10) 44f6c63835SKrzysztof Helt #define MODQ_BUFF_SIZE 0x400 45f6c63835SKrzysztof Helt 46f6c63835SKrzysztof Helt #define DAPQ_DATA_BUFF 0x6C00 47f6c63835SKrzysztof Helt #define DARQ_DATA_BUFF 0x6C30 48f6c63835SKrzysztof Helt #define MODQ_DATA_BUFF 0x6C60 49f6c63835SKrzysztof Helt #define MIDQ_DATA_BUFF 0x7060 50f6c63835SKrzysztof Helt 51f6c63835SKrzysztof Helt #define DAPQ_OFFSET SRAM_CNTL_START 52f6c63835SKrzysztof Helt #define DARQ_OFFSET (SRAM_CNTL_START + 0x08) 53f6c63835SKrzysztof Helt #define MODQ_OFFSET (SRAM_CNTL_START + 0x10) 54f6c63835SKrzysztof Helt #define MIDQ_OFFSET (SRAM_CNTL_START + 0x18) 55f6c63835SKrzysztof Helt #define DSPQ_OFFSET (SRAM_CNTL_START + 0x20) 56f6c63835SKrzysztof Helt 57f6c63835SKrzysztof Helt #define HP_ICR 0x00 58f6c63835SKrzysztof Helt #define HP_CVR 0x01 59f6c63835SKrzysztof Helt #define HP_ISR 0x02 60f6c63835SKrzysztof Helt #define HP_IVR 0x03 61f6c63835SKrzysztof Helt #define HP_NU 0x04 62f6c63835SKrzysztof Helt #define HP_INFO 0x04 63f6c63835SKrzysztof Helt #define HP_TXH 0x05 64f6c63835SKrzysztof Helt #define HP_RXH 0x05 65f6c63835SKrzysztof Helt #define HP_TXM 0x06 66f6c63835SKrzysztof Helt #define HP_RXM 0x06 67f6c63835SKrzysztof Helt #define HP_TXL 0x07 68f6c63835SKrzysztof Helt #define HP_RXL 0x07 69f6c63835SKrzysztof Helt 70f6c63835SKrzysztof Helt #define HP_ICR_DEF 0x00 71f6c63835SKrzysztof Helt #define HP_CVR_DEF 0x12 72f6c63835SKrzysztof Helt #define HP_ISR_DEF 0x06 73f6c63835SKrzysztof Helt #define HP_IVR_DEF 0x0f 74f6c63835SKrzysztof Helt #define HP_NU_DEF 0x00 75f6c63835SKrzysztof Helt 76f6c63835SKrzysztof Helt #define HP_IRQM 0x09 77f6c63835SKrzysztof Helt 78f6c63835SKrzysztof Helt #define HPR_BLRC 0x08 79f6c63835SKrzysztof Helt #define HPR_SPR1 0x09 80f6c63835SKrzysztof Helt #define HPR_SPR2 0x0A 81f6c63835SKrzysztof Helt #define HPR_TCL0 0x0B 82f6c63835SKrzysztof Helt #define HPR_TCL1 0x0C 83f6c63835SKrzysztof Helt #define HPR_TCL2 0x0D 84f6c63835SKrzysztof Helt #define HPR_TCL3 0x0E 85f6c63835SKrzysztof Helt #define HPR_TCL4 0x0F 86f6c63835SKrzysztof Helt 87f6c63835SKrzysztof Helt #define HPICR_INIT 0x80 88f6c63835SKrzysztof Helt #define HPICR_HM1 0x40 89f6c63835SKrzysztof Helt #define HPICR_HM0 0x20 90f6c63835SKrzysztof Helt #define HPICR_HF1 0x10 91f6c63835SKrzysztof Helt #define HPICR_HF0 0x08 92f6c63835SKrzysztof Helt #define HPICR_TREQ 0x02 93f6c63835SKrzysztof Helt #define HPICR_RREQ 0x01 94f6c63835SKrzysztof Helt 95f6c63835SKrzysztof Helt #define HPCVR_HC 0x80 96f6c63835SKrzysztof Helt 97f6c63835SKrzysztof Helt #define HPISR_HREQ 0x80 98f6c63835SKrzysztof Helt #define HPISR_DMA 0x40 99f6c63835SKrzysztof Helt #define HPISR_HF3 0x10 100f6c63835SKrzysztof Helt #define HPISR_HF2 0x08 101f6c63835SKrzysztof Helt #define HPISR_TRDY 0x04 102f6c63835SKrzysztof Helt #define HPISR_TXDE 0x02 103f6c63835SKrzysztof Helt #define HPISR_RXDF 0x01 104f6c63835SKrzysztof Helt 105f6c63835SKrzysztof Helt #define HPIO_290 0 106f6c63835SKrzysztof Helt #define HPIO_260 1 107f6c63835SKrzysztof Helt #define HPIO_250 2 108f6c63835SKrzysztof Helt #define HPIO_240 3 109f6c63835SKrzysztof Helt #define HPIO_230 4 110f6c63835SKrzysztof Helt #define HPIO_220 5 111f6c63835SKrzysztof Helt #define HPIO_210 6 112f6c63835SKrzysztof Helt #define HPIO_3E0 7 113f6c63835SKrzysztof Helt 114f6c63835SKrzysztof Helt #define HPMEM_NONE 0 115f6c63835SKrzysztof Helt #define HPMEM_B000 1 116f6c63835SKrzysztof Helt #define HPMEM_C800 2 117f6c63835SKrzysztof Helt #define HPMEM_D000 3 118f6c63835SKrzysztof Helt #define HPMEM_D400 4 119f6c63835SKrzysztof Helt #define HPMEM_D800 5 120f6c63835SKrzysztof Helt #define HPMEM_E000 6 121f6c63835SKrzysztof Helt #define HPMEM_E800 7 122f6c63835SKrzysztof Helt 123f6c63835SKrzysztof Helt #define HPIRQ_NONE 0 124f6c63835SKrzysztof Helt #define HPIRQ_5 1 125f6c63835SKrzysztof Helt #define HPIRQ_7 2 126f6c63835SKrzysztof Helt #define HPIRQ_9 3 127f6c63835SKrzysztof Helt #define HPIRQ_10 4 128f6c63835SKrzysztof Helt #define HPIRQ_11 5 129f6c63835SKrzysztof Helt #define HPIRQ_12 6 130f6c63835SKrzysztof Helt #define HPIRQ_15 7 131f6c63835SKrzysztof Helt 132f6c63835SKrzysztof Helt #define HIMT_PLAY_DONE 0x00 133f6c63835SKrzysztof Helt #define HIMT_RECORD_DONE 0x01 134f6c63835SKrzysztof Helt #define HIMT_MIDI_EOS 0x02 135f6c63835SKrzysztof Helt #define HIMT_MIDI_OUT 0x03 136f6c63835SKrzysztof Helt 137f6c63835SKrzysztof Helt #define HIMT_MIDI_IN_UCHAR 0x0E 138f6c63835SKrzysztof Helt #define HIMT_DSP 0x0F 139f6c63835SKrzysztof Helt 140f6c63835SKrzysztof Helt #define HDEX_BASE 0x92 141f6c63835SKrzysztof Helt #define HDEX_PLAY_START (0 + HDEX_BASE) 142f6c63835SKrzysztof Helt #define HDEX_PLAY_STOP (1 + HDEX_BASE) 143f6c63835SKrzysztof Helt #define HDEX_PLAY_PAUSE (2 + HDEX_BASE) 144f6c63835SKrzysztof Helt #define HDEX_PLAY_RESUME (3 + HDEX_BASE) 145f6c63835SKrzysztof Helt #define HDEX_RECORD_START (4 + HDEX_BASE) 146f6c63835SKrzysztof Helt #define HDEX_RECORD_STOP (5 + HDEX_BASE) 147f6c63835SKrzysztof Helt #define HDEX_MIDI_IN_START (6 + HDEX_BASE) 148f6c63835SKrzysztof Helt #define HDEX_MIDI_IN_STOP (7 + HDEX_BASE) 149f6c63835SKrzysztof Helt #define HDEX_MIDI_OUT_START (8 + HDEX_BASE) 150f6c63835SKrzysztof Helt #define HDEX_MIDI_OUT_STOP (9 + HDEX_BASE) 151f6c63835SKrzysztof Helt #define HDEX_AUX_REQ (10 + HDEX_BASE) 152f6c63835SKrzysztof Helt 153f6c63835SKrzysztof Helt #define HDEXAR_CLEAR_PEAKS 1 154f6c63835SKrzysztof Helt #define HDEXAR_IN_SET_POTS 2 155f6c63835SKrzysztof Helt #define HDEXAR_AUX_SET_POTS 3 156f6c63835SKrzysztof Helt #define HDEXAR_CAL_A_TO_D 4 157f6c63835SKrzysztof Helt #define HDEXAR_RD_EXT_DSP_BITS 5 158f6c63835SKrzysztof Helt 159f6c63835SKrzysztof Helt /* Pinnacle only HDEXAR defs */ 160f6c63835SKrzysztof Helt #define HDEXAR_SET_ANA_IN 0 161f6c63835SKrzysztof Helt #define HDEXAR_SET_SYNTH_IN 4 162f6c63835SKrzysztof Helt #define HDEXAR_READ_DAT_IN 5 163f6c63835SKrzysztof Helt #define HDEXAR_MIC_SET_POTS 6 164f6c63835SKrzysztof Helt #define HDEXAR_SET_DAT_IN 7 165f6c63835SKrzysztof Helt 166f6c63835SKrzysztof Helt #define HDEXAR_SET_SYNTH_48 8 167f6c63835SKrzysztof Helt #define HDEXAR_SET_SYNTH_44 9 168f6c63835SKrzysztof Helt 169f6c63835SKrzysztof Helt #define HIWORD(l) ((u16)((((u32)(l)) >> 16) & 0xFFFF)) 170f6c63835SKrzysztof Helt #define LOWORD(l) ((u16)(u32)(l)) 171f6c63835SKrzysztof Helt #define HIBYTE(w) ((u8)(((u16)(w) >> 8) & 0xFF)) 172f6c63835SKrzysztof Helt #define LOBYTE(w) ((u8)(w)) 173f6c63835SKrzysztof Helt #define MAKELONG(low, hi) ((long)(((u16)(low))|(((u32)((u16)(hi)))<<16))) 174f6c63835SKrzysztof Helt #define MAKEWORD(low, hi) ((u16)(((u8)(low))|(((u16)((u8)(hi)))<<8))) 175f6c63835SKrzysztof Helt 176f6c63835SKrzysztof Helt #define PCTODSP_OFFSET(w) (u16)((w)/2) 177f6c63835SKrzysztof Helt #define PCTODSP_BASED(w) (u16)(((w)/2) + DSP_BASE_ADDR) 178f6c63835SKrzysztof Helt #define DSPTOPC_BASED(w) (((w) - DSP_BASE_ADDR) * 2) 179f6c63835SKrzysztof Helt 180f6c63835SKrzysztof Helt #ifdef SLOWIO 181f6c63835SKrzysztof Helt # undef outb 182f6c63835SKrzysztof Helt # undef inb 183f6c63835SKrzysztof Helt # define outb outb_p 184f6c63835SKrzysztof Helt # define inb inb_p 185f6c63835SKrzysztof Helt #endif 186f6c63835SKrzysztof Helt 187f6c63835SKrzysztof Helt /* JobQueueStruct */ 188f6c63835SKrzysztof Helt #define JQS_wStart 0x00 189f6c63835SKrzysztof Helt #define JQS_wSize 0x02 190f6c63835SKrzysztof Helt #define JQS_wHead 0x04 191f6c63835SKrzysztof Helt #define JQS_wTail 0x06 192f6c63835SKrzysztof Helt #define JQS__size 0x08 193f6c63835SKrzysztof Helt 194f6c63835SKrzysztof Helt /* DAQueueDataStruct */ 195f6c63835SKrzysztof Helt #define DAQDS_wStart 0x00 196f6c63835SKrzysztof Helt #define DAQDS_wSize 0x02 197f6c63835SKrzysztof Helt #define DAQDS_wFormat 0x04 198f6c63835SKrzysztof Helt #define DAQDS_wSampleSize 0x06 199f6c63835SKrzysztof Helt #define DAQDS_wChannels 0x08 200f6c63835SKrzysztof Helt #define DAQDS_wSampleRate 0x0A 201f6c63835SKrzysztof Helt #define DAQDS_wIntMsg 0x0C 202f6c63835SKrzysztof Helt #define DAQDS_wFlags 0x0E 203f6c63835SKrzysztof Helt #define DAQDS__size 0x10 204f6c63835SKrzysztof Helt 205f6c63835SKrzysztof Helt #include <sound/pcm.h> 206f6c63835SKrzysztof Helt 207f6c63835SKrzysztof Helt struct snd_msnd { 208f6c63835SKrzysztof Helt void __iomem *mappedbase; 209f6c63835SKrzysztof Helt int play_period_bytes; 210f6c63835SKrzysztof Helt int playLimit; 211f6c63835SKrzysztof Helt int playPeriods; 212f6c63835SKrzysztof Helt int playDMAPos; 213f6c63835SKrzysztof Helt int banksPlayed; 214f6c63835SKrzysztof Helt int captureDMAPos; 215f6c63835SKrzysztof Helt int capturePeriodBytes; 216f6c63835SKrzysztof Helt int captureLimit; 217f6c63835SKrzysztof Helt int capturePeriods; 218f6c63835SKrzysztof Helt struct snd_card *card; 219f6c63835SKrzysztof Helt void *msndmidi_mpu; 220f6c63835SKrzysztof Helt struct snd_rawmidi *rmidi; 221f6c63835SKrzysztof Helt 222f6c63835SKrzysztof Helt /* Hardware resources */ 223f6c63835SKrzysztof Helt long io; 224f6c63835SKrzysztof Helt int memid, irqid; 225f6c63835SKrzysztof Helt int irq, irq_ref; 226f6c63835SKrzysztof Helt unsigned long base; 227f6c63835SKrzysztof Helt 228f6c63835SKrzysztof Helt /* Motorola 56k DSP SMA */ 229f6c63835SKrzysztof Helt void __iomem *SMA; 230f6c63835SKrzysztof Helt void __iomem *DAPQ; 231f6c63835SKrzysztof Helt void __iomem *DARQ; 232f6c63835SKrzysztof Helt void __iomem *MODQ; 233f6c63835SKrzysztof Helt void __iomem *MIDQ; 234f6c63835SKrzysztof Helt void __iomem *DSPQ; 235f6c63835SKrzysztof Helt int dspq_data_buff, dspq_buff_size; 236f6c63835SKrzysztof Helt 237f6c63835SKrzysztof Helt /* State variables */ 238f6c63835SKrzysztof Helt enum { msndClassic, msndPinnacle } type; 239da404dc0SAl Viro fmode_t mode; 240f6c63835SKrzysztof Helt unsigned long flags; 241f6c63835SKrzysztof Helt #define F_RESETTING 0 242f6c63835SKrzysztof Helt #define F_HAVEDIGITAL 1 243f6c63835SKrzysztof Helt #define F_AUDIO_WRITE_INUSE 2 244f6c63835SKrzysztof Helt #define F_WRITING 3 245f6c63835SKrzysztof Helt #define F_WRITEBLOCK 4 246f6c63835SKrzysztof Helt #define F_WRITEFLUSH 5 247f6c63835SKrzysztof Helt #define F_AUDIO_READ_INUSE 6 248f6c63835SKrzysztof Helt #define F_READING 7 249f6c63835SKrzysztof Helt #define F_READBLOCK 8 250f6c63835SKrzysztof Helt #define F_EXT_MIDI_INUSE 9 251f6c63835SKrzysztof Helt #define F_HDR_MIDI_INUSE 10 252f6c63835SKrzysztof Helt #define F_DISABLE_WRITE_NDELAY 11 253f6c63835SKrzysztof Helt spinlock_t lock; 254f6c63835SKrzysztof Helt spinlock_t mixer_lock; 255f6c63835SKrzysztof Helt int nresets; 256f6c63835SKrzysztof Helt unsigned recsrc; 257f6c63835SKrzysztof Helt #define LEVEL_ENTRIES 32 258f6c63835SKrzysztof Helt int left_levels[LEVEL_ENTRIES]; 259f6c63835SKrzysztof Helt int right_levels[LEVEL_ENTRIES]; 260f6c63835SKrzysztof Helt int calibrate_signal; 261f6c63835SKrzysztof Helt int play_sample_size, play_sample_rate, play_channels; 262f6c63835SKrzysztof Helt int play_ndelay; 263f6c63835SKrzysztof Helt int capture_sample_size, capture_sample_rate, capture_channels; 264f6c63835SKrzysztof Helt int capture_ndelay; 265f6c63835SKrzysztof Helt u8 bCurrentMidiPatch; 266f6c63835SKrzysztof Helt 267f6c63835SKrzysztof Helt int last_playbank, last_recbank; 268f6c63835SKrzysztof Helt struct snd_pcm_substream *playback_substream; 269f6c63835SKrzysztof Helt struct snd_pcm_substream *capture_substream; 270f6c63835SKrzysztof Helt 271f6c63835SKrzysztof Helt }; 272f6c63835SKrzysztof Helt 273ab647a2dSTakashi Iwai void snd_msnd_init_queue(void __iomem *base, int start, int size); 274f6c63835SKrzysztof Helt 275f6c63835SKrzysztof Helt int snd_msnd_send_dsp_cmd(struct snd_msnd *chip, u8 cmd); 276f6c63835SKrzysztof Helt int snd_msnd_send_word(struct snd_msnd *chip, 277f6c63835SKrzysztof Helt unsigned char high, 278f6c63835SKrzysztof Helt unsigned char mid, 279f6c63835SKrzysztof Helt unsigned char low); 280f6c63835SKrzysztof Helt int snd_msnd_upload_host(struct snd_msnd *chip, 281f6c63835SKrzysztof Helt const u8 *bin, int len); 282f6c63835SKrzysztof Helt int snd_msnd_enable_irq(struct snd_msnd *chip); 283f6c63835SKrzysztof Helt int snd_msnd_disable_irq(struct snd_msnd *chip); 284f6c63835SKrzysztof Helt void snd_msnd_dsp_halt(struct snd_msnd *chip, struct file *file); 285f6c63835SKrzysztof Helt int snd_msnd_DAPQ(struct snd_msnd *chip, int start); 286f6c63835SKrzysztof Helt int snd_msnd_DARQ(struct snd_msnd *chip, int start); 287f6be4e62SLars-Peter Clausen int snd_msnd_pcm(struct snd_card *card, int device); 288f6c63835SKrzysztof Helt 289f6c63835SKrzysztof Helt int snd_msndmidi_new(struct snd_card *card, int device); 290f6c63835SKrzysztof Helt void snd_msndmidi_input_read(void *mpu); 291f6c63835SKrzysztof Helt 292f6c63835SKrzysztof Helt void snd_msndmix_setup(struct snd_msnd *chip); 2931bff292eSBill Pemberton int snd_msndmix_new(struct snd_card *card); 294f6c63835SKrzysztof Helt int snd_msndmix_force_recsrc(struct snd_msnd *chip, int recsrc); 295f6c63835SKrzysztof Helt #endif /* __MSND_H */ 296