1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Audio and Music Data Transmission Protocol (IEC 61883-6) streams 4 * with Common Isochronous Packet (IEC 61883-1) headers 5 * 6 * Copyright (c) Clemens Ladisch <clemens@ladisch.de> 7 */ 8 9 #include <linux/device.h> 10 #include <linux/err.h> 11 #include <linux/firewire.h> 12 #include <linux/firewire-constants.h> 13 #include <linux/module.h> 14 #include <linux/slab.h> 15 #include <sound/pcm.h> 16 #include <sound/pcm_params.h> 17 #include "amdtp-stream.h" 18 19 #define TICKS_PER_CYCLE 3072 20 #define CYCLES_PER_SECOND 8000 21 #define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND) 22 23 #define OHCI_MAX_SECOND 8 24 25 /* Always support Linux tracing subsystem. */ 26 #define CREATE_TRACE_POINTS 27 #include "amdtp-stream-trace.h" 28 29 #define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */ 30 31 /* isochronous header parameters */ 32 #define ISO_DATA_LENGTH_SHIFT 16 33 #define TAG_NO_CIP_HEADER 0 34 #define TAG_CIP 1 35 36 /* common isochronous packet header parameters */ 37 #define CIP_EOH_SHIFT 31 38 #define CIP_EOH (1u << CIP_EOH_SHIFT) 39 #define CIP_EOH_MASK 0x80000000 40 #define CIP_SID_SHIFT 24 41 #define CIP_SID_MASK 0x3f000000 42 #define CIP_DBS_MASK 0x00ff0000 43 #define CIP_DBS_SHIFT 16 44 #define CIP_SPH_MASK 0x00000400 45 #define CIP_SPH_SHIFT 10 46 #define CIP_DBC_MASK 0x000000ff 47 #define CIP_FMT_SHIFT 24 48 #define CIP_FMT_MASK 0x3f000000 49 #define CIP_FDF_MASK 0x00ff0000 50 #define CIP_FDF_SHIFT 16 51 #define CIP_SYT_MASK 0x0000ffff 52 #define CIP_SYT_NO_INFO 0xffff 53 54 /* Audio and Music transfer protocol specific parameters */ 55 #define CIP_FMT_AM 0x10 56 #define AMDTP_FDF_NO_DATA 0xff 57 58 // For iso header, tstamp and 2 CIP header. 59 #define IR_CTX_HEADER_SIZE_CIP 16 60 // For iso header and tstamp. 61 #define IR_CTX_HEADER_SIZE_NO_CIP 8 62 #define HEADER_TSTAMP_MASK 0x0000ffff 63 64 #define IT_PKT_HEADER_SIZE_CIP 8 // For 2 CIP header. 65 #define IT_PKT_HEADER_SIZE_NO_CIP 0 // Nothing. 66 67 // The initial firmware of OXFW970 can postpone transmission of packet during finishing 68 // asynchronous transaction. This module accepts 5 cycles to skip as maximum to avoid buffer 69 // overrun. Actual device can skip more, then this module stops the packet streaming. 70 #define IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES 5 71 72 static void pcm_period_work(struct work_struct *work); 73 74 /** 75 * amdtp_stream_init - initialize an AMDTP stream structure 76 * @s: the AMDTP stream to initialize 77 * @unit: the target of the stream 78 * @dir: the direction of stream 79 * @flags: the details of the streaming protocol consist of cip_flags enumeration-constants. 80 * @fmt: the value of fmt field in CIP header 81 * @process_ctx_payloads: callback handler to process payloads of isoc context 82 * @protocol_size: the size to allocate newly for protocol 83 */ 84 int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit, 85 enum amdtp_stream_direction dir, unsigned int flags, 86 unsigned int fmt, 87 amdtp_stream_process_ctx_payloads_t process_ctx_payloads, 88 unsigned int protocol_size) 89 { 90 if (process_ctx_payloads == NULL) 91 return -EINVAL; 92 93 s->protocol = kzalloc(protocol_size, GFP_KERNEL); 94 if (!s->protocol) 95 return -ENOMEM; 96 97 s->unit = unit; 98 s->direction = dir; 99 s->flags = flags; 100 s->context = ERR_PTR(-1); 101 mutex_init(&s->mutex); 102 INIT_WORK(&s->period_work, pcm_period_work); 103 s->packet_index = 0; 104 105 init_waitqueue_head(&s->callback_wait); 106 s->callbacked = false; 107 108 s->fmt = fmt; 109 s->process_ctx_payloads = process_ctx_payloads; 110 111 if (dir == AMDTP_OUT_STREAM) 112 s->ctx_data.rx.syt_override = -1; 113 114 return 0; 115 } 116 EXPORT_SYMBOL(amdtp_stream_init); 117 118 /** 119 * amdtp_stream_destroy - free stream resources 120 * @s: the AMDTP stream to destroy 121 */ 122 void amdtp_stream_destroy(struct amdtp_stream *s) 123 { 124 /* Not initialized. */ 125 if (s->protocol == NULL) 126 return; 127 128 WARN_ON(amdtp_stream_running(s)); 129 kfree(s->protocol); 130 mutex_destroy(&s->mutex); 131 } 132 EXPORT_SYMBOL(amdtp_stream_destroy); 133 134 const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = { 135 [CIP_SFC_32000] = 8, 136 [CIP_SFC_44100] = 8, 137 [CIP_SFC_48000] = 8, 138 [CIP_SFC_88200] = 16, 139 [CIP_SFC_96000] = 16, 140 [CIP_SFC_176400] = 32, 141 [CIP_SFC_192000] = 32, 142 }; 143 EXPORT_SYMBOL(amdtp_syt_intervals); 144 145 const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = { 146 [CIP_SFC_32000] = 32000, 147 [CIP_SFC_44100] = 44100, 148 [CIP_SFC_48000] = 48000, 149 [CIP_SFC_88200] = 88200, 150 [CIP_SFC_96000] = 96000, 151 [CIP_SFC_176400] = 176400, 152 [CIP_SFC_192000] = 192000, 153 }; 154 EXPORT_SYMBOL(amdtp_rate_table); 155 156 static int apply_constraint_to_size(struct snd_pcm_hw_params *params, 157 struct snd_pcm_hw_rule *rule) 158 { 159 struct snd_interval *s = hw_param_interval(params, rule->var); 160 const struct snd_interval *r = 161 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE); 162 struct snd_interval t = {0}; 163 unsigned int step = 0; 164 int i; 165 166 for (i = 0; i < CIP_SFC_COUNT; ++i) { 167 if (snd_interval_test(r, amdtp_rate_table[i])) 168 step = max(step, amdtp_syt_intervals[i]); 169 } 170 171 t.min = roundup(s->min, step); 172 t.max = rounddown(s->max, step); 173 t.integer = 1; 174 175 return snd_interval_refine(s, &t); 176 } 177 178 /** 179 * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream 180 * @s: the AMDTP stream, which must be initialized. 181 * @runtime: the PCM substream runtime 182 */ 183 int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s, 184 struct snd_pcm_runtime *runtime) 185 { 186 struct snd_pcm_hardware *hw = &runtime->hw; 187 unsigned int ctx_header_size; 188 unsigned int maximum_usec_per_period; 189 int err; 190 191 hw->info = SNDRV_PCM_INFO_BATCH | 192 SNDRV_PCM_INFO_BLOCK_TRANSFER | 193 SNDRV_PCM_INFO_INTERLEAVED | 194 SNDRV_PCM_INFO_JOINT_DUPLEX | 195 SNDRV_PCM_INFO_MMAP | 196 SNDRV_PCM_INFO_MMAP_VALID; 197 198 /* SNDRV_PCM_INFO_BATCH */ 199 hw->periods_min = 2; 200 hw->periods_max = UINT_MAX; 201 202 /* bytes for a frame */ 203 hw->period_bytes_min = 4 * hw->channels_max; 204 205 /* Just to prevent from allocating much pages. */ 206 hw->period_bytes_max = hw->period_bytes_min * 2048; 207 hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min; 208 209 // Linux driver for 1394 OHCI controller voluntarily flushes isoc 210 // context when total size of accumulated context header reaches 211 // PAGE_SIZE. This kicks work for the isoc context and brings 212 // callback in the middle of scheduled interrupts. 213 // Although AMDTP streams in the same domain use the same events per 214 // IRQ, use the largest size of context header between IT/IR contexts. 215 // Here, use the value of context header in IR context is for both 216 // contexts. 217 if (!(s->flags & CIP_NO_HEADER)) 218 ctx_header_size = IR_CTX_HEADER_SIZE_CIP; 219 else 220 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP; 221 maximum_usec_per_period = USEC_PER_SEC * PAGE_SIZE / 222 CYCLES_PER_SECOND / ctx_header_size; 223 224 // In IEC 61883-6, one isoc packet can transfer events up to the value 225 // of syt interval. This comes from the interval of isoc cycle. As 1394 226 // OHCI controller can generate hardware IRQ per isoc packet, the 227 // interval is 125 usec. 228 // However, there are two ways of transmission in IEC 61883-6; blocking 229 // and non-blocking modes. In blocking mode, the sequence of isoc packet 230 // includes 'empty' or 'NODATA' packets which include no event. In 231 // non-blocking mode, the number of events per packet is variable up to 232 // the syt interval. 233 // Due to the above protocol design, the minimum PCM frames per 234 // interrupt should be double of the value of syt interval, thus it is 235 // 250 usec. 236 err = snd_pcm_hw_constraint_minmax(runtime, 237 SNDRV_PCM_HW_PARAM_PERIOD_TIME, 238 250, maximum_usec_per_period); 239 if (err < 0) 240 goto end; 241 242 /* Non-Blocking stream has no more constraints */ 243 if (!(s->flags & CIP_BLOCKING)) 244 goto end; 245 246 /* 247 * One AMDTP packet can include some frames. In blocking mode, the 248 * number equals to SYT_INTERVAL. So the number is 8, 16 or 32, 249 * depending on its sampling rate. For accurate period interrupt, it's 250 * preferrable to align period/buffer sizes to current SYT_INTERVAL. 251 */ 252 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 253 apply_constraint_to_size, NULL, 254 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 255 SNDRV_PCM_HW_PARAM_RATE, -1); 256 if (err < 0) 257 goto end; 258 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 259 apply_constraint_to_size, NULL, 260 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 261 SNDRV_PCM_HW_PARAM_RATE, -1); 262 if (err < 0) 263 goto end; 264 end: 265 return err; 266 } 267 EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints); 268 269 /** 270 * amdtp_stream_set_parameters - set stream parameters 271 * @s: the AMDTP stream to configure 272 * @rate: the sample rate 273 * @data_block_quadlets: the size of a data block in quadlet unit 274 * 275 * The parameters must be set before the stream is started, and must not be 276 * changed while the stream is running. 277 */ 278 int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate, 279 unsigned int data_block_quadlets) 280 { 281 unsigned int sfc; 282 283 for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) { 284 if (amdtp_rate_table[sfc] == rate) 285 break; 286 } 287 if (sfc == ARRAY_SIZE(amdtp_rate_table)) 288 return -EINVAL; 289 290 s->sfc = sfc; 291 s->data_block_quadlets = data_block_quadlets; 292 s->syt_interval = amdtp_syt_intervals[sfc]; 293 294 // default buffering in the device. 295 if (s->direction == AMDTP_OUT_STREAM) { 296 s->ctx_data.rx.transfer_delay = 297 TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE; 298 299 if (s->flags & CIP_BLOCKING) { 300 // additional buffering needed to adjust for no-data 301 // packets. 302 s->ctx_data.rx.transfer_delay += 303 TICKS_PER_SECOND * s->syt_interval / rate; 304 } 305 } 306 307 return 0; 308 } 309 EXPORT_SYMBOL(amdtp_stream_set_parameters); 310 311 /** 312 * amdtp_stream_get_max_payload - get the stream's packet size 313 * @s: the AMDTP stream 314 * 315 * This function must not be called before the stream has been configured 316 * with amdtp_stream_set_parameters(). 317 */ 318 unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s) 319 { 320 unsigned int multiplier = 1; 321 unsigned int cip_header_size = 0; 322 323 if (s->flags & CIP_JUMBO_PAYLOAD) 324 multiplier = IR_JUMBO_PAYLOAD_MAX_SKIP_CYCLES; 325 if (!(s->flags & CIP_NO_HEADER)) 326 cip_header_size = sizeof(__be32) * 2; 327 328 return cip_header_size + 329 s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier; 330 } 331 EXPORT_SYMBOL(amdtp_stream_get_max_payload); 332 333 /** 334 * amdtp_stream_pcm_prepare - prepare PCM device for running 335 * @s: the AMDTP stream 336 * 337 * This function should be called from the PCM device's .prepare callback. 338 */ 339 void amdtp_stream_pcm_prepare(struct amdtp_stream *s) 340 { 341 cancel_work_sync(&s->period_work); 342 s->pcm_buffer_pointer = 0; 343 s->pcm_period_pointer = 0; 344 } 345 EXPORT_SYMBOL(amdtp_stream_pcm_prepare); 346 347 static unsigned int calculate_data_blocks(unsigned int *data_block_state, 348 bool is_blocking, bool is_no_info, 349 unsigned int syt_interval, enum cip_sfc sfc) 350 { 351 unsigned int data_blocks; 352 353 /* Blocking mode. */ 354 if (is_blocking) { 355 /* This module generate empty packet for 'no data'. */ 356 if (is_no_info) 357 data_blocks = 0; 358 else 359 data_blocks = syt_interval; 360 /* Non-blocking mode. */ 361 } else { 362 if (!cip_sfc_is_base_44100(sfc)) { 363 // Sample_rate / 8000 is an integer, and precomputed. 364 data_blocks = *data_block_state; 365 } else { 366 unsigned int phase = *data_block_state; 367 368 /* 369 * This calculates the number of data blocks per packet so that 370 * 1) the overall rate is correct and exactly synchronized to 371 * the bus clock, and 372 * 2) packets with a rounded-up number of blocks occur as early 373 * as possible in the sequence (to prevent underruns of the 374 * device's buffer). 375 */ 376 if (sfc == CIP_SFC_44100) 377 /* 6 6 5 6 5 6 5 ... */ 378 data_blocks = 5 + ((phase & 1) ^ 379 (phase == 0 || phase >= 40)); 380 else 381 /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */ 382 data_blocks = 11 * (sfc >> 1) + (phase == 0); 383 if (++phase >= (80 >> (sfc >> 1))) 384 phase = 0; 385 *data_block_state = phase; 386 } 387 } 388 389 return data_blocks; 390 } 391 392 static unsigned int calculate_syt_offset(unsigned int *last_syt_offset, 393 unsigned int *syt_offset_state, enum cip_sfc sfc) 394 { 395 unsigned int syt_offset; 396 397 if (*last_syt_offset < TICKS_PER_CYCLE) { 398 if (!cip_sfc_is_base_44100(sfc)) 399 syt_offset = *last_syt_offset + *syt_offset_state; 400 else { 401 /* 402 * The time, in ticks, of the n'th SYT_INTERVAL sample is: 403 * n * SYT_INTERVAL * 24576000 / sample_rate 404 * Modulo TICKS_PER_CYCLE, the difference between successive 405 * elements is about 1386.23. Rounding the results of this 406 * formula to the SYT precision results in a sequence of 407 * differences that begins with: 408 * 1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ... 409 * This code generates _exactly_ the same sequence. 410 */ 411 unsigned int phase = *syt_offset_state; 412 unsigned int index = phase % 13; 413 414 syt_offset = *last_syt_offset; 415 syt_offset += 1386 + ((index && !(index & 3)) || 416 phase == 146); 417 if (++phase >= 147) 418 phase = 0; 419 *syt_offset_state = phase; 420 } 421 } else 422 syt_offset = *last_syt_offset - TICKS_PER_CYCLE; 423 *last_syt_offset = syt_offset; 424 425 if (syt_offset >= TICKS_PER_CYCLE) 426 syt_offset = CIP_SYT_NO_INFO; 427 428 return syt_offset; 429 } 430 431 static void update_pcm_pointers(struct amdtp_stream *s, 432 struct snd_pcm_substream *pcm, 433 unsigned int frames) 434 { 435 unsigned int ptr; 436 437 ptr = s->pcm_buffer_pointer + frames; 438 if (ptr >= pcm->runtime->buffer_size) 439 ptr -= pcm->runtime->buffer_size; 440 WRITE_ONCE(s->pcm_buffer_pointer, ptr); 441 442 s->pcm_period_pointer += frames; 443 if (s->pcm_period_pointer >= pcm->runtime->period_size) { 444 s->pcm_period_pointer -= pcm->runtime->period_size; 445 queue_work(system_highpri_wq, &s->period_work); 446 } 447 } 448 449 static void pcm_period_work(struct work_struct *work) 450 { 451 struct amdtp_stream *s = container_of(work, struct amdtp_stream, 452 period_work); 453 struct snd_pcm_substream *pcm = READ_ONCE(s->pcm); 454 455 if (pcm) 456 snd_pcm_period_elapsed(pcm); 457 } 458 459 static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params, 460 bool sched_irq) 461 { 462 int err; 463 464 params->interrupt = sched_irq; 465 params->tag = s->tag; 466 params->sy = 0; 467 468 err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer, 469 s->buffer.packets[s->packet_index].offset); 470 if (err < 0) { 471 dev_err(&s->unit->device, "queueing error: %d\n", err); 472 goto end; 473 } 474 475 if (++s->packet_index >= s->queue_size) 476 s->packet_index = 0; 477 end: 478 return err; 479 } 480 481 static inline int queue_out_packet(struct amdtp_stream *s, 482 struct fw_iso_packet *params, bool sched_irq) 483 { 484 params->skip = 485 !!(params->header_length == 0 && params->payload_length == 0); 486 return queue_packet(s, params, sched_irq); 487 } 488 489 static inline int queue_in_packet(struct amdtp_stream *s, 490 struct fw_iso_packet *params) 491 { 492 // Queue one packet for IR context. 493 params->header_length = s->ctx_data.tx.ctx_header_size; 494 params->payload_length = s->ctx_data.tx.max_ctx_payload_length; 495 params->skip = false; 496 return queue_packet(s, params, false); 497 } 498 499 static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2], 500 unsigned int data_block_counter, unsigned int syt) 501 { 502 cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) | 503 (s->data_block_quadlets << CIP_DBS_SHIFT) | 504 ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) | 505 data_block_counter); 506 cip_header[1] = cpu_to_be32(CIP_EOH | 507 ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) | 508 ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) | 509 (syt & CIP_SYT_MASK)); 510 } 511 512 static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle, 513 struct fw_iso_packet *params, 514 unsigned int data_blocks, 515 unsigned int data_block_counter, 516 unsigned int syt, unsigned int index) 517 { 518 unsigned int payload_length; 519 __be32 *cip_header; 520 521 payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets; 522 params->payload_length = payload_length; 523 524 if (!(s->flags & CIP_NO_HEADER)) { 525 cip_header = (__be32 *)params->header; 526 generate_cip_header(s, cip_header, data_block_counter, syt); 527 params->header_length = 2 * sizeof(__be32); 528 payload_length += params->header_length; 529 } else { 530 cip_header = NULL; 531 } 532 533 trace_amdtp_packet(s, cycle, cip_header, payload_length, data_blocks, 534 data_block_counter, s->packet_index, index); 535 } 536 537 static int check_cip_header(struct amdtp_stream *s, const __be32 *buf, 538 unsigned int payload_length, 539 unsigned int *data_blocks, 540 unsigned int *data_block_counter, unsigned int *syt) 541 { 542 u32 cip_header[2]; 543 unsigned int sph; 544 unsigned int fmt; 545 unsigned int fdf; 546 unsigned int dbc; 547 bool lost; 548 549 cip_header[0] = be32_to_cpu(buf[0]); 550 cip_header[1] = be32_to_cpu(buf[1]); 551 552 /* 553 * This module supports 'Two-quadlet CIP header with SYT field'. 554 * For convenience, also check FMT field is AM824 or not. 555 */ 556 if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) || 557 ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) && 558 (!(s->flags & CIP_HEADER_WITHOUT_EOH))) { 559 dev_info_ratelimited(&s->unit->device, 560 "Invalid CIP header for AMDTP: %08X:%08X\n", 561 cip_header[0], cip_header[1]); 562 return -EAGAIN; 563 } 564 565 /* Check valid protocol or not. */ 566 sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT; 567 fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT; 568 if (sph != s->sph || fmt != s->fmt) { 569 dev_info_ratelimited(&s->unit->device, 570 "Detect unexpected protocol: %08x %08x\n", 571 cip_header[0], cip_header[1]); 572 return -EAGAIN; 573 } 574 575 /* Calculate data blocks */ 576 fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT; 577 if (payload_length < sizeof(__be32) * 2 || 578 (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) { 579 *data_blocks = 0; 580 } else { 581 unsigned int data_block_quadlets = 582 (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT; 583 /* avoid division by zero */ 584 if (data_block_quadlets == 0) { 585 dev_err(&s->unit->device, 586 "Detect invalid value in dbs field: %08X\n", 587 cip_header[0]); 588 return -EPROTO; 589 } 590 if (s->flags & CIP_WRONG_DBS) 591 data_block_quadlets = s->data_block_quadlets; 592 593 *data_blocks = (payload_length / sizeof(__be32) - 2) / 594 data_block_quadlets; 595 } 596 597 /* Check data block counter continuity */ 598 dbc = cip_header[0] & CIP_DBC_MASK; 599 if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) && 600 *data_block_counter != UINT_MAX) 601 dbc = *data_block_counter; 602 603 if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) || 604 *data_block_counter == UINT_MAX) { 605 lost = false; 606 } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) { 607 lost = dbc != *data_block_counter; 608 } else { 609 unsigned int dbc_interval; 610 611 if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0) 612 dbc_interval = s->ctx_data.tx.dbc_interval; 613 else 614 dbc_interval = *data_blocks; 615 616 lost = dbc != ((*data_block_counter + dbc_interval) & 0xff); 617 } 618 619 if (lost) { 620 dev_err(&s->unit->device, 621 "Detect discontinuity of CIP: %02X %02X\n", 622 *data_block_counter, dbc); 623 return -EIO; 624 } 625 626 *data_block_counter = dbc; 627 628 *syt = cip_header[1] & CIP_SYT_MASK; 629 630 return 0; 631 } 632 633 static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle, 634 const __be32 *ctx_header, 635 unsigned int *payload_length, 636 unsigned int *data_blocks, 637 unsigned int *data_block_counter, 638 unsigned int *syt, unsigned int packet_index, unsigned int index) 639 { 640 const __be32 *cip_header; 641 unsigned int cip_header_size; 642 int err; 643 644 *payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT; 645 646 if (!(s->flags & CIP_NO_HEADER)) 647 cip_header_size = 8; 648 else 649 cip_header_size = 0; 650 651 if (*payload_length > cip_header_size + s->ctx_data.tx.max_ctx_payload_length) { 652 dev_err(&s->unit->device, 653 "Detect jumbo payload: %04x %04x\n", 654 *payload_length, cip_header_size + s->ctx_data.tx.max_ctx_payload_length); 655 return -EIO; 656 } 657 658 if (cip_header_size > 0) { 659 cip_header = ctx_header + 2; 660 err = check_cip_header(s, cip_header, *payload_length, 661 data_blocks, data_block_counter, syt); 662 if (err < 0) 663 return err; 664 } else { 665 cip_header = NULL; 666 err = 0; 667 *data_blocks = *payload_length / sizeof(__be32) / 668 s->data_block_quadlets; 669 *syt = 0; 670 671 if (*data_block_counter == UINT_MAX) 672 *data_block_counter = 0; 673 } 674 675 trace_amdtp_packet(s, cycle, cip_header, *payload_length, *data_blocks, 676 *data_block_counter, packet_index, index); 677 678 return err; 679 } 680 681 // In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On 682 // the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent 683 // it. Thus, via Linux firewire subsystem, we can get the 3 bits for second. 684 static inline u32 compute_cycle_count(__be32 ctx_header_tstamp) 685 { 686 u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK; 687 return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff); 688 } 689 690 static inline u32 increment_cycle_count(u32 cycle, unsigned int addend) 691 { 692 cycle += addend; 693 if (cycle >= OHCI_MAX_SECOND * CYCLES_PER_SECOND) 694 cycle -= OHCI_MAX_SECOND * CYCLES_PER_SECOND; 695 return cycle; 696 } 697 698 // Align to actual cycle count for the packet which is going to be scheduled. 699 // This module queued the same number of isochronous cycle as the size of queue 700 // to kip isochronous cycle, therefore it's OK to just increment the cycle by 701 // the size of queue for scheduled cycle. 702 static inline u32 compute_it_cycle(const __be32 ctx_header_tstamp, 703 unsigned int queue_size) 704 { 705 u32 cycle = compute_cycle_count(ctx_header_tstamp); 706 return increment_cycle_count(cycle, queue_size); 707 } 708 709 static int generate_device_pkt_descs(struct amdtp_stream *s, 710 struct pkt_desc *descs, 711 const __be32 *ctx_header, 712 unsigned int packets) 713 { 714 unsigned int dbc = s->data_block_counter; 715 unsigned int packet_index = s->packet_index; 716 unsigned int queue_size = s->queue_size; 717 int i; 718 int err; 719 720 for (i = 0; i < packets; ++i) { 721 struct pkt_desc *desc = descs + i; 722 unsigned int cycle; 723 unsigned int payload_length; 724 unsigned int data_blocks; 725 unsigned int syt; 726 727 cycle = compute_cycle_count(ctx_header[1]); 728 729 err = parse_ir_ctx_header(s, cycle, ctx_header, &payload_length, 730 &data_blocks, &dbc, &syt, packet_index, i); 731 if (err < 0) 732 return err; 733 734 desc->cycle = cycle; 735 desc->syt = syt; 736 desc->data_blocks = data_blocks; 737 desc->data_block_counter = dbc; 738 desc->ctx_payload = s->buffer.packets[packet_index].buffer; 739 740 if (!(s->flags & CIP_DBC_IS_END_EVENT)) 741 dbc = (dbc + desc->data_blocks) & 0xff; 742 743 ctx_header += 744 s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header); 745 746 packet_index = (packet_index + 1) % queue_size; 747 } 748 749 s->data_block_counter = dbc; 750 751 return 0; 752 } 753 754 static unsigned int compute_syt(unsigned int syt_offset, unsigned int cycle, 755 unsigned int transfer_delay) 756 { 757 unsigned int syt; 758 759 syt_offset += transfer_delay; 760 syt = ((cycle + syt_offset / TICKS_PER_CYCLE) << 12) | 761 (syt_offset % TICKS_PER_CYCLE); 762 return syt & CIP_SYT_MASK; 763 } 764 765 static void generate_pkt_descs(struct amdtp_stream *s, struct pkt_desc *descs, 766 const __be32 *ctx_header, unsigned int packets, 767 const struct seq_desc *seq_descs, 768 unsigned int seq_size) 769 { 770 unsigned int dbc = s->data_block_counter; 771 unsigned int seq_index = s->ctx_data.rx.seq_index; 772 int i; 773 774 for (i = 0; i < packets; ++i) { 775 struct pkt_desc *desc = descs + i; 776 unsigned int index = (s->packet_index + i) % s->queue_size; 777 const struct seq_desc *seq = seq_descs + seq_index; 778 unsigned int syt; 779 780 desc->cycle = compute_it_cycle(*ctx_header, s->queue_size); 781 782 syt = seq->syt_offset; 783 if (syt != CIP_SYT_NO_INFO) { 784 syt = compute_syt(syt, desc->cycle, 785 s->ctx_data.rx.transfer_delay); 786 } 787 desc->syt = syt; 788 desc->data_blocks = seq->data_blocks; 789 790 if (s->flags & CIP_DBC_IS_END_EVENT) 791 dbc = (dbc + desc->data_blocks) & 0xff; 792 793 desc->data_block_counter = dbc; 794 795 if (!(s->flags & CIP_DBC_IS_END_EVENT)) 796 dbc = (dbc + desc->data_blocks) & 0xff; 797 798 desc->ctx_payload = s->buffer.packets[index].buffer; 799 800 seq_index = (seq_index + 1) % seq_size; 801 802 ++ctx_header; 803 } 804 805 s->data_block_counter = dbc; 806 s->ctx_data.rx.seq_index = seq_index; 807 } 808 809 static inline void cancel_stream(struct amdtp_stream *s) 810 { 811 s->packet_index = -1; 812 if (current_work() == &s->period_work) 813 amdtp_stream_pcm_abort(s); 814 WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN); 815 } 816 817 static void process_ctx_payloads(struct amdtp_stream *s, 818 const struct pkt_desc *descs, 819 unsigned int packets) 820 { 821 struct snd_pcm_substream *pcm; 822 unsigned int pcm_frames; 823 824 pcm = READ_ONCE(s->pcm); 825 pcm_frames = s->process_ctx_payloads(s, descs, packets, pcm); 826 if (pcm) 827 update_pcm_pointers(s, pcm, pcm_frames); 828 } 829 830 static void out_stream_callback(struct fw_iso_context *context, u32 tstamp, 831 size_t header_length, void *header, 832 void *private_data) 833 { 834 struct amdtp_stream *s = private_data; 835 const struct amdtp_domain *d = s->domain; 836 const __be32 *ctx_header = header; 837 unsigned int events_per_period = s->ctx_data.rx.events_per_period; 838 unsigned int event_count = s->ctx_data.rx.event_count; 839 unsigned int packets; 840 int i; 841 842 if (s->packet_index < 0) 843 return; 844 845 // Calculate the number of packets in buffer and check XRUN. 846 packets = header_length / sizeof(*ctx_header); 847 848 generate_pkt_descs(s, s->pkt_descs, ctx_header, packets, d->seq_descs, 849 d->seq_size); 850 851 process_ctx_payloads(s, s->pkt_descs, packets); 852 853 for (i = 0; i < packets; ++i) { 854 const struct pkt_desc *desc = s->pkt_descs + i; 855 unsigned int syt; 856 struct { 857 struct fw_iso_packet params; 858 __be32 header[IT_PKT_HEADER_SIZE_CIP / sizeof(__be32)]; 859 } template = { {0}, {0} }; 860 bool sched_irq = false; 861 862 if (s->ctx_data.rx.syt_override < 0) 863 syt = desc->syt; 864 else 865 syt = s->ctx_data.rx.syt_override; 866 867 build_it_pkt_header(s, desc->cycle, &template.params, 868 desc->data_blocks, desc->data_block_counter, 869 syt, i); 870 871 if (s == s->domain->irq_target) { 872 event_count += desc->data_blocks; 873 if (event_count >= events_per_period) { 874 event_count -= events_per_period; 875 sched_irq = true; 876 } 877 } 878 879 if (queue_out_packet(s, &template.params, sched_irq) < 0) { 880 cancel_stream(s); 881 return; 882 } 883 } 884 885 s->ctx_data.rx.event_count = event_count; 886 } 887 888 static void in_stream_callback(struct fw_iso_context *context, u32 tstamp, 889 size_t header_length, void *header, 890 void *private_data) 891 { 892 struct amdtp_stream *s = private_data; 893 __be32 *ctx_header = header; 894 unsigned int packets; 895 int i; 896 int err; 897 898 if (s->packet_index < 0) 899 return; 900 901 // Calculate the number of packets in buffer and check XRUN. 902 packets = header_length / s->ctx_data.tx.ctx_header_size; 903 904 err = generate_device_pkt_descs(s, s->pkt_descs, ctx_header, packets); 905 if (err < 0) { 906 if (err != -EAGAIN) { 907 cancel_stream(s); 908 return; 909 } 910 } else { 911 process_ctx_payloads(s, s->pkt_descs, packets); 912 } 913 914 for (i = 0; i < packets; ++i) { 915 struct fw_iso_packet params = {0}; 916 917 if (queue_in_packet(s, ¶ms) < 0) { 918 cancel_stream(s); 919 return; 920 } 921 } 922 } 923 924 static void pool_ideal_seq_descs(struct amdtp_domain *d, unsigned int packets) 925 { 926 struct amdtp_stream *irq_target = d->irq_target; 927 unsigned int seq_tail = d->seq_tail; 928 unsigned int seq_size = d->seq_size; 929 unsigned int min_avail; 930 struct amdtp_stream *s; 931 932 min_avail = d->seq_size; 933 list_for_each_entry(s, &d->streams, list) { 934 unsigned int seq_index; 935 unsigned int avail; 936 937 if (s->direction == AMDTP_IN_STREAM) 938 continue; 939 940 seq_index = s->ctx_data.rx.seq_index; 941 avail = d->seq_tail; 942 if (seq_index > avail) 943 avail += d->seq_size; 944 avail -= seq_index; 945 946 if (avail < min_avail) 947 min_avail = avail; 948 } 949 950 while (min_avail < packets) { 951 struct seq_desc *desc = d->seq_descs + seq_tail; 952 953 desc->syt_offset = calculate_syt_offset(&d->last_syt_offset, 954 &d->syt_offset_state, irq_target->sfc); 955 desc->data_blocks = calculate_data_blocks(&d->data_block_state, 956 !!(irq_target->flags & CIP_BLOCKING), 957 desc->syt_offset == CIP_SYT_NO_INFO, 958 irq_target->syt_interval, irq_target->sfc); 959 960 ++seq_tail; 961 seq_tail %= seq_size; 962 963 ++min_avail; 964 } 965 966 d->seq_tail = seq_tail; 967 } 968 969 static void irq_target_callback(struct fw_iso_context *context, u32 tstamp, 970 size_t header_length, void *header, 971 void *private_data) 972 { 973 struct amdtp_stream *irq_target = private_data; 974 struct amdtp_domain *d = irq_target->domain; 975 unsigned int packets = header_length / sizeof(__be32); 976 struct amdtp_stream *s; 977 978 // Record enough entries with extra 3 cycles at least. 979 pool_ideal_seq_descs(d, packets + 3); 980 981 out_stream_callback(context, tstamp, header_length, header, irq_target); 982 if (amdtp_streaming_error(irq_target)) 983 goto error; 984 985 list_for_each_entry(s, &d->streams, list) { 986 if (s != irq_target && amdtp_stream_running(s)) { 987 fw_iso_context_flush_completions(s->context); 988 if (amdtp_streaming_error(s)) 989 goto error; 990 } 991 } 992 993 return; 994 error: 995 if (amdtp_stream_running(irq_target)) 996 cancel_stream(irq_target); 997 998 list_for_each_entry(s, &d->streams, list) { 999 if (amdtp_stream_running(s)) 1000 cancel_stream(s); 1001 } 1002 } 1003 1004 // this is executed one time. 1005 static void amdtp_stream_first_callback(struct fw_iso_context *context, 1006 u32 tstamp, size_t header_length, 1007 void *header, void *private_data) 1008 { 1009 struct amdtp_stream *s = private_data; 1010 const __be32 *ctx_header = header; 1011 u32 cycle; 1012 1013 /* 1014 * For in-stream, first packet has come. 1015 * For out-stream, prepared to transmit first packet 1016 */ 1017 s->callbacked = true; 1018 wake_up(&s->callback_wait); 1019 1020 if (s->direction == AMDTP_IN_STREAM) { 1021 cycle = compute_cycle_count(ctx_header[1]); 1022 1023 context->callback.sc = in_stream_callback; 1024 } else { 1025 cycle = compute_it_cycle(*ctx_header, s->queue_size); 1026 1027 if (s == s->domain->irq_target) 1028 context->callback.sc = irq_target_callback; 1029 else 1030 context->callback.sc = out_stream_callback; 1031 } 1032 1033 s->start_cycle = cycle; 1034 1035 context->callback.sc(context, tstamp, header_length, header, s); 1036 } 1037 1038 /** 1039 * amdtp_stream_start - start transferring packets 1040 * @s: the AMDTP stream to start 1041 * @channel: the isochronous channel on the bus 1042 * @speed: firewire speed code 1043 * @start_cycle: the isochronous cycle to start the context. Start immediately 1044 * if negative value is given. 1045 * @queue_size: The number of packets in the queue. 1046 * @idle_irq_interval: the interval to queue packet during initial state. 1047 * 1048 * The stream cannot be started until it has been configured with 1049 * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI 1050 * device can be started. 1051 */ 1052 static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed, 1053 int start_cycle, unsigned int queue_size, 1054 unsigned int idle_irq_interval) 1055 { 1056 bool is_irq_target = (s == s->domain->irq_target); 1057 unsigned int ctx_header_size; 1058 unsigned int max_ctx_payload_size; 1059 enum dma_data_direction dir; 1060 int type, tag, err; 1061 1062 mutex_lock(&s->mutex); 1063 1064 if (WARN_ON(amdtp_stream_running(s) || 1065 (s->data_block_quadlets < 1))) { 1066 err = -EBADFD; 1067 goto err_unlock; 1068 } 1069 1070 if (s->direction == AMDTP_IN_STREAM) { 1071 // NOTE: IT context should be used for constant IRQ. 1072 if (is_irq_target) { 1073 err = -EINVAL; 1074 goto err_unlock; 1075 } 1076 1077 s->data_block_counter = UINT_MAX; 1078 } else { 1079 s->data_block_counter = 0; 1080 } 1081 1082 // initialize packet buffer. 1083 max_ctx_payload_size = amdtp_stream_get_max_payload(s); 1084 if (s->direction == AMDTP_IN_STREAM) { 1085 dir = DMA_FROM_DEVICE; 1086 type = FW_ISO_CONTEXT_RECEIVE; 1087 if (!(s->flags & CIP_NO_HEADER)) { 1088 max_ctx_payload_size -= 8; 1089 ctx_header_size = IR_CTX_HEADER_SIZE_CIP; 1090 } else { 1091 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP; 1092 } 1093 } else { 1094 dir = DMA_TO_DEVICE; 1095 type = FW_ISO_CONTEXT_TRANSMIT; 1096 ctx_header_size = 0; // No effect for IT context. 1097 1098 if (!(s->flags & CIP_NO_HEADER)) 1099 max_ctx_payload_size -= IT_PKT_HEADER_SIZE_CIP; 1100 } 1101 1102 err = iso_packets_buffer_init(&s->buffer, s->unit, queue_size, 1103 max_ctx_payload_size, dir); 1104 if (err < 0) 1105 goto err_unlock; 1106 s->queue_size = queue_size; 1107 1108 s->context = fw_iso_context_create(fw_parent_device(s->unit)->card, 1109 type, channel, speed, ctx_header_size, 1110 amdtp_stream_first_callback, s); 1111 if (IS_ERR(s->context)) { 1112 err = PTR_ERR(s->context); 1113 if (err == -EBUSY) 1114 dev_err(&s->unit->device, 1115 "no free stream on this controller\n"); 1116 goto err_buffer; 1117 } 1118 1119 amdtp_stream_update(s); 1120 1121 if (s->direction == AMDTP_IN_STREAM) { 1122 s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size; 1123 s->ctx_data.tx.ctx_header_size = ctx_header_size; 1124 } 1125 1126 if (s->flags & CIP_NO_HEADER) 1127 s->tag = TAG_NO_CIP_HEADER; 1128 else 1129 s->tag = TAG_CIP; 1130 1131 s->pkt_descs = kcalloc(s->queue_size, sizeof(*s->pkt_descs), 1132 GFP_KERNEL); 1133 if (!s->pkt_descs) { 1134 err = -ENOMEM; 1135 goto err_context; 1136 } 1137 1138 s->packet_index = 0; 1139 do { 1140 struct fw_iso_packet params; 1141 1142 if (s->direction == AMDTP_IN_STREAM) { 1143 err = queue_in_packet(s, ¶ms); 1144 } else { 1145 bool sched_irq = false; 1146 1147 params.header_length = 0; 1148 params.payload_length = 0; 1149 1150 if (is_irq_target) { 1151 sched_irq = !((s->packet_index + 1) % 1152 idle_irq_interval); 1153 } 1154 1155 err = queue_out_packet(s, ¶ms, sched_irq); 1156 } 1157 if (err < 0) 1158 goto err_pkt_descs; 1159 } while (s->packet_index > 0); 1160 1161 /* NOTE: TAG1 matches CIP. This just affects in stream. */ 1162 tag = FW_ISO_CONTEXT_MATCH_TAG1; 1163 if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER)) 1164 tag |= FW_ISO_CONTEXT_MATCH_TAG0; 1165 1166 s->callbacked = false; 1167 err = fw_iso_context_start(s->context, start_cycle, 0, tag); 1168 if (err < 0) 1169 goto err_pkt_descs; 1170 1171 mutex_unlock(&s->mutex); 1172 1173 return 0; 1174 err_pkt_descs: 1175 kfree(s->pkt_descs); 1176 err_context: 1177 fw_iso_context_destroy(s->context); 1178 s->context = ERR_PTR(-1); 1179 err_buffer: 1180 iso_packets_buffer_destroy(&s->buffer, s->unit); 1181 err_unlock: 1182 mutex_unlock(&s->mutex); 1183 1184 return err; 1185 } 1186 1187 /** 1188 * amdtp_domain_stream_pcm_pointer - get the PCM buffer position 1189 * @d: the AMDTP domain. 1190 * @s: the AMDTP stream that transports the PCM data 1191 * 1192 * Returns the current buffer position, in frames. 1193 */ 1194 unsigned long amdtp_domain_stream_pcm_pointer(struct amdtp_domain *d, 1195 struct amdtp_stream *s) 1196 { 1197 struct amdtp_stream *irq_target = d->irq_target; 1198 1199 if (irq_target && amdtp_stream_running(irq_target)) { 1200 // This function is called in software IRQ context of 1201 // period_work or process context. 1202 // 1203 // When the software IRQ context was scheduled by software IRQ 1204 // context of IT contexts, queued packets were already handled. 1205 // Therefore, no need to flush the queue in buffer furthermore. 1206 // 1207 // When the process context reach here, some packets will be 1208 // already queued in the buffer. These packets should be handled 1209 // immediately to keep better granularity of PCM pointer. 1210 // 1211 // Later, the process context will sometimes schedules software 1212 // IRQ context of the period_work. Then, no need to flush the 1213 // queue by the same reason as described in the above 1214 if (current_work() != &s->period_work) { 1215 // Queued packet should be processed without any kernel 1216 // preemption to keep latency against bus cycle. 1217 preempt_disable(); 1218 fw_iso_context_flush_completions(irq_target->context); 1219 preempt_enable(); 1220 } 1221 } 1222 1223 return READ_ONCE(s->pcm_buffer_pointer); 1224 } 1225 EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_pointer); 1226 1227 /** 1228 * amdtp_domain_stream_pcm_ack - acknowledge queued PCM frames 1229 * @d: the AMDTP domain. 1230 * @s: the AMDTP stream that transfers the PCM frames 1231 * 1232 * Returns zero always. 1233 */ 1234 int amdtp_domain_stream_pcm_ack(struct amdtp_domain *d, struct amdtp_stream *s) 1235 { 1236 struct amdtp_stream *irq_target = d->irq_target; 1237 1238 // Process isochronous packets for recent isochronous cycle to handle 1239 // queued PCM frames. 1240 if (irq_target && amdtp_stream_running(irq_target)) { 1241 // Queued packet should be processed without any kernel 1242 // preemption to keep latency against bus cycle. 1243 preempt_disable(); 1244 fw_iso_context_flush_completions(irq_target->context); 1245 preempt_enable(); 1246 } 1247 1248 return 0; 1249 } 1250 EXPORT_SYMBOL_GPL(amdtp_domain_stream_pcm_ack); 1251 1252 /** 1253 * amdtp_stream_update - update the stream after a bus reset 1254 * @s: the AMDTP stream 1255 */ 1256 void amdtp_stream_update(struct amdtp_stream *s) 1257 { 1258 /* Precomputing. */ 1259 WRITE_ONCE(s->source_node_id_field, 1260 (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK); 1261 } 1262 EXPORT_SYMBOL(amdtp_stream_update); 1263 1264 /** 1265 * amdtp_stream_stop - stop sending packets 1266 * @s: the AMDTP stream to stop 1267 * 1268 * All PCM and MIDI devices of the stream must be stopped before the stream 1269 * itself can be stopped. 1270 */ 1271 static void amdtp_stream_stop(struct amdtp_stream *s) 1272 { 1273 mutex_lock(&s->mutex); 1274 1275 if (!amdtp_stream_running(s)) { 1276 mutex_unlock(&s->mutex); 1277 return; 1278 } 1279 1280 cancel_work_sync(&s->period_work); 1281 fw_iso_context_stop(s->context); 1282 fw_iso_context_destroy(s->context); 1283 s->context = ERR_PTR(-1); 1284 iso_packets_buffer_destroy(&s->buffer, s->unit); 1285 kfree(s->pkt_descs); 1286 1287 s->callbacked = false; 1288 1289 mutex_unlock(&s->mutex); 1290 } 1291 1292 /** 1293 * amdtp_stream_pcm_abort - abort the running PCM device 1294 * @s: the AMDTP stream about to be stopped 1295 * 1296 * If the isochronous stream needs to be stopped asynchronously, call this 1297 * function first to stop the PCM device. 1298 */ 1299 void amdtp_stream_pcm_abort(struct amdtp_stream *s) 1300 { 1301 struct snd_pcm_substream *pcm; 1302 1303 pcm = READ_ONCE(s->pcm); 1304 if (pcm) 1305 snd_pcm_stop_xrun(pcm); 1306 } 1307 EXPORT_SYMBOL(amdtp_stream_pcm_abort); 1308 1309 /** 1310 * amdtp_domain_init - initialize an AMDTP domain structure 1311 * @d: the AMDTP domain to initialize. 1312 */ 1313 int amdtp_domain_init(struct amdtp_domain *d) 1314 { 1315 INIT_LIST_HEAD(&d->streams); 1316 1317 d->events_per_period = 0; 1318 1319 d->seq_descs = NULL; 1320 1321 return 0; 1322 } 1323 EXPORT_SYMBOL_GPL(amdtp_domain_init); 1324 1325 /** 1326 * amdtp_domain_destroy - destroy an AMDTP domain structure 1327 * @d: the AMDTP domain to destroy. 1328 */ 1329 void amdtp_domain_destroy(struct amdtp_domain *d) 1330 { 1331 // At present nothing to do. 1332 return; 1333 } 1334 EXPORT_SYMBOL_GPL(amdtp_domain_destroy); 1335 1336 /** 1337 * amdtp_domain_add_stream - register isoc context into the domain. 1338 * @d: the AMDTP domain. 1339 * @s: the AMDTP stream. 1340 * @channel: the isochronous channel on the bus. 1341 * @speed: firewire speed code. 1342 */ 1343 int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s, 1344 int channel, int speed) 1345 { 1346 struct amdtp_stream *tmp; 1347 1348 list_for_each_entry(tmp, &d->streams, list) { 1349 if (s == tmp) 1350 return -EBUSY; 1351 } 1352 1353 list_add(&s->list, &d->streams); 1354 1355 s->channel = channel; 1356 s->speed = speed; 1357 s->domain = d; 1358 1359 return 0; 1360 } 1361 EXPORT_SYMBOL_GPL(amdtp_domain_add_stream); 1362 1363 static int get_current_cycle_time(struct fw_card *fw_card, int *cur_cycle) 1364 { 1365 int generation; 1366 int rcode; 1367 __be32 reg; 1368 u32 data; 1369 1370 // This is a request to local 1394 OHCI controller and expected to 1371 // complete without any event waiting. 1372 generation = fw_card->generation; 1373 smp_rmb(); // node_id vs. generation. 1374 rcode = fw_run_transaction(fw_card, TCODE_READ_QUADLET_REQUEST, 1375 fw_card->node_id, generation, SCODE_100, 1376 CSR_REGISTER_BASE + CSR_CYCLE_TIME, 1377 ®, sizeof(reg)); 1378 if (rcode != RCODE_COMPLETE) 1379 return -EIO; 1380 1381 data = be32_to_cpu(reg); 1382 *cur_cycle = data >> 12; 1383 1384 return 0; 1385 } 1386 1387 /** 1388 * amdtp_domain_start - start sending packets for isoc context in the domain. 1389 * @d: the AMDTP domain. 1390 * @ir_delay_cycle: the cycle delay to start all IR contexts. 1391 */ 1392 int amdtp_domain_start(struct amdtp_domain *d, unsigned int ir_delay_cycle) 1393 { 1394 static const struct { 1395 unsigned int data_block; 1396 unsigned int syt_offset; 1397 } *entry, initial_state[] = { 1398 [CIP_SFC_32000] = { 4, 3072 }, 1399 [CIP_SFC_48000] = { 6, 1024 }, 1400 [CIP_SFC_96000] = { 12, 1024 }, 1401 [CIP_SFC_192000] = { 24, 1024 }, 1402 [CIP_SFC_44100] = { 0, 67 }, 1403 [CIP_SFC_88200] = { 0, 67 }, 1404 [CIP_SFC_176400] = { 0, 67 }, 1405 }; 1406 unsigned int events_per_buffer = d->events_per_buffer; 1407 unsigned int events_per_period = d->events_per_period; 1408 unsigned int idle_irq_interval; 1409 unsigned int queue_size; 1410 struct amdtp_stream *s; 1411 int cycle; 1412 int err; 1413 1414 // Select an IT context as IRQ target. 1415 list_for_each_entry(s, &d->streams, list) { 1416 if (s->direction == AMDTP_OUT_STREAM) 1417 break; 1418 } 1419 if (!s) 1420 return -ENXIO; 1421 d->irq_target = s; 1422 1423 // This is a case that AMDTP streams in domain run just for MIDI 1424 // substream. Use the number of events equivalent to 10 msec as 1425 // interval of hardware IRQ. 1426 if (events_per_period == 0) 1427 events_per_period = amdtp_rate_table[d->irq_target->sfc] / 100; 1428 if (events_per_buffer == 0) 1429 events_per_buffer = events_per_period * 3; 1430 1431 queue_size = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_buffer, 1432 amdtp_rate_table[d->irq_target->sfc]); 1433 1434 d->seq_descs = kcalloc(queue_size, sizeof(*d->seq_descs), GFP_KERNEL); 1435 if (!d->seq_descs) 1436 return -ENOMEM; 1437 d->seq_size = queue_size; 1438 d->seq_tail = 0; 1439 1440 entry = &initial_state[s->sfc]; 1441 d->data_block_state = entry->data_block; 1442 d->syt_offset_state = entry->syt_offset; 1443 d->last_syt_offset = TICKS_PER_CYCLE; 1444 1445 if (ir_delay_cycle > 0) { 1446 struct fw_card *fw_card = fw_parent_device(s->unit)->card; 1447 1448 err = get_current_cycle_time(fw_card, &cycle); 1449 if (err < 0) 1450 goto error; 1451 1452 // No need to care overflow in cycle field because of enough 1453 // width. 1454 cycle += ir_delay_cycle; 1455 1456 // Round up to sec field. 1457 if ((cycle & 0x00001fff) >= CYCLES_PER_SECOND) { 1458 unsigned int sec; 1459 1460 // The sec field can overflow. 1461 sec = (cycle & 0xffffe000) >> 13; 1462 cycle = (++sec << 13) | 1463 ((cycle & 0x00001fff) / CYCLES_PER_SECOND); 1464 } 1465 1466 // In OHCI 1394 specification, lower 2 bits are available for 1467 // sec field. 1468 cycle &= 0x00007fff; 1469 } else { 1470 cycle = -1; 1471 } 1472 1473 list_for_each_entry(s, &d->streams, list) { 1474 int cycle_match; 1475 1476 if (s->direction == AMDTP_IN_STREAM) { 1477 cycle_match = cycle; 1478 } else { 1479 // IT context starts immediately. 1480 cycle_match = -1; 1481 s->ctx_data.rx.seq_index = 0; 1482 } 1483 1484 if (s != d->irq_target) { 1485 err = amdtp_stream_start(s, s->channel, s->speed, 1486 cycle_match, queue_size, 0); 1487 if (err < 0) 1488 goto error; 1489 } 1490 } 1491 1492 s = d->irq_target; 1493 s->ctx_data.rx.events_per_period = events_per_period; 1494 s->ctx_data.rx.event_count = 0; 1495 s->ctx_data.rx.seq_index = 0; 1496 1497 idle_irq_interval = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period, 1498 amdtp_rate_table[d->irq_target->sfc]); 1499 err = amdtp_stream_start(s, s->channel, s->speed, -1, queue_size, 1500 idle_irq_interval); 1501 if (err < 0) 1502 goto error; 1503 1504 return 0; 1505 error: 1506 list_for_each_entry(s, &d->streams, list) 1507 amdtp_stream_stop(s); 1508 kfree(d->seq_descs); 1509 d->seq_descs = NULL; 1510 return err; 1511 } 1512 EXPORT_SYMBOL_GPL(amdtp_domain_start); 1513 1514 /** 1515 * amdtp_domain_stop - stop sending packets for isoc context in the same domain. 1516 * @d: the AMDTP domain to which the isoc contexts belong. 1517 */ 1518 void amdtp_domain_stop(struct amdtp_domain *d) 1519 { 1520 struct amdtp_stream *s, *next; 1521 1522 if (d->irq_target) 1523 amdtp_stream_stop(d->irq_target); 1524 1525 list_for_each_entry_safe(s, next, &d->streams, list) { 1526 list_del(&s->list); 1527 1528 if (s != d->irq_target) 1529 amdtp_stream_stop(s); 1530 } 1531 1532 d->events_per_period = 0; 1533 d->irq_target = NULL; 1534 1535 kfree(d->seq_descs); 1536 d->seq_descs = NULL; 1537 } 1538 EXPORT_SYMBOL_GPL(amdtp_domain_stop); 1539