xref: /openbmc/linux/sound/arm/aaci.c (revision e868d61272caa648214046a096e5a6bfc068dc8c)
1 /*
2  *  linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
3  *
4  *  Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  *  Documentation: ARM DDI 0173B
11  */
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/ioport.h>
16 #include <linux/device.h>
17 #include <linux/spinlock.h>
18 #include <linux/interrupt.h>
19 #include <linux/err.h>
20 #include <linux/amba/bus.h>
21 
22 #include <asm/io.h>
23 #include <asm/irq.h>
24 #include <asm/sizes.h>
25 
26 #include <sound/driver.h>
27 #include <sound/core.h>
28 #include <sound/initval.h>
29 #include <sound/ac97_codec.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 
33 #include "aaci.h"
34 #include "devdma.h"
35 
36 #define DRIVER_NAME	"aaci-pl041"
37 
38 /*
39  * PM support is not complete.  Turn it off.
40  */
41 #undef CONFIG_PM
42 
43 static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
44 {
45 	u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
46 
47 	/*
48 	 * Ensure that the slot 1/2 RX registers are empty.
49 	 */
50 	v = readl(aaci->base + AACI_SLFR);
51 	if (v & SLFR_2RXV)
52 		readl(aaci->base + AACI_SL2RX);
53 	if (v & SLFR_1RXV)
54 		readl(aaci->base + AACI_SL1RX);
55 
56 	writel(maincr, aaci->base + AACI_MAINCR);
57 }
58 
59 /*
60  * P29:
61  *  The recommended use of programming the external codec through slot 1
62  *  and slot 2 data is to use the channels during setup routines and the
63  *  slot register at any other time.  The data written into slot 1, slot 2
64  *  and slot 12 registers is transmitted only when their corresponding
65  *  SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
66  *  register.
67  */
68 static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
69 			    unsigned short val)
70 {
71 	struct aaci *aaci = ac97->private_data;
72 	u32 v;
73 	int timeout = 5000;
74 
75 	if (ac97->num >= 4)
76 		return;
77 
78 	mutex_lock(&aaci->ac97_sem);
79 
80 	aaci_ac97_select_codec(aaci, ac97);
81 
82 	/*
83 	 * P54: You must ensure that AACI_SL2TX is always written
84 	 * to, if required, before data is written to AACI_SL1TX.
85 	 */
86 	writel(val << 4, aaci->base + AACI_SL2TX);
87 	writel(reg << 12, aaci->base + AACI_SL1TX);
88 
89 	/*
90 	 * Wait for the transmission of both slots to complete.
91 	 */
92 	do {
93 		v = readl(aaci->base + AACI_SLFR);
94 	} while ((v & (SLFR_1TXB|SLFR_2TXB)) && timeout--);
95 
96 	if (!timeout)
97 		dev_err(&aaci->dev->dev,
98 			"timeout waiting for write to complete\n");
99 
100 	mutex_unlock(&aaci->ac97_sem);
101 }
102 
103 /*
104  * Read an AC'97 register.
105  */
106 static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
107 {
108 	struct aaci *aaci = ac97->private_data;
109 	u32 v;
110 	int timeout = 5000;
111 	int retries = 10;
112 
113 	if (ac97->num >= 4)
114 		return ~0;
115 
116 	mutex_lock(&aaci->ac97_sem);
117 
118 	aaci_ac97_select_codec(aaci, ac97);
119 
120 	/*
121 	 * Write the register address to slot 1.
122 	 */
123 	writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
124 
125 	/*
126 	 * Wait for the transmission to complete.
127 	 */
128 	do {
129 		v = readl(aaci->base + AACI_SLFR);
130 	} while ((v & SLFR_1TXB) && timeout--);
131 
132 	if (!timeout) {
133 		dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
134 		v = ~0;
135 		goto out;
136 	}
137 
138 	/*
139 	 * Give the AC'97 codec more than enough time
140 	 * to respond. (42us = ~2 frames at 48kHz.)
141 	 */
142 	udelay(42);
143 
144 	/*
145 	 * Wait for slot 2 to indicate data.
146 	 */
147 	timeout = 5000;
148 	do {
149 		cond_resched();
150 		v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
151 	} while ((v != (SLFR_1RXV|SLFR_2RXV)) && timeout--);
152 
153 	if (!timeout) {
154 		dev_err(&aaci->dev->dev, "timeout on RX valid\n");
155 		v = ~0;
156 		goto out;
157 	}
158 
159 	do {
160 		v = readl(aaci->base + AACI_SL1RX) >> 12;
161 		if (v == reg) {
162 			v = readl(aaci->base + AACI_SL2RX) >> 4;
163 			break;
164 		} else if (--retries) {
165 			dev_warn(&aaci->dev->dev,
166 				 "ac97 read back fail.  retry\n");
167 			continue;
168 		} else {
169 			dev_warn(&aaci->dev->dev,
170 				"wrong ac97 register read back (%x != %x)\n",
171 				v, reg);
172 			v = ~0;
173 		}
174 	} while (retries);
175  out:
176 	mutex_unlock(&aaci->ac97_sem);
177 	return v;
178 }
179 
180 static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun)
181 {
182 	u32 val;
183 	int timeout = 5000;
184 
185 	do {
186 		val = readl(aacirun->base + AACI_SR);
187 	} while (val & (SR_TXB|SR_RXB) && timeout--);
188 }
189 
190 
191 
192 /*
193  * Interrupt support.
194  */
195 static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
196 {
197 	if (mask & ISR_ORINTR) {
198 		dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
199 		writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
200 	}
201 
202 	if (mask & ISR_RXTOINTR) {
203 		dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
204 		writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
205 	}
206 
207 	if (mask & ISR_RXINTR) {
208 		struct aaci_runtime *aacirun = &aaci->capture;
209 		void *ptr;
210 
211 		if (!aacirun->substream || !aacirun->start) {
212 			dev_warn(&aaci->dev->dev, "RX interrupt???");
213 			writel(0, aacirun->base + AACI_IE);
214 			return;
215 		}
216 		ptr = aacirun->ptr;
217 
218 		do {
219 			unsigned int len = aacirun->fifosz;
220 			u32 val;
221 
222 			if (aacirun->bytes <= 0) {
223 				aacirun->bytes += aacirun->period;
224 				aacirun->ptr = ptr;
225 				spin_unlock(&aaci->lock);
226 				snd_pcm_period_elapsed(aacirun->substream);
227 				spin_lock(&aaci->lock);
228 			}
229 			if (!(aacirun->cr & CR_EN))
230 				break;
231 
232 			val = readl(aacirun->base + AACI_SR);
233 			if (!(val & SR_RXHF))
234 				break;
235 			if (!(val & SR_RXFF))
236 				len >>= 1;
237 
238 			aacirun->bytes -= len;
239 
240 			/* reading 16 bytes at a time */
241 			for( ; len > 0; len -= 16) {
242 				asm(
243 					"ldmia	%1, {r0, r1, r2, r3}\n\t"
244 					"stmia	%0!, {r0, r1, r2, r3}"
245 					: "+r" (ptr)
246 					: "r" (aacirun->fifo)
247 					: "r0", "r1", "r2", "r3", "cc");
248 
249 				if (ptr >= aacirun->end)
250 					ptr = aacirun->start;
251 			}
252 		} while(1);
253 		aacirun->ptr = ptr;
254 	}
255 
256 	if (mask & ISR_URINTR) {
257 		dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
258 		writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
259 	}
260 
261 	if (mask & ISR_TXINTR) {
262 		struct aaci_runtime *aacirun = &aaci->playback;
263 		void *ptr;
264 
265 		if (!aacirun->substream || !aacirun->start) {
266 			dev_warn(&aaci->dev->dev, "TX interrupt???");
267 			writel(0, aacirun->base + AACI_IE);
268 			return;
269 		}
270 
271 		ptr = aacirun->ptr;
272 		do {
273 			unsigned int len = aacirun->fifosz;
274 			u32 val;
275 
276 			if (aacirun->bytes <= 0) {
277 				aacirun->bytes += aacirun->period;
278 				aacirun->ptr = ptr;
279 				spin_unlock(&aaci->lock);
280 				snd_pcm_period_elapsed(aacirun->substream);
281 				spin_lock(&aaci->lock);
282 			}
283 			if (!(aacirun->cr & CR_EN))
284 				break;
285 
286 			val = readl(aacirun->base + AACI_SR);
287 			if (!(val & SR_TXHE))
288 				break;
289 			if (!(val & SR_TXFE))
290 				len >>= 1;
291 
292 			aacirun->bytes -= len;
293 
294 			/* writing 16 bytes at a time */
295 			for ( ; len > 0; len -= 16) {
296 				asm(
297 					"ldmia	%0!, {r0, r1, r2, r3}\n\t"
298 					"stmia	%1, {r0, r1, r2, r3}"
299 					: "+r" (ptr)
300 					: "r" (aacirun->fifo)
301 					: "r0", "r1", "r2", "r3", "cc");
302 
303 				if (ptr >= aacirun->end)
304 					ptr = aacirun->start;
305 			}
306 		} while (1);
307 
308 		aacirun->ptr = ptr;
309 	}
310 }
311 
312 static irqreturn_t aaci_irq(int irq, void *devid)
313 {
314 	struct aaci *aaci = devid;
315 	u32 mask;
316 	int i;
317 
318 	spin_lock(&aaci->lock);
319 	mask = readl(aaci->base + AACI_ALLINTS);
320 	if (mask) {
321 		u32 m = mask;
322 		for (i = 0; i < 4; i++, m >>= 7) {
323 			if (m & 0x7f) {
324 				aaci_fifo_irq(aaci, i, m);
325 			}
326 		}
327 	}
328 	spin_unlock(&aaci->lock);
329 
330 	return mask ? IRQ_HANDLED : IRQ_NONE;
331 }
332 
333 
334 
335 /*
336  * ALSA support.
337  */
338 
339 struct aaci_stream {
340 	unsigned char codec_idx;
341 	unsigned char rate_idx;
342 };
343 
344 static struct aaci_stream aaci_streams[] = {
345 	[ACSTREAM_FRONT] = {
346 		.codec_idx	= 0,
347 		.rate_idx	= AC97_RATES_FRONT_DAC,
348 	},
349 	[ACSTREAM_SURROUND] = {
350 		.codec_idx	= 0,
351 		.rate_idx	= AC97_RATES_SURR_DAC,
352 	},
353 	[ACSTREAM_LFE] = {
354 		.codec_idx	= 0,
355 		.rate_idx	= AC97_RATES_LFE_DAC,
356 	},
357 };
358 
359 static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid)
360 {
361 	struct aaci_stream *s = aaci_streams + streamid;
362 	return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx];
363 }
364 
365 static unsigned int rate_list[] = {
366 	5512, 8000, 11025, 16000, 22050, 32000, 44100,
367 	48000, 64000, 88200, 96000, 176400, 192000
368 };
369 
370 /*
371  * Double-rate rule: we can support double rate iff channels == 2
372  *  (unimplemented)
373  */
374 static int
375 aaci_rule_rate_by_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
376 {
377 	struct aaci *aaci = rule->private;
378 	unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512;
379 	struct snd_interval *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS);
380 
381 	switch (c->max) {
382 	case 6:
383 		rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE);
384 	case 4:
385 		rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND);
386 	case 2:
387 		rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT);
388 	}
389 
390 	return snd_interval_list(hw_param_interval(p, rule->var),
391 				 ARRAY_SIZE(rate_list), rate_list,
392 				 rate_mask);
393 }
394 
395 static struct snd_pcm_hardware aaci_hw_info = {
396 	.info			= SNDRV_PCM_INFO_MMAP |
397 				  SNDRV_PCM_INFO_MMAP_VALID |
398 				  SNDRV_PCM_INFO_INTERLEAVED |
399 				  SNDRV_PCM_INFO_BLOCK_TRANSFER |
400 				  SNDRV_PCM_INFO_RESUME,
401 
402 	/*
403 	 * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
404 	 * words.  It also doesn't support 12-bit at all.
405 	 */
406 	.formats		= SNDRV_PCM_FMTBIT_S16_LE,
407 
408 	/* should this be continuous or knot? */
409 	.rates			= SNDRV_PCM_RATE_CONTINUOUS,
410 	.rate_max		= 48000,
411 	.rate_min		= 4000,
412 	.channels_min		= 2,
413 	.channels_max		= 6,
414 	.buffer_bytes_max	= 64 * 1024,
415 	.period_bytes_min	= 256,
416 	.period_bytes_max	= PAGE_SIZE,
417 	.periods_min		= 4,
418 	.periods_max		= PAGE_SIZE / 16,
419 };
420 
421 static int __aaci_pcm_open(struct aaci *aaci,
422 			   struct snd_pcm_substream *substream,
423 			   struct aaci_runtime *aacirun)
424 {
425 	struct snd_pcm_runtime *runtime = substream->runtime;
426 	int ret;
427 
428 	aacirun->substream = substream;
429 	runtime->private_data = aacirun;
430 	runtime->hw = aaci_hw_info;
431 
432 	/*
433 	 * FIXME: ALSA specifies fifo_size in bytes.  If we're in normal
434 	 * mode, each 32-bit word contains one sample.  If we're in
435 	 * compact mode, each 32-bit word contains two samples, effectively
436 	 * halving the FIFO size.  However, we don't know for sure which
437 	 * we'll be using at this point.  We set this to the lower limit.
438 	 */
439 	runtime->hw.fifo_size = aaci->fifosize * 2;
440 
441 	/*
442 	 * Add rule describing hardware rate dependency
443 	 * on the number of channels.
444 	 */
445 	ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
446 				  aaci_rule_rate_by_channels, aaci,
447 				  SNDRV_PCM_HW_PARAM_CHANNELS,
448 				  SNDRV_PCM_HW_PARAM_RATE, -1);
449 	if (ret)
450 		goto out;
451 
452 	ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED,
453 			  DRIVER_NAME, aaci);
454 	if (ret)
455 		goto out;
456 
457 	return 0;
458 
459  out:
460 	return ret;
461 }
462 
463 
464 /*
465  * Common ALSA stuff
466  */
467 static int aaci_pcm_close(struct snd_pcm_substream *substream)
468 {
469 	struct aaci *aaci = substream->private_data;
470 	struct aaci_runtime *aacirun = substream->runtime->private_data;
471 
472 	WARN_ON(aacirun->cr & CR_EN);
473 
474 	aacirun->substream = NULL;
475 	free_irq(aaci->dev->irq[0], aaci);
476 
477 	return 0;
478 }
479 
480 static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
481 {
482 	struct aaci_runtime *aacirun = substream->runtime->private_data;
483 
484 	/*
485 	 * This must not be called with the device enabled.
486 	 */
487 	WARN_ON(aacirun->cr & CR_EN);
488 
489 	if (aacirun->pcm_open)
490 		snd_ac97_pcm_close(aacirun->pcm);
491 	aacirun->pcm_open = 0;
492 
493 	/*
494 	 * Clear out the DMA and any allocated buffers.
495 	 */
496 	devdma_hw_free(NULL, substream);
497 
498 	return 0;
499 }
500 
501 static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
502 			      struct aaci_runtime *aacirun,
503 			      struct snd_pcm_hw_params *params)
504 {
505 	int err;
506 
507 	aaci_pcm_hw_free(substream);
508 
509 	err = devdma_hw_alloc(NULL, substream,
510 			      params_buffer_bytes(params));
511 	if (err < 0)
512 		goto out;
513 
514 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
515 		err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
516 					params_channels(params),
517 					aacirun->pcm->r[0].slots);
518 	else
519 		err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
520 					params_channels(params),
521 					aacirun->pcm->r[1].slots);
522 
523 	if (err)
524 		goto out;
525 
526 	aacirun->pcm_open = 1;
527 
528  out:
529 	return err;
530 }
531 
532 static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
533 {
534 	struct snd_pcm_runtime *runtime = substream->runtime;
535 	struct aaci_runtime *aacirun = runtime->private_data;
536 
537 	aacirun->start	= (void *)runtime->dma_area;
538 	aacirun->end	= aacirun->start + runtime->dma_bytes;
539 	aacirun->ptr	= aacirun->start;
540 	aacirun->period	=
541 	aacirun->bytes	= frames_to_bytes(runtime, runtime->period_size);
542 
543 	return 0;
544 }
545 
546 static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
547 {
548 	struct snd_pcm_runtime *runtime = substream->runtime;
549 	struct aaci_runtime *aacirun = runtime->private_data;
550 	ssize_t bytes = aacirun->ptr - aacirun->start;
551 
552 	return bytes_to_frames(runtime, bytes);
553 }
554 
555 static int aaci_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma)
556 {
557 	return devdma_mmap(NULL, substream, vma);
558 }
559 
560 
561 /*
562  * Playback specific ALSA stuff
563  */
564 static const u32 channels_to_txmask[] = {
565 	[2] = CR_SL3 | CR_SL4,
566 	[4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
567 	[6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
568 };
569 
570 /*
571  * We can support two and four channel audio.  Unfortunately
572  * six channel audio requires a non-standard channel ordering:
573  *   2 -> FL(3), FR(4)
574  *   4 -> FL(3), FR(4), SL(7), SR(8)
575  *   6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
576  *        FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
577  * This requires an ALSA configuration file to correct.
578  */
579 static unsigned int channel_list[] = { 2, 4, 6 };
580 
581 static int
582 aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
583 {
584 	struct aaci *aaci = rule->private;
585 	unsigned int chan_mask = 1 << 0, slots;
586 
587 	/*
588 	 * pcms[0] is the our 5.1 PCM instance.
589 	 */
590 	slots = aaci->ac97_bus->pcms[0].r[0].slots;
591 	if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
592 		chan_mask |= 1 << 1;
593 		if (slots & (1 << AC97_SLOT_LFE))
594 			chan_mask |= 1 << 2;
595 	}
596 
597 	return snd_interval_list(hw_param_interval(p, rule->var),
598 				 ARRAY_SIZE(channel_list), channel_list,
599 				 chan_mask);
600 }
601 
602 static int aaci_pcm_open(struct snd_pcm_substream *substream)
603 {
604 	struct aaci *aaci = substream->private_data;
605 	int ret;
606 
607 	/*
608 	 * Add rule describing channel dependency.
609 	 */
610 	ret = snd_pcm_hw_rule_add(substream->runtime, 0,
611 				  SNDRV_PCM_HW_PARAM_CHANNELS,
612 				  aaci_rule_channels, aaci,
613 				  SNDRV_PCM_HW_PARAM_CHANNELS, -1);
614 	if (ret)
615 		return ret;
616 
617 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
618 		ret = __aaci_pcm_open(aaci, substream, &aaci->playback);
619 	} else {
620 		ret = __aaci_pcm_open(aaci, substream, &aaci->capture);
621 	}
622 	return ret;
623 }
624 
625 static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream,
626 				       struct snd_pcm_hw_params *params)
627 {
628 	struct aaci *aaci = substream->private_data;
629 	struct aaci_runtime *aacirun = substream->runtime->private_data;
630 	unsigned int channels = params_channels(params);
631 	int ret;
632 
633 	WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
634 		!channels_to_txmask[channels]);
635 
636 	ret = aaci_pcm_hw_params(substream, aacirun, params);
637 
638 	/*
639 	 * Enable FIFO, compact mode, 16 bits per sample.
640 	 * FIXME: double rate slots?
641 	 */
642 	if (ret >= 0) {
643 		aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
644 		aacirun->cr |= channels_to_txmask[channels];
645 
646 		aacirun->fifosz	= aaci->fifosize * 4;
647 		if (aacirun->cr & CR_COMPACT)
648 			aacirun->fifosz >>= 1;
649 	}
650 	return ret;
651 }
652 
653 static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
654 {
655 	u32 ie;
656 
657 	ie = readl(aacirun->base + AACI_IE);
658 	ie &= ~(IE_URIE|IE_TXIE);
659 	writel(ie, aacirun->base + AACI_IE);
660 	aacirun->cr &= ~CR_EN;
661 	aaci_chan_wait_ready(aacirun);
662 	writel(aacirun->cr, aacirun->base + AACI_TXCR);
663 }
664 
665 static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
666 {
667 	u32 ie;
668 
669 	aaci_chan_wait_ready(aacirun);
670 	aacirun->cr |= CR_EN;
671 
672 	ie = readl(aacirun->base + AACI_IE);
673 	ie |= IE_URIE | IE_TXIE;
674 	writel(ie, aacirun->base + AACI_IE);
675 	writel(aacirun->cr, aacirun->base + AACI_TXCR);
676 }
677 
678 static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
679 {
680 	struct aaci *aaci = substream->private_data;
681 	struct aaci_runtime *aacirun = substream->runtime->private_data;
682 	unsigned long flags;
683 	int ret = 0;
684 
685 	spin_lock_irqsave(&aaci->lock, flags);
686 	switch (cmd) {
687 	case SNDRV_PCM_TRIGGER_START:
688 		aaci_pcm_playback_start(aacirun);
689 		break;
690 
691 	case SNDRV_PCM_TRIGGER_RESUME:
692 		aaci_pcm_playback_start(aacirun);
693 		break;
694 
695 	case SNDRV_PCM_TRIGGER_STOP:
696 		aaci_pcm_playback_stop(aacirun);
697 		break;
698 
699 	case SNDRV_PCM_TRIGGER_SUSPEND:
700 		aaci_pcm_playback_stop(aacirun);
701 		break;
702 
703 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
704 		break;
705 
706 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
707 		break;
708 
709 	default:
710 		ret = -EINVAL;
711 	}
712 	spin_unlock_irqrestore(&aaci->lock, flags);
713 
714 	return ret;
715 }
716 
717 static struct snd_pcm_ops aaci_playback_ops = {
718 	.open		= aaci_pcm_open,
719 	.close		= aaci_pcm_close,
720 	.ioctl		= snd_pcm_lib_ioctl,
721 	.hw_params	= aaci_pcm_playback_hw_params,
722 	.hw_free	= aaci_pcm_hw_free,
723 	.prepare	= aaci_pcm_prepare,
724 	.trigger	= aaci_pcm_playback_trigger,
725 	.pointer	= aaci_pcm_pointer,
726 	.mmap		= aaci_pcm_mmap,
727 };
728 
729 static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream,
730 				      struct snd_pcm_hw_params *params)
731 {
732 	struct aaci *aaci = substream->private_data;
733 	struct aaci_runtime *aacirun = substream->runtime->private_data;
734 	int ret;
735 
736 	ret = aaci_pcm_hw_params(substream, aacirun, params);
737 
738 	if (ret >= 0) {
739 		aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
740 
741 		/* Line in record: slot 3 and 4 */
742 		aacirun->cr |= CR_SL3 | CR_SL4;
743 
744 		aacirun->fifosz = aaci->fifosize * 4;
745 
746 		if (aacirun->cr & CR_COMPACT)
747 			aacirun->fifosz >>= 1;
748 	}
749 	return ret;
750 }
751 
752 static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
753 {
754 	u32 ie;
755 
756 	aaci_chan_wait_ready(aacirun);
757 
758 	ie = readl(aacirun->base + AACI_IE);
759 	ie &= ~(IE_ORIE | IE_RXIE);
760 	writel(ie, aacirun->base+AACI_IE);
761 
762 	aacirun->cr &= ~CR_EN;
763 
764 	writel(aacirun->cr, aacirun->base + AACI_RXCR);
765 }
766 
767 static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
768 {
769 	u32 ie;
770 
771 	aaci_chan_wait_ready(aacirun);
772 
773 #ifdef DEBUG
774 	/* RX Timeout value: bits 28:17 in RXCR */
775 	aacirun->cr |= 0xf << 17;
776 #endif
777 
778 	aacirun->cr |= CR_EN;
779 	writel(aacirun->cr, aacirun->base + AACI_RXCR);
780 
781 	ie = readl(aacirun->base + AACI_IE);
782 	ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
783 	writel(ie, aacirun->base + AACI_IE);
784 }
785 
786 static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
787 {
788 	struct aaci *aaci = substream->private_data;
789 	struct aaci_runtime *aacirun = substream->runtime->private_data;
790 	unsigned long flags;
791 	int ret = 0;
792 
793 	spin_lock_irqsave(&aaci->lock, flags);
794 
795 	switch (cmd) {
796 	case SNDRV_PCM_TRIGGER_START:
797 		aaci_pcm_capture_start(aacirun);
798 		break;
799 
800 	case SNDRV_PCM_TRIGGER_RESUME:
801 		aaci_pcm_capture_start(aacirun);
802 		break;
803 
804 	case SNDRV_PCM_TRIGGER_STOP:
805 		aaci_pcm_capture_stop(aacirun);
806 		break;
807 
808 	case SNDRV_PCM_TRIGGER_SUSPEND:
809 		aaci_pcm_capture_stop(aacirun);
810 		break;
811 
812 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
813 		break;
814 
815 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
816 		break;
817 
818 	default:
819 		ret = -EINVAL;
820 	}
821 
822 	spin_unlock_irqrestore(&aaci->lock, flags);
823 
824 	return ret;
825 }
826 
827 static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
828 {
829 	struct snd_pcm_runtime *runtime = substream->runtime;
830 	struct aaci *aaci = substream->private_data;
831 
832 	aaci_pcm_prepare(substream);
833 
834 	/* allow changing of sample rate */
835 	aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
836 	aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
837 	aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
838 
839 	/* Record select: Mic: 0, Aux: 3, Line: 4 */
840 	aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
841 
842 	return 0;
843 }
844 
845 static struct snd_pcm_ops aaci_capture_ops = {
846 	.open		= aaci_pcm_open,
847 	.close		= aaci_pcm_close,
848 	.ioctl		= snd_pcm_lib_ioctl,
849 	.hw_params	= aaci_pcm_capture_hw_params,
850 	.hw_free	= aaci_pcm_hw_free,
851 	.prepare	= aaci_pcm_capture_prepare,
852 	.trigger	= aaci_pcm_capture_trigger,
853 	.pointer	= aaci_pcm_pointer,
854 	.mmap		= aaci_pcm_mmap,
855 };
856 
857 /*
858  * Power Management.
859  */
860 #ifdef CONFIG_PM
861 static int aaci_do_suspend(struct snd_card *card, unsigned int state)
862 {
863 	struct aaci *aaci = card->private_data;
864 	snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
865 	snd_pcm_suspend_all(aaci->pcm);
866 	return 0;
867 }
868 
869 static int aaci_do_resume(struct snd_card *card, unsigned int state)
870 {
871 	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
872 	return 0;
873 }
874 
875 static int aaci_suspend(struct amba_device *dev, pm_message_t state)
876 {
877 	struct snd_card *card = amba_get_drvdata(dev);
878 	return card ? aaci_do_suspend(card) : 0;
879 }
880 
881 static int aaci_resume(struct amba_device *dev)
882 {
883 	struct snd_card *card = amba_get_drvdata(dev);
884 	return card ? aaci_do_resume(card) : 0;
885 }
886 #else
887 #define aaci_do_suspend		NULL
888 #define aaci_do_resume		NULL
889 #define aaci_suspend		NULL
890 #define aaci_resume		NULL
891 #endif
892 
893 
894 static struct ac97_pcm ac97_defs[] __devinitdata = {
895 	[0] = {	/* Front PCM */
896 		.exclusive = 1,
897 		.r = {
898 			[0] = {
899 				.slots	= (1 << AC97_SLOT_PCM_LEFT) |
900 					  (1 << AC97_SLOT_PCM_RIGHT) |
901 					  (1 << AC97_SLOT_PCM_CENTER) |
902 					  (1 << AC97_SLOT_PCM_SLEFT) |
903 					  (1 << AC97_SLOT_PCM_SRIGHT) |
904 					  (1 << AC97_SLOT_LFE),
905 			},
906 		},
907 	},
908 	[1] = {	/* PCM in */
909 		.stream = 1,
910 		.exclusive = 1,
911 		.r = {
912 			[0] = {
913 				.slots	= (1 << AC97_SLOT_PCM_LEFT) |
914 					  (1 << AC97_SLOT_PCM_RIGHT),
915 			},
916 		},
917 	},
918 	[2] = {	/* Mic in */
919 		.stream = 1,
920 		.exclusive = 1,
921 		.r = {
922 			[0] = {
923 				.slots	= (1 << AC97_SLOT_MIC),
924 			},
925 		},
926 	}
927 };
928 
929 static struct snd_ac97_bus_ops aaci_bus_ops = {
930 	.write	= aaci_ac97_write,
931 	.read	= aaci_ac97_read,
932 };
933 
934 static int __devinit aaci_probe_ac97(struct aaci *aaci)
935 {
936 	struct snd_ac97_template ac97_template;
937 	struct snd_ac97_bus *ac97_bus;
938 	struct snd_ac97 *ac97;
939 	int ret;
940 
941 	/*
942 	 * Assert AACIRESET for 2us
943 	 */
944 	writel(0, aaci->base + AACI_RESET);
945 	udelay(2);
946 	writel(RESET_NRST, aaci->base + AACI_RESET);
947 
948 	/*
949 	 * Give the AC'97 codec more than enough time
950 	 * to wake up. (42us = ~2 frames at 48kHz.)
951 	 */
952 	udelay(42);
953 
954 	ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
955 	if (ret)
956 		goto out;
957 
958 	ac97_bus->clock = 48000;
959 	aaci->ac97_bus = ac97_bus;
960 
961 	memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
962 	ac97_template.private_data = aaci;
963 	ac97_template.num = 0;
964 	ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
965 
966 	ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
967 	if (ret)
968 		goto out;
969 	aaci->ac97 = ac97;
970 
971 	/*
972 	 * Disable AC97 PC Beep input on audio codecs.
973 	 */
974 	if (ac97_is_audio(ac97))
975 		snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
976 
977 	ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
978 	if (ret)
979 		goto out;
980 
981 	aaci->playback.pcm = &ac97_bus->pcms[0];
982 	aaci->capture.pcm  = &ac97_bus->pcms[1];
983 
984  out:
985 	return ret;
986 }
987 
988 static void aaci_free_card(struct snd_card *card)
989 {
990 	struct aaci *aaci = card->private_data;
991 	if (aaci->base)
992 		iounmap(aaci->base);
993 }
994 
995 static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
996 {
997 	struct aaci *aaci;
998 	struct snd_card *card;
999 
1000 	card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
1001 			    THIS_MODULE, sizeof(struct aaci));
1002 	if (card == NULL)
1003 		return ERR_PTR(-ENOMEM);
1004 
1005 	card->private_free = aaci_free_card;
1006 
1007 	strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
1008 	strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
1009 	snprintf(card->longname, sizeof(card->longname),
1010 		 "%s at 0x%016llx, irq %d",
1011 		 card->shortname, (unsigned long long)dev->res.start,
1012 		 dev->irq[0]);
1013 
1014 	aaci = card->private_data;
1015 	mutex_init(&aaci->ac97_sem);
1016 	spin_lock_init(&aaci->lock);
1017 	aaci->card = card;
1018 	aaci->dev = dev;
1019 
1020 	/* Set MAINCR to allow slot 1 and 2 data IO */
1021 	aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
1022 		       MAINCR_SL2RXEN | MAINCR_SL2TXEN;
1023 
1024 	return aaci;
1025 }
1026 
1027 static int __devinit aaci_init_pcm(struct aaci *aaci)
1028 {
1029 	struct snd_pcm *pcm;
1030 	int ret;
1031 
1032 	ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
1033 	if (ret == 0) {
1034 		aaci->pcm = pcm;
1035 		pcm->private_data = aaci;
1036 		pcm->info_flags = 0;
1037 
1038 		strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
1039 
1040 		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
1041 		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
1042 	}
1043 
1044 	return ret;
1045 }
1046 
1047 static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
1048 {
1049 	struct aaci_runtime *aacirun = &aaci->playback;
1050 	int i;
1051 
1052 	writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
1053 
1054 	for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
1055 		writel(0, aacirun->fifo);
1056 
1057 	writel(0, aacirun->base + AACI_TXCR);
1058 
1059 	/*
1060 	 * Re-initialise the AACI after the FIFO depth test, to
1061 	 * ensure that the FIFOs are empty.  Unfortunately, merely
1062 	 * disabling the channel doesn't clear the FIFO.
1063 	 */
1064 	writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
1065 	writel(aaci->maincr, aaci->base + AACI_MAINCR);
1066 
1067 	/*
1068 	 * If we hit 4096, we failed.  Go back to the specified
1069 	 * fifo depth.
1070 	 */
1071 	if (i == 4096)
1072 		i = 8;
1073 
1074 	return i;
1075 }
1076 
1077 static int __devinit aaci_probe(struct amba_device *dev, void *id)
1078 {
1079 	struct aaci *aaci;
1080 	int ret, i;
1081 
1082 	ret = amba_request_regions(dev, NULL);
1083 	if (ret)
1084 		return ret;
1085 
1086 	aaci = aaci_init_card(dev);
1087 	if (IS_ERR(aaci)) {
1088 		ret = PTR_ERR(aaci);
1089 		goto out;
1090 	}
1091 
1092 	aaci->base = ioremap(dev->res.start, SZ_4K);
1093 	if (!aaci->base) {
1094 		ret = -ENOMEM;
1095 		goto out;
1096 	}
1097 
1098 	/*
1099 	 * Playback uses AACI channel 0
1100 	 */
1101 	aaci->playback.base = aaci->base + AACI_CSCH1;
1102 	aaci->playback.fifo = aaci->base + AACI_DR1;
1103 
1104 	/*
1105 	 * Capture uses AACI channel 0
1106 	 */
1107 	aaci->capture.base = aaci->base + AACI_CSCH1;
1108 	aaci->capture.fifo = aaci->base + AACI_DR1;
1109 
1110 	for (i = 0; i < 4; i++) {
1111 		void __iomem *base = aaci->base + i * 0x14;
1112 
1113 		writel(0, base + AACI_IE);
1114 		writel(0, base + AACI_TXCR);
1115 		writel(0, base + AACI_RXCR);
1116 	}
1117 
1118 	writel(0x1fff, aaci->base + AACI_INTCLR);
1119 	writel(aaci->maincr, aaci->base + AACI_MAINCR);
1120 
1121 	ret = aaci_probe_ac97(aaci);
1122 	if (ret)
1123 		goto out;
1124 
1125 	/*
1126 	 * Size the FIFOs (must be multiple of 16).
1127 	 */
1128 	aaci->fifosize = aaci_size_fifo(aaci);
1129 	if (aaci->fifosize & 15) {
1130 		printk(KERN_WARNING "AACI: fifosize = %d not supported\n",
1131 		       aaci->fifosize);
1132 		ret = -ENODEV;
1133 		goto out;
1134 	}
1135 
1136 	ret = aaci_init_pcm(aaci);
1137 	if (ret)
1138 		goto out;
1139 
1140 	snd_card_set_dev(aaci->card, &dev->dev);
1141 
1142 	ret = snd_card_register(aaci->card);
1143 	if (ret == 0) {
1144 		dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
1145 			 aaci->fifosize);
1146 		amba_set_drvdata(dev, aaci->card);
1147 		return ret;
1148 	}
1149 
1150  out:
1151 	if (aaci)
1152 		snd_card_free(aaci->card);
1153 	amba_release_regions(dev);
1154 	return ret;
1155 }
1156 
1157 static int __devexit aaci_remove(struct amba_device *dev)
1158 {
1159 	struct snd_card *card = amba_get_drvdata(dev);
1160 
1161 	amba_set_drvdata(dev, NULL);
1162 
1163 	if (card) {
1164 		struct aaci *aaci = card->private_data;
1165 		writel(0, aaci->base + AACI_MAINCR);
1166 
1167 		snd_card_free(card);
1168 		amba_release_regions(dev);
1169 	}
1170 
1171 	return 0;
1172 }
1173 
1174 static struct amba_id aaci_ids[] = {
1175 	{
1176 		.id	= 0x00041041,
1177 		.mask	= 0x000fffff,
1178 	},
1179 	{ 0, 0 },
1180 };
1181 
1182 static struct amba_driver aaci_driver = {
1183 	.drv		= {
1184 		.name	= DRIVER_NAME,
1185 	},
1186 	.probe		= aaci_probe,
1187 	.remove		= __devexit_p(aaci_remove),
1188 	.suspend	= aaci_suspend,
1189 	.resume		= aaci_resume,
1190 	.id_table	= aaci_ids,
1191 };
1192 
1193 static int __init aaci_init(void)
1194 {
1195 	return amba_driver_register(&aaci_driver);
1196 }
1197 
1198 static void __exit aaci_exit(void)
1199 {
1200 	amba_driver_unregister(&aaci_driver);
1201 }
1202 
1203 module_init(aaci_init);
1204 module_exit(aaci_exit);
1205 
1206 MODULE_LICENSE("GPL");
1207 MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");
1208