1*a62f48deSStefan Roese/* 2*a62f48deSStefan Roese * Device Tree Source for AMCC Kilauea (405EX) 3*a62f48deSStefan Roese * 4*a62f48deSStefan Roese * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> 5*a62f48deSStefan Roese * 6*a62f48deSStefan Roese * This file is licensed under the terms of the GNU General Public 7*a62f48deSStefan Roese * License version 2. This program is licensed "as is" without 8*a62f48deSStefan Roese * any warranty of any kind, whether express or implied. 9*a62f48deSStefan Roese */ 10*a62f48deSStefan Roese 11*a62f48deSStefan Roese/ { 12*a62f48deSStefan Roese #address-cells = <1>; 13*a62f48deSStefan Roese #size-cells = <1>; 14*a62f48deSStefan Roese model = "amcc,kilauea"; 15*a62f48deSStefan Roese compatible = "amcc,kilauea"; 16*a62f48deSStefan Roese dcr-parent = <&/cpus/PowerPC,405EX@0>; 17*a62f48deSStefan Roese 18*a62f48deSStefan Roese cpus { 19*a62f48deSStefan Roese #address-cells = <1>; 20*a62f48deSStefan Roese #size-cells = <0>; 21*a62f48deSStefan Roese 22*a62f48deSStefan Roese PowerPC,405EX@0 { 23*a62f48deSStefan Roese device_type = "cpu"; 24*a62f48deSStefan Roese reg = <0>; 25*a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 26*a62f48deSStefan Roese timebase-frequency = <0>; /* Filled in by U-Boot */ 27*a62f48deSStefan Roese i-cache-line-size = <20>; 28*a62f48deSStefan Roese d-cache-line-size = <20>; 29*a62f48deSStefan Roese i-cache-size = <4000>; /* 16 kB */ 30*a62f48deSStefan Roese d-cache-size = <4000>; /* 16 kB */ 31*a62f48deSStefan Roese dcr-controller; 32*a62f48deSStefan Roese dcr-access-method = "native"; 33*a62f48deSStefan Roese }; 34*a62f48deSStefan Roese }; 35*a62f48deSStefan Roese 36*a62f48deSStefan Roese memory { 37*a62f48deSStefan Roese device_type = "memory"; 38*a62f48deSStefan Roese reg = <0 0>; /* Filled in by U-Boot */ 39*a62f48deSStefan Roese }; 40*a62f48deSStefan Roese 41*a62f48deSStefan Roese UIC0: interrupt-controller { 42*a62f48deSStefan Roese compatible = "ibm,uic-405ex", "ibm,uic"; 43*a62f48deSStefan Roese interrupt-controller; 44*a62f48deSStefan Roese cell-index = <0>; 45*a62f48deSStefan Roese dcr-reg = <0c0 009>; 46*a62f48deSStefan Roese #address-cells = <0>; 47*a62f48deSStefan Roese #size-cells = <0>; 48*a62f48deSStefan Roese #interrupt-cells = <2>; 49*a62f48deSStefan Roese }; 50*a62f48deSStefan Roese 51*a62f48deSStefan Roese UIC1: interrupt-controller1 { 52*a62f48deSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 53*a62f48deSStefan Roese interrupt-controller; 54*a62f48deSStefan Roese cell-index = <1>; 55*a62f48deSStefan Roese dcr-reg = <0d0 009>; 56*a62f48deSStefan Roese #address-cells = <0>; 57*a62f48deSStefan Roese #size-cells = <0>; 58*a62f48deSStefan Roese #interrupt-cells = <2>; 59*a62f48deSStefan Roese interrupts = <1e 4 1f 4>; /* cascade */ 60*a62f48deSStefan Roese interrupt-parent = <&UIC0>; 61*a62f48deSStefan Roese }; 62*a62f48deSStefan Roese 63*a62f48deSStefan Roese UIC2: interrupt-controller2 { 64*a62f48deSStefan Roese compatible = "ibm,uic-405ex","ibm,uic"; 65*a62f48deSStefan Roese interrupt-controller; 66*a62f48deSStefan Roese cell-index = <2>; 67*a62f48deSStefan Roese dcr-reg = <0e0 009>; 68*a62f48deSStefan Roese #address-cells = <0>; 69*a62f48deSStefan Roese #size-cells = <0>; 70*a62f48deSStefan Roese #interrupt-cells = <2>; 71*a62f48deSStefan Roese interrupts = <1c 4 1d 4>; /* cascade */ 72*a62f48deSStefan Roese interrupt-parent = <&UIC0>; 73*a62f48deSStefan Roese }; 74*a62f48deSStefan Roese 75*a62f48deSStefan Roese plb { 76*a62f48deSStefan Roese compatible = "ibm,plb-405ex", "ibm,plb4"; 77*a62f48deSStefan Roese #address-cells = <1>; 78*a62f48deSStefan Roese #size-cells = <1>; 79*a62f48deSStefan Roese ranges; 80*a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 81*a62f48deSStefan Roese 82*a62f48deSStefan Roese SDRAM0: memory-controller { 83*a62f48deSStefan Roese compatible = "ibm,sdram-405ex"; 84*a62f48deSStefan Roese dcr-reg = <010 2>; 85*a62f48deSStefan Roese }; 86*a62f48deSStefan Roese 87*a62f48deSStefan Roese MAL0: mcmal { 88*a62f48deSStefan Roese compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; 89*a62f48deSStefan Roese dcr-reg = <180 62>; 90*a62f48deSStefan Roese num-tx-chans = <2>; 91*a62f48deSStefan Roese num-rx-chans = <2>; 92*a62f48deSStefan Roese interrupt-parent = <&MAL0>; 93*a62f48deSStefan Roese interrupts = <0 1 2 3 4>; 94*a62f48deSStefan Roese #interrupt-cells = <1>; 95*a62f48deSStefan Roese #address-cells = <0>; 96*a62f48deSStefan Roese #size-cells = <0>; 97*a62f48deSStefan Roese interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 98*a62f48deSStefan Roese /*RXEOB*/ 1 &UIC0 b 4 99*a62f48deSStefan Roese /*SERR*/ 2 &UIC1 0 4 100*a62f48deSStefan Roese /*TXDE*/ 3 &UIC1 1 4 101*a62f48deSStefan Roese /*RXDE*/ 4 &UIC1 2 4>; 102*a62f48deSStefan Roese interrupt-map-mask = <ffffffff>; 103*a62f48deSStefan Roese }; 104*a62f48deSStefan Roese 105*a62f48deSStefan Roese POB0: opb { 106*a62f48deSStefan Roese compatible = "ibm,opb-405ex", "ibm,opb"; 107*a62f48deSStefan Roese #address-cells = <1>; 108*a62f48deSStefan Roese #size-cells = <1>; 109*a62f48deSStefan Roese ranges = <80000000 80000000 10000000 110*a62f48deSStefan Roese ef600000 ef600000 a00000 111*a62f48deSStefan Roese f0000000 f0000000 10000000>; 112*a62f48deSStefan Roese dcr-reg = <0a0 5>; 113*a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 114*a62f48deSStefan Roese 115*a62f48deSStefan Roese EBC0: ebc { 116*a62f48deSStefan Roese compatible = "ibm,ebc-405ex", "ibm,ebc"; 117*a62f48deSStefan Roese dcr-reg = <012 2>; 118*a62f48deSStefan Roese #address-cells = <2>; 119*a62f48deSStefan Roese #size-cells = <1>; 120*a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 121*a62f48deSStefan Roese /* ranges property is supplied by U-Boot */ 122*a62f48deSStefan Roese interrupts = <5 1>; 123*a62f48deSStefan Roese interrupt-parent = <&UIC1>; 124*a62f48deSStefan Roese 125*a62f48deSStefan Roese nor_flash@0,0 { 126*a62f48deSStefan Roese compatible = "amd,s29gl512n", "cfi-flash"; 127*a62f48deSStefan Roese bank-width = <2>; 128*a62f48deSStefan Roese reg = <0 000000 4000000>; 129*a62f48deSStefan Roese #address-cells = <1>; 130*a62f48deSStefan Roese #size-cells = <1>; 131*a62f48deSStefan Roese partition@0 { 132*a62f48deSStefan Roese label = "kernel"; 133*a62f48deSStefan Roese reg = <0 200000>; 134*a62f48deSStefan Roese }; 135*a62f48deSStefan Roese partition@200000 { 136*a62f48deSStefan Roese label = "root"; 137*a62f48deSStefan Roese reg = <200000 200000>; 138*a62f48deSStefan Roese }; 139*a62f48deSStefan Roese partition@400000 { 140*a62f48deSStefan Roese label = "user"; 141*a62f48deSStefan Roese reg = <400000 3b60000>; 142*a62f48deSStefan Roese }; 143*a62f48deSStefan Roese partition@3f60000 { 144*a62f48deSStefan Roese label = "env"; 145*a62f48deSStefan Roese reg = <3f60000 40000>; 146*a62f48deSStefan Roese }; 147*a62f48deSStefan Roese partition@3fa0000 { 148*a62f48deSStefan Roese label = "u-boot"; 149*a62f48deSStefan Roese reg = <3fa0000 60000>; 150*a62f48deSStefan Roese }; 151*a62f48deSStefan Roese }; 152*a62f48deSStefan Roese }; 153*a62f48deSStefan Roese 154*a62f48deSStefan Roese UART0: serial@ef600200 { 155*a62f48deSStefan Roese device_type = "serial"; 156*a62f48deSStefan Roese compatible = "ns16550"; 157*a62f48deSStefan Roese reg = <ef600200 8>; 158*a62f48deSStefan Roese virtual-reg = <ef600200>; 159*a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 160*a62f48deSStefan Roese current-speed = <0>; 161*a62f48deSStefan Roese interrupt-parent = <&UIC0>; 162*a62f48deSStefan Roese interrupts = <1a 4>; 163*a62f48deSStefan Roese }; 164*a62f48deSStefan Roese 165*a62f48deSStefan Roese UART1: serial@ef600300 { 166*a62f48deSStefan Roese device_type = "serial"; 167*a62f48deSStefan Roese compatible = "ns16550"; 168*a62f48deSStefan Roese reg = <ef600300 8>; 169*a62f48deSStefan Roese virtual-reg = <ef600300>; 170*a62f48deSStefan Roese clock-frequency = <0>; /* Filled in by U-Boot */ 171*a62f48deSStefan Roese current-speed = <0>; 172*a62f48deSStefan Roese interrupt-parent = <&UIC0>; 173*a62f48deSStefan Roese interrupts = <1 4>; 174*a62f48deSStefan Roese }; 175*a62f48deSStefan Roese 176*a62f48deSStefan Roese IIC0: i2c@ef600400 { 177*a62f48deSStefan Roese device_type = "i2c"; 178*a62f48deSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 179*a62f48deSStefan Roese reg = <ef600400 14>; 180*a62f48deSStefan Roese interrupt-parent = <&UIC0>; 181*a62f48deSStefan Roese interrupts = <2 4>; 182*a62f48deSStefan Roese }; 183*a62f48deSStefan Roese 184*a62f48deSStefan Roese IIC1: i2c@ef600500 { 185*a62f48deSStefan Roese device_type = "i2c"; 186*a62f48deSStefan Roese compatible = "ibm,iic-405ex", "ibm,iic"; 187*a62f48deSStefan Roese reg = <ef600500 14>; 188*a62f48deSStefan Roese interrupt-parent = <&UIC0>; 189*a62f48deSStefan Roese interrupts = <7 4>; 190*a62f48deSStefan Roese }; 191*a62f48deSStefan Roese 192*a62f48deSStefan Roese 193*a62f48deSStefan Roese RGMII0: emac-rgmii@ef600b00 { 194*a62f48deSStefan Roese device_type = "rgmii-interface"; 195*a62f48deSStefan Roese compatible = "ibm,rgmii-405ex", "ibm,rgmii"; 196*a62f48deSStefan Roese reg = <ef600b00 104>; 197*a62f48deSStefan Roese }; 198*a62f48deSStefan Roese 199*a62f48deSStefan Roese EMAC0: ethernet@ef600900 { 200*a62f48deSStefan Roese linux,network-index = <0>; 201*a62f48deSStefan Roese device_type = "network"; 202*a62f48deSStefan Roese compatible = "ibm,emac-405ex", "ibm,emac4"; 203*a62f48deSStefan Roese interrupt-parent = <&EMAC0>; 204*a62f48deSStefan Roese interrupts = <0 1>; 205*a62f48deSStefan Roese #interrupt-cells = <1>; 206*a62f48deSStefan Roese #address-cells = <0>; 207*a62f48deSStefan Roese #size-cells = <0>; 208*a62f48deSStefan Roese interrupt-map = </*Status*/ 0 &UIC0 18 4 209*a62f48deSStefan Roese /*Wake*/ 1 &UIC1 1d 4>; 210*a62f48deSStefan Roese reg = <ef600900 70>; 211*a62f48deSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 212*a62f48deSStefan Roese mal-device = <&MAL0>; 213*a62f48deSStefan Roese mal-tx-channel = <0>; 214*a62f48deSStefan Roese mal-rx-channel = <0>; 215*a62f48deSStefan Roese cell-index = <0>; 216*a62f48deSStefan Roese max-frame-size = <5dc>; 217*a62f48deSStefan Roese rx-fifo-size = <1000>; 218*a62f48deSStefan Roese tx-fifo-size = <800>; 219*a62f48deSStefan Roese phy-mode = "rgmii"; 220*a62f48deSStefan Roese phy-map = <00000000>; 221*a62f48deSStefan Roese rgmii-device = <&RGMII0>; 222*a62f48deSStefan Roese rgmii-channel = <0>; 223*a62f48deSStefan Roese }; 224*a62f48deSStefan Roese 225*a62f48deSStefan Roese EMAC1: ethernet@ef600a00 { 226*a62f48deSStefan Roese linux,network-index = <1>; 227*a62f48deSStefan Roese device_type = "network"; 228*a62f48deSStefan Roese compatible = "ibm,emac-405ex", "ibm,emac4"; 229*a62f48deSStefan Roese interrupt-parent = <&EMAC1>; 230*a62f48deSStefan Roese interrupts = <0 1>; 231*a62f48deSStefan Roese #interrupt-cells = <1>; 232*a62f48deSStefan Roese #address-cells = <0>; 233*a62f48deSStefan Roese #size-cells = <0>; 234*a62f48deSStefan Roese interrupt-map = </*Status*/ 0 &UIC0 19 4 235*a62f48deSStefan Roese /*Wake*/ 1 &UIC1 1f 4>; 236*a62f48deSStefan Roese reg = <ef600a00 70>; 237*a62f48deSStefan Roese local-mac-address = [000000000000]; /* Filled in by U-Boot */ 238*a62f48deSStefan Roese mal-device = <&MAL0>; 239*a62f48deSStefan Roese mal-tx-channel = <1>; 240*a62f48deSStefan Roese mal-rx-channel = <1>; 241*a62f48deSStefan Roese cell-index = <1>; 242*a62f48deSStefan Roese max-frame-size = <5dc>; 243*a62f48deSStefan Roese rx-fifo-size = <1000>; 244*a62f48deSStefan Roese tx-fifo-size = <800>; 245*a62f48deSStefan Roese phy-mode = "rgmii"; 246*a62f48deSStefan Roese phy-map = <00000000>; 247*a62f48deSStefan Roese rgmii-device = <&RGMII0>; 248*a62f48deSStefan Roese rgmii-channel = <1>; 249*a62f48deSStefan Roese }; 250*a62f48deSStefan Roese }; 251*a62f48deSStefan Roese }; 252*a62f48deSStefan Roese}; 253