1*8cbc5d2fSElaine Zhang /* SPDX-License-Identifier: GPL-2.0 */ 2*8cbc5d2fSElaine Zhang #ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ 3*8cbc5d2fSElaine Zhang #define __DT_BINDINGS_POWER_RK3568_POWER_H__ 4*8cbc5d2fSElaine Zhang 5*8cbc5d2fSElaine Zhang /* VD_CORE */ 6*8cbc5d2fSElaine Zhang #define RK3568_PD_CPU_0 0 7*8cbc5d2fSElaine Zhang #define RK3568_PD_CPU_1 1 8*8cbc5d2fSElaine Zhang #define RK3568_PD_CPU_2 2 9*8cbc5d2fSElaine Zhang #define RK3568_PD_CPU_3 3 10*8cbc5d2fSElaine Zhang #define RK3568_PD_CORE_ALIVE 4 11*8cbc5d2fSElaine Zhang 12*8cbc5d2fSElaine Zhang /* VD_PMU */ 13*8cbc5d2fSElaine Zhang #define RK3568_PD_PMU 5 14*8cbc5d2fSElaine Zhang 15*8cbc5d2fSElaine Zhang /* VD_NPU */ 16*8cbc5d2fSElaine Zhang #define RK3568_PD_NPU 6 17*8cbc5d2fSElaine Zhang 18*8cbc5d2fSElaine Zhang /* VD_GPU */ 19*8cbc5d2fSElaine Zhang #define RK3568_PD_GPU 7 20*8cbc5d2fSElaine Zhang 21*8cbc5d2fSElaine Zhang /* VD_LOGIC */ 22*8cbc5d2fSElaine Zhang #define RK3568_PD_VI 8 23*8cbc5d2fSElaine Zhang #define RK3568_PD_VO 9 24*8cbc5d2fSElaine Zhang #define RK3568_PD_RGA 10 25*8cbc5d2fSElaine Zhang #define RK3568_PD_VPU 11 26*8cbc5d2fSElaine Zhang #define RK3568_PD_CENTER 12 27*8cbc5d2fSElaine Zhang #define RK3568_PD_RKVDEC 13 28*8cbc5d2fSElaine Zhang #define RK3568_PD_RKVENC 14 29*8cbc5d2fSElaine Zhang #define RK3568_PD_PIPE 15 30*8cbc5d2fSElaine Zhang #define RK3568_PD_LOGIC_ALIVE 16 31*8cbc5d2fSElaine Zhang 32*8cbc5d2fSElaine Zhang #endif 33