1*355f9e64STakeshi Kihara /* SPDX-License-Identifier: GPL-2.0 */ 2*355f9e64STakeshi Kihara /* 3*355f9e64STakeshi Kihara * Copyright (C) 2018 Renesas Electronics Corp. 4*355f9e64STakeshi Kihara */ 5*355f9e64STakeshi Kihara #ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__ 6*355f9e64STakeshi Kihara #define __DT_BINDINGS_POWER_R8A77990_SYSC_H__ 7*355f9e64STakeshi Kihara 8*355f9e64STakeshi Kihara /* 9*355f9e64STakeshi Kihara * These power domain indices match the numbers of the interrupt bits 10*355f9e64STakeshi Kihara * representing the power areas in the various Interrupt Registers 11*355f9e64STakeshi Kihara * (e.g. SYSCISR, Interrupt Status Register) 12*355f9e64STakeshi Kihara */ 13*355f9e64STakeshi Kihara 14*355f9e64STakeshi Kihara #define R8A77990_PD_CA53_CPU0 5 15*355f9e64STakeshi Kihara #define R8A77990_PD_CA53_CPU1 6 16*355f9e64STakeshi Kihara #define R8A77990_PD_CR7 13 17*355f9e64STakeshi Kihara #define R8A77990_PD_A3VC 14 18*355f9e64STakeshi Kihara #define R8A77990_PD_3DG_A 17 19*355f9e64STakeshi Kihara #define R8A77990_PD_3DG_B 18 20*355f9e64STakeshi Kihara #define R8A77990_PD_CA53_SCU 21 21*355f9e64STakeshi Kihara #define R8A77990_PD_A2VC1 26 22*355f9e64STakeshi Kihara 23*355f9e64STakeshi Kihara /* Always-on power area */ 24*355f9e64STakeshi Kihara #define R8A77990_PD_ALWAYS_ON 32 25*355f9e64STakeshi Kihara 26*355f9e64STakeshi Kihara #endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */ 27