1*a527709bSJacopo Mondi /* SPDX-License-Identifier: GPL-2.0 */ 2*a527709bSJacopo Mondi /* 3*a527709bSJacopo Mondi * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> 4*a527709bSJacopo Mondi * Copyright (C) 2016 Glider bvba 5*a527709bSJacopo Mondi */ 6*a527709bSJacopo Mondi 7*a527709bSJacopo Mondi #ifndef __DT_BINDINGS_POWER_R8A77965_SYSC_H__ 8*a527709bSJacopo Mondi #define __DT_BINDINGS_POWER_R8A77965_SYSC_H__ 9*a527709bSJacopo Mondi 10*a527709bSJacopo Mondi /* 11*a527709bSJacopo Mondi * These power domain indices match the numbers of the interrupt bits 12*a527709bSJacopo Mondi * representing the power areas in the various Interrupt Registers 13*a527709bSJacopo Mondi * (e.g. SYSCISR, Interrupt Status Register) 14*a527709bSJacopo Mondi */ 15*a527709bSJacopo Mondi 16*a527709bSJacopo Mondi #define R8A77965_PD_CA57_CPU0 0 17*a527709bSJacopo Mondi #define R8A77965_PD_CA57_CPU1 1 18*a527709bSJacopo Mondi #define R8A77965_PD_A3VP 9 19*a527709bSJacopo Mondi #define R8A77965_PD_CA57_SCU 12 20*a527709bSJacopo Mondi #define R8A77965_PD_CR7 13 21*a527709bSJacopo Mondi #define R8A77965_PD_A3VC 14 22*a527709bSJacopo Mondi #define R8A77965_PD_3DG_A 17 23*a527709bSJacopo Mondi #define R8A77965_PD_3DG_B 18 24*a527709bSJacopo Mondi #define R8A77965_PD_A2VC1 26 25*a527709bSJacopo Mondi 26*a527709bSJacopo Mondi /* Always-on power area */ 27*a527709bSJacopo Mondi #define R8A77965_PD_ALWAYS_ON 32 28*a527709bSJacopo Mondi 29*a527709bSJacopo Mondi #endif /* __DT_BINDINGS_POWER_R8A77965_SYSC_H__ */ 30