xref: /openbmc/linux/scripts/dtc/include-prefixes/dt-bindings/pinctrl/dra.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
26e58b8f1SR Sricharan /*
36e58b8f1SR Sricharan  * This header provides constants for DRA pinctrl bindings.
46e58b8f1SR Sricharan  *
56e58b8f1SR Sricharan  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
66e58b8f1SR Sricharan  * Author: Rajendra Nayak <rnayak@ti.com>
76e58b8f1SR Sricharan  */
86e58b8f1SR Sricharan 
96e58b8f1SR Sricharan #ifndef _DT_BINDINGS_PINCTRL_DRA_H
106e58b8f1SR Sricharan #define _DT_BINDINGS_PINCTRL_DRA_H
116e58b8f1SR Sricharan 
126e58b8f1SR Sricharan /* DRA7 mux mode options for each pin. See TRM for options */
136e58b8f1SR Sricharan #define MUX_MODE0	0x0
146e58b8f1SR Sricharan #define MUX_MODE1	0x1
156e58b8f1SR Sricharan #define MUX_MODE2	0x2
166e58b8f1SR Sricharan #define MUX_MODE3	0x3
176e58b8f1SR Sricharan #define MUX_MODE4	0x4
186e58b8f1SR Sricharan #define MUX_MODE5	0x5
196e58b8f1SR Sricharan #define MUX_MODE6	0x6
206e58b8f1SR Sricharan #define MUX_MODE7	0x7
216e58b8f1SR Sricharan #define MUX_MODE8	0x8
226e58b8f1SR Sricharan #define MUX_MODE9	0x9
236e58b8f1SR Sricharan #define MUX_MODE10	0xa
246e58b8f1SR Sricharan #define MUX_MODE11	0xb
256e58b8f1SR Sricharan #define MUX_MODE12	0xc
266e58b8f1SR Sricharan #define MUX_MODE13	0xd
276e58b8f1SR Sricharan #define MUX_MODE14	0xe
286e58b8f1SR Sricharan #define MUX_MODE15	0xf
296e58b8f1SR Sricharan 
30601b29aaSNishanth Menon /* Certain pins need virtual mode, but note: they may glitch */
31601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE0	(MODE_SELECT | (0x0 << 4))
32601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE1	(MODE_SELECT | (0x1 << 4))
33601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE2	(MODE_SELECT | (0x2 << 4))
34601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE3	(MODE_SELECT | (0x3 << 4))
35601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE4	(MODE_SELECT | (0x4 << 4))
36601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE5	(MODE_SELECT | (0x5 << 4))
37601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE6	(MODE_SELECT | (0x6 << 4))
38601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE7	(MODE_SELECT | (0x7 << 4))
39601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE8	(MODE_SELECT | (0x8 << 4))
40601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE9	(MODE_SELECT | (0x9 << 4))
41601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE10	(MODE_SELECT | (0xa << 4))
42601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE11	(MODE_SELECT | (0xb << 4))
43601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE12	(MODE_SELECT | (0xc << 4))
44601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE13	(MODE_SELECT | (0xd << 4))
45601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE14	(MODE_SELECT | (0xe << 4))
46601b29aaSNishanth Menon #define MUX_VIRTUAL_MODE15	(MODE_SELECT | (0xf << 4))
47601b29aaSNishanth Menon 
48601b29aaSNishanth Menon #define MODE_SELECT		(1 << 8)
49601b29aaSNishanth Menon 
5023d9cec0SNishanth Menon #define PULL_ENA		(0 << 16)
5123d9cec0SNishanth Menon #define PULL_DIS		(1 << 16)
526e58b8f1SR Sricharan #define PULL_UP			(1 << 17)
536e58b8f1SR Sricharan #define INPUT_EN		(1 << 18)
546e58b8f1SR Sricharan #define SLEWCONTROL		(1 << 19)
556e58b8f1SR Sricharan #define WAKEUP_EN		(1 << 24)
566e58b8f1SR Sricharan #define WAKEUP_EVENT		(1 << 25)
576e58b8f1SR Sricharan 
586e58b8f1SR Sricharan /* Active pin states */
5923d9cec0SNishanth Menon #define PIN_OUTPUT		(0 | PULL_DIS)
6073b3a665SRoger Quadros #define PIN_OUTPUT_PULLUP	(PULL_UP)
6173b3a665SRoger Quadros #define PIN_OUTPUT_PULLDOWN	(0)
6223d9cec0SNishanth Menon #define PIN_INPUT		(INPUT_EN | PULL_DIS)
636e58b8f1SR Sricharan #define PIN_INPUT_SLEW		(INPUT_EN | SLEWCONTROL)
646e58b8f1SR Sricharan #define PIN_INPUT_PULLUP	(PULL_ENA | INPUT_EN | PULL_UP)
656e58b8f1SR Sricharan #define PIN_INPUT_PULLDOWN	(PULL_ENA | INPUT_EN)
666e58b8f1SR Sricharan 
67fc63efdfSJavier Martinez Canillas /*
68fc63efdfSJavier Martinez Canillas  * Macro to allow using the absolute physical address instead of the
69fc63efdfSJavier Martinez Canillas  * padconf registers instead of the offset from padconf base.
70fc63efdfSJavier Martinez Canillas  */
71fc63efdfSJavier Martinez Canillas #define DRA7XX_CORE_IOPAD(pa, val)	(((pa) & 0xffff) - 0x3400) (val)
72fc63efdfSJavier Martinez Canillas 
73eba6130bSTony Lindgren /* DRA7 IODELAY configuration parameters */
74eba6130bSTony Lindgren #define A_DELAY_PS(val)			((val) & 0xffff)
75eba6130bSTony Lindgren #define G_DELAY_PS(val)			((val) & 0xffff)
766e58b8f1SR Sricharan #endif
776e58b8f1SR Sricharan 
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