1*b9890054S周琰杰 (Zhou Yanjie) /* SPDX-License-Identifier: GPL-2.0-only */ 2*b9890054S周琰杰 (Zhou Yanjie) /* 3*b9890054S周琰杰 (Zhou Yanjie) * This header provides macros for X1830 DMA bindings. 4*b9890054S周琰杰 (Zhou Yanjie) * 5*b9890054S周琰杰 (Zhou Yanjie) * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 6*b9890054S周琰杰 (Zhou Yanjie) */ 7*b9890054S周琰杰 (Zhou Yanjie) 8*b9890054S周琰杰 (Zhou Yanjie) #ifndef __DT_BINDINGS_DMA_X1830_DMA_H__ 9*b9890054S周琰杰 (Zhou Yanjie) #define __DT_BINDINGS_DMA_X1830_DMA_H__ 10*b9890054S周琰杰 (Zhou Yanjie) 11*b9890054S周琰杰 (Zhou Yanjie) /* 12*b9890054S周琰杰 (Zhou Yanjie) * Request type numbers for the X1830 DMA controller (written to the DRTn 13*b9890054S周琰杰 (Zhou Yanjie) * register for the channel). 14*b9890054S周琰杰 (Zhou Yanjie) */ 15*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_I2S0_TX 0x6 16*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_I2S0_RX 0x7 17*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_AUTO 0x8 18*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_SADC_RX 0x9 19*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_UART1_TX 0x12 20*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_UART1_RX 0x13 21*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_UART0_TX 0x14 22*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_UART0_RX 0x15 23*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_SSI0_TX 0x16 24*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_SSI0_RX 0x17 25*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_SSI1_TX 0x18 26*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_SSI1_RX 0x19 27*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_MSC0_TX 0x1a 28*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_MSC0_RX 0x1b 29*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_MSC1_TX 0x1c 30*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_MSC1_RX 0x1d 31*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_DMIC_RX 0x21 32*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_SMB0_TX 0x24 33*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_SMB0_RX 0x25 34*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_SMB1_TX 0x26 35*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_SMB1_RX 0x27 36*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_DES_TX 0x2e 37*b9890054S周琰杰 (Zhou Yanjie) #define X1830_DMA_DES_RX 0x2f 38*b9890054S周琰杰 (Zhou Yanjie) 39*b9890054S周琰杰 (Zhou Yanjie) #endif /* __DT_BINDINGS_DMA_X1830_DMA_H__ */ 40