1*0c94efabSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2ca79522cSLudovic Desroches /* 3ca79522cSLudovic Desroches * This header provides macros for at91 dma bindings. 4ca79522cSLudovic Desroches * 5ca79522cSLudovic Desroches * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com> 6ca79522cSLudovic Desroches */ 7ca79522cSLudovic Desroches 8ca79522cSLudovic Desroches #ifndef __DT_BINDINGS_AT91_DMA_H__ 9ca79522cSLudovic Desroches #define __DT_BINDINGS_AT91_DMA_H__ 10ca79522cSLudovic Desroches 11e1f7c9eeSLudovic Desroches /* ---------- HDMAC ---------- */ 12e1f7c9eeSLudovic Desroches 13ca79522cSLudovic Desroches /* 14ca79522cSLudovic Desroches * Source and/or destination peripheral ID 15ca79522cSLudovic Desroches */ 16ca79522cSLudovic Desroches #define AT91_DMA_CFG_PER_ID_MASK (0xff) 17ca79522cSLudovic Desroches #define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) 18ca79522cSLudovic Desroches 19ca79522cSLudovic Desroches /* 20ca79522cSLudovic Desroches * FIFO configuration: it defines when a request is serviced. 21ca79522cSLudovic Desroches */ 22ca79522cSLudovic Desroches #define AT91_DMA_CFG_FIFOCFG_OFFSET (8) 23ca79522cSLudovic Desroches #define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) 24ca79522cSLudovic Desroches #define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ 25ca79522cSLudovic Desroches #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ 26ca79522cSLudovic Desroches #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ 27ca79522cSLudovic Desroches 28e1f7c9eeSLudovic Desroches 29e1f7c9eeSLudovic Desroches /* ---------- XDMAC ---------- */ 30e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_MEM_IF_MASK (0x1) 31e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_MEM_IF_OFFSET (13) 32e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ 33e1f7c9eeSLudovic Desroches << AT91_XDMAC_DT_MEM_IF_OFFSET) 34e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ 35e1f7c9eeSLudovic Desroches & AT91_XDMAC_DT_MEM_IF_MASK) 36e1f7c9eeSLudovic Desroches 37e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_PER_IF_MASK (0x1) 38e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_PER_IF_OFFSET (14) 39e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ 40e1f7c9eeSLudovic Desroches << AT91_XDMAC_DT_PER_IF_OFFSET) 41e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ 42e1f7c9eeSLudovic Desroches & AT91_XDMAC_DT_PER_IF_MASK) 43e1f7c9eeSLudovic Desroches 44e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_PERID_MASK (0x7f) 45e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_PERID_OFFSET (24) 46e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ 47e1f7c9eeSLudovic Desroches << AT91_XDMAC_DT_PERID_OFFSET) 48e1f7c9eeSLudovic Desroches #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ 49e1f7c9eeSLudovic Desroches & AT91_XDMAC_DT_PERID_MASK) 50e1f7c9eeSLudovic Desroches 51ca79522cSLudovic Desroches #endif /* __DT_BINDINGS_AT91_DMA_H__ */ 52