1*8adea9b9SFabien Parent /* SPDX-License-Identifier: GPL-2.0 */ 2*8adea9b9SFabien Parent /* 3*8adea9b9SFabien Parent * Copyright (c) 2020 MediaTek Inc. 4*8adea9b9SFabien Parent * Copyright (c) 2020 BayLibre, SAS. 5*8adea9b9SFabien Parent * Author: James Liao <jamesjj.liao@mediatek.com> 6*8adea9b9SFabien Parent * Fabien Parent <fparent@baylibre.com> 7*8adea9b9SFabien Parent */ 8*8adea9b9SFabien Parent 9*8adea9b9SFabien Parent #ifndef _DT_BINDINGS_CLK_MT8167_H 10*8adea9b9SFabien Parent #define _DT_BINDINGS_CLK_MT8167_H 11*8adea9b9SFabien Parent 12*8adea9b9SFabien Parent /* MT8167 is based on MT8516 */ 13*8adea9b9SFabien Parent #include <dt-bindings/clock/mt8516-clk.h> 14*8adea9b9SFabien Parent 15*8adea9b9SFabien Parent /* APMIXEDSYS */ 16*8adea9b9SFabien Parent 17*8adea9b9SFabien Parent #define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0) 18*8adea9b9SFabien Parent #define CLK_APMIXED_LVDSPLL (CLK_APMIXED_NR_CLK + 1) 19*8adea9b9SFabien Parent #define CLK_APMIXED_HDMI_REF (CLK_APMIXED_NR_CLK + 2) 20*8adea9b9SFabien Parent #define MT8167_CLK_APMIXED_NR_CLK (CLK_APMIXED_NR_CLK + 3) 21*8adea9b9SFabien Parent 22*8adea9b9SFabien Parent /* TOPCKGEN */ 23*8adea9b9SFabien Parent 24*8adea9b9SFabien Parent #define CLK_TOP_DSI0_LNTC_DSICK (CLK_TOP_NR_CLK + 0) 25*8adea9b9SFabien Parent #define CLK_TOP_VPLL_DPIX (CLK_TOP_NR_CLK + 1) 26*8adea9b9SFabien Parent #define CLK_TOP_LVDSTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 2) 27*8adea9b9SFabien Parent #define CLK_TOP_HDMTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 3) 28*8adea9b9SFabien Parent #define CLK_TOP_LVDSPLL (CLK_TOP_NR_CLK + 4) 29*8adea9b9SFabien Parent #define CLK_TOP_LVDSPLL_D2 (CLK_TOP_NR_CLK + 5) 30*8adea9b9SFabien Parent #define CLK_TOP_LVDSPLL_D4 (CLK_TOP_NR_CLK + 6) 31*8adea9b9SFabien Parent #define CLK_TOP_LVDSPLL_D8 (CLK_TOP_NR_CLK + 7) 32*8adea9b9SFabien Parent #define CLK_TOP_MIPI_26M (CLK_TOP_NR_CLK + 8) 33*8adea9b9SFabien Parent #define CLK_TOP_TVDPLL (CLK_TOP_NR_CLK + 9) 34*8adea9b9SFabien Parent #define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10) 35*8adea9b9SFabien Parent #define CLK_TOP_TVDPLL_D4 (CLK_TOP_NR_CLK + 11) 36*8adea9b9SFabien Parent #define CLK_TOP_TVDPLL_D8 (CLK_TOP_NR_CLK + 12) 37*8adea9b9SFabien Parent #define CLK_TOP_TVDPLL_D16 (CLK_TOP_NR_CLK + 13) 38*8adea9b9SFabien Parent #define CLK_TOP_PWM_MM (CLK_TOP_NR_CLK + 14) 39*8adea9b9SFabien Parent #define CLK_TOP_CAM_MM (CLK_TOP_NR_CLK + 15) 40*8adea9b9SFabien Parent #define CLK_TOP_MFG_MM (CLK_TOP_NR_CLK + 16) 41*8adea9b9SFabien Parent #define CLK_TOP_SPM_52M (CLK_TOP_NR_CLK + 17) 42*8adea9b9SFabien Parent #define CLK_TOP_MIPI_26M_DBG (CLK_TOP_NR_CLK + 18) 43*8adea9b9SFabien Parent #define CLK_TOP_SCAM_MM (CLK_TOP_NR_CLK + 19) 44*8adea9b9SFabien Parent #define CLK_TOP_SMI_MM (CLK_TOP_NR_CLK + 20) 45*8adea9b9SFabien Parent #define CLK_TOP_26M_HDMI_SIFM (CLK_TOP_NR_CLK + 21) 46*8adea9b9SFabien Parent #define CLK_TOP_26M_CEC (CLK_TOP_NR_CLK + 22) 47*8adea9b9SFabien Parent #define CLK_TOP_32K_CEC (CLK_TOP_NR_CLK + 23) 48*8adea9b9SFabien Parent #define CLK_TOP_GCPU_B (CLK_TOP_NR_CLK + 24) 49*8adea9b9SFabien Parent #define CLK_TOP_RG_VDEC (CLK_TOP_NR_CLK + 25) 50*8adea9b9SFabien Parent #define CLK_TOP_RG_FDPI0 (CLK_TOP_NR_CLK + 26) 51*8adea9b9SFabien Parent #define CLK_TOP_RG_FDPI1 (CLK_TOP_NR_CLK + 27) 52*8adea9b9SFabien Parent #define CLK_TOP_RG_AXI_MFG (CLK_TOP_NR_CLK + 28) 53*8adea9b9SFabien Parent #define CLK_TOP_RG_SLOW_MFG (CLK_TOP_NR_CLK + 29) 54*8adea9b9SFabien Parent #define CLK_TOP_GFMUX_EMI1X_SEL (CLK_TOP_NR_CLK + 30) 55*8adea9b9SFabien Parent #define CLK_TOP_CSW_MUX_MFG_SEL (CLK_TOP_NR_CLK + 31) 56*8adea9b9SFabien Parent #define CLK_TOP_CAMTG_MM_SEL (CLK_TOP_NR_CLK + 32) 57*8adea9b9SFabien Parent #define CLK_TOP_PWM_MM_SEL (CLK_TOP_NR_CLK + 33) 58*8adea9b9SFabien Parent #define CLK_TOP_SPM_52M_SEL (CLK_TOP_NR_CLK + 34) 59*8adea9b9SFabien Parent #define CLK_TOP_MFG_MM_SEL (CLK_TOP_NR_CLK + 35) 60*8adea9b9SFabien Parent #define CLK_TOP_SMI_MM_SEL (CLK_TOP_NR_CLK + 36) 61*8adea9b9SFabien Parent #define CLK_TOP_SCAM_MM_SEL (CLK_TOP_NR_CLK + 37) 62*8adea9b9SFabien Parent #define CLK_TOP_VDEC_MM_SEL (CLK_TOP_NR_CLK + 38) 63*8adea9b9SFabien Parent #define CLK_TOP_DPI0_MM_SEL (CLK_TOP_NR_CLK + 39) 64*8adea9b9SFabien Parent #define CLK_TOP_DPI1_MM_SEL (CLK_TOP_NR_CLK + 40) 65*8adea9b9SFabien Parent #define CLK_TOP_AXI_MFG_IN_SEL (CLK_TOP_NR_CLK + 41) 66*8adea9b9SFabien Parent #define CLK_TOP_SLOW_MFG_SEL (CLK_TOP_NR_CLK + 42) 67*8adea9b9SFabien Parent #define MT8167_CLK_TOP_NR_CLK (CLK_TOP_NR_CLK + 43) 68*8adea9b9SFabien Parent 69*8adea9b9SFabien Parent /* MFGCFG */ 70*8adea9b9SFabien Parent 71*8adea9b9SFabien Parent #define CLK_MFG_BAXI 0 72*8adea9b9SFabien Parent #define CLK_MFG_BMEM 1 73*8adea9b9SFabien Parent #define CLK_MFG_BG3D 2 74*8adea9b9SFabien Parent #define CLK_MFG_B26M 3 75*8adea9b9SFabien Parent #define CLK_MFG_NR_CLK 4 76*8adea9b9SFabien Parent 77*8adea9b9SFabien Parent /* MMSYS */ 78*8adea9b9SFabien Parent 79*8adea9b9SFabien Parent #define CLK_MM_SMI_COMMON 0 80*8adea9b9SFabien Parent #define CLK_MM_SMI_LARB0 1 81*8adea9b9SFabien Parent #define CLK_MM_CAM_MDP 2 82*8adea9b9SFabien Parent #define CLK_MM_MDP_RDMA 3 83*8adea9b9SFabien Parent #define CLK_MM_MDP_RSZ0 4 84*8adea9b9SFabien Parent #define CLK_MM_MDP_RSZ1 5 85*8adea9b9SFabien Parent #define CLK_MM_MDP_TDSHP 6 86*8adea9b9SFabien Parent #define CLK_MM_MDP_WDMA 7 87*8adea9b9SFabien Parent #define CLK_MM_MDP_WROT 8 88*8adea9b9SFabien Parent #define CLK_MM_FAKE_ENG 9 89*8adea9b9SFabien Parent #define CLK_MM_DISP_OVL0 10 90*8adea9b9SFabien Parent #define CLK_MM_DISP_RDMA0 11 91*8adea9b9SFabien Parent #define CLK_MM_DISP_RDMA1 12 92*8adea9b9SFabien Parent #define CLK_MM_DISP_WDMA 13 93*8adea9b9SFabien Parent #define CLK_MM_DISP_COLOR 14 94*8adea9b9SFabien Parent #define CLK_MM_DISP_CCORR 15 95*8adea9b9SFabien Parent #define CLK_MM_DISP_AAL 16 96*8adea9b9SFabien Parent #define CLK_MM_DISP_GAMMA 17 97*8adea9b9SFabien Parent #define CLK_MM_DISP_DITHER 18 98*8adea9b9SFabien Parent #define CLK_MM_DISP_UFOE 19 99*8adea9b9SFabien Parent #define CLK_MM_DISP_PWM_MM 20 100*8adea9b9SFabien Parent #define CLK_MM_DISP_PWM_26M 21 101*8adea9b9SFabien Parent #define CLK_MM_DSI_ENGINE 22 102*8adea9b9SFabien Parent #define CLK_MM_DSI_DIGITAL 23 103*8adea9b9SFabien Parent #define CLK_MM_DPI0_ENGINE 24 104*8adea9b9SFabien Parent #define CLK_MM_DPI0_PXL 25 105*8adea9b9SFabien Parent #define CLK_MM_LVDS_PXL 26 106*8adea9b9SFabien Parent #define CLK_MM_LVDS_CTS 27 107*8adea9b9SFabien Parent #define CLK_MM_DPI1_ENGINE 28 108*8adea9b9SFabien Parent #define CLK_MM_DPI1_PXL 29 109*8adea9b9SFabien Parent #define CLK_MM_HDMI_PXL 30 110*8adea9b9SFabien Parent #define CLK_MM_HDMI_SPDIF 31 111*8adea9b9SFabien Parent #define CLK_MM_HDMI_ADSP_BCK 32 112*8adea9b9SFabien Parent #define CLK_MM_HDMI_PLL 33 113*8adea9b9SFabien Parent #define CLK_MM_NR_CLK 34 114*8adea9b9SFabien Parent 115*8adea9b9SFabien Parent /* IMGSYS */ 116*8adea9b9SFabien Parent 117*8adea9b9SFabien Parent #define CLK_IMG_LARB1_SMI 0 118*8adea9b9SFabien Parent #define CLK_IMG_CAM_SMI 1 119*8adea9b9SFabien Parent #define CLK_IMG_CAM_CAM 2 120*8adea9b9SFabien Parent #define CLK_IMG_SEN_TG 3 121*8adea9b9SFabien Parent #define CLK_IMG_SEN_CAM 4 122*8adea9b9SFabien Parent #define CLK_IMG_VENC 5 123*8adea9b9SFabien Parent #define CLK_IMG_NR_CLK 6 124*8adea9b9SFabien Parent 125*8adea9b9SFabien Parent /* VDECSYS */ 126*8adea9b9SFabien Parent 127*8adea9b9SFabien Parent #define CLK_VDEC_CKEN 0 128*8adea9b9SFabien Parent #define CLK_VDEC_LARB1_CKEN 1 129*8adea9b9SFabien Parent #define CLK_VDEC_NR_CLK 2 130*8adea9b9SFabien Parent 131*8adea9b9SFabien Parent #endif /* _DT_BINDINGS_CLK_MT8167_H */ 132