1cd9102e9SKrzysztof Kozlowski /* SPDX-License-Identifier: GPL-2.0 */ 24c5773f9SKrzysztof Kozlowski /* 34c5773f9SKrzysztof Kozlowski * Copyright (c) 2014 Samsung Electronics Co., Ltd. 45cd3535aSKrzysztof Kozlowski * Copyright (c) 2016 Krzysztof Kozlowski 54c5773f9SKrzysztof Kozlowski * 64c5773f9SKrzysztof Kozlowski * Device Tree binding constants for Exynos5421 clock controller. 74c5773f9SKrzysztof Kozlowski */ 84c5773f9SKrzysztof Kozlowski 9e7ef0b63STarek Dakhran #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H 10e7ef0b63STarek Dakhran #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H 11e7ef0b63STarek Dakhran 12e7ef0b63STarek Dakhran /* core clocks */ 13e7ef0b63STarek Dakhran #define CLK_FIN_PLL 1 14e7ef0b63STarek Dakhran #define CLK_FOUT_APLL 2 15e7ef0b63STarek Dakhran #define CLK_FOUT_CPLL 3 16e7ef0b63STarek Dakhran #define CLK_FOUT_MPLL 4 17e7ef0b63STarek Dakhran #define CLK_FOUT_BPLL 5 18e7ef0b63STarek Dakhran #define CLK_FOUT_KPLL 6 1958d6506fSSylwester Nawrocki #define CLK_FOUT_EPLL 7 20e7ef0b63STarek Dakhran 21e7ef0b63STarek Dakhran /* gate for special clocks (sclk) */ 22e7ef0b63STarek Dakhran #define CLK_SCLK_UART0 128 23e7ef0b63STarek Dakhran #define CLK_SCLK_UART1 129 24e7ef0b63STarek Dakhran #define CLK_SCLK_UART2 130 25e7ef0b63STarek Dakhran #define CLK_SCLK_UART3 131 26e7ef0b63STarek Dakhran #define CLK_SCLK_MMC0 132 27e7ef0b63STarek Dakhran #define CLK_SCLK_MMC1 133 28e7ef0b63STarek Dakhran #define CLK_SCLK_MMC2 134 295cd3535aSKrzysztof Kozlowski #define CLK_SCLK_USBD300 150 305cd3535aSKrzysztof Kozlowski #define CLK_SCLK_USBD301 151 315cd3535aSKrzysztof Kozlowski #define CLK_SCLK_USBPHY300 152 325cd3535aSKrzysztof Kozlowski #define CLK_SCLK_USBPHY301 153 335cd3535aSKrzysztof Kozlowski #define CLK_SCLK_PWM 155 34e7ef0b63STarek Dakhran 35e7ef0b63STarek Dakhran /* gate clocks */ 36e7ef0b63STarek Dakhran #define CLK_UART0 257 37e7ef0b63STarek Dakhran #define CLK_UART1 258 38e7ef0b63STarek Dakhran #define CLK_UART2 259 399d8e8f04SKrzysztof Kozlowski #define CLK_UART3 260 40ed1e1505SKrzysztof Kozlowski #define CLK_I2C0 261 41ed1e1505SKrzysztof Kozlowski #define CLK_I2C1 262 42ed1e1505SKrzysztof Kozlowski #define CLK_I2C2 263 43ed1e1505SKrzysztof Kozlowski #define CLK_I2C3 264 44ed1e1505SKrzysztof Kozlowski #define CLK_USI0 265 45ed1e1505SKrzysztof Kozlowski #define CLK_USI1 266 46ed1e1505SKrzysztof Kozlowski #define CLK_USI2 267 47ed1e1505SKrzysztof Kozlowski #define CLK_USI3 268 48*c52c6857SKrzysztof Kozlowski #define CLK_TSADC 270 495cd3535aSKrzysztof Kozlowski #define CLK_PWM 279 50e7ef0b63STarek Dakhran #define CLK_MCT 315 514528dd8eSKrzysztof Kozlowski #define CLK_WDT 316 52ed1e1505SKrzysztof Kozlowski #define CLK_RTC 317 53109869f5SKrzysztof Kozlowski #define CLK_TMU 318 54e7ef0b63STarek Dakhran #define CLK_MMC0 351 55e7ef0b63STarek Dakhran #define CLK_MMC1 352 56e7ef0b63STarek Dakhran #define CLK_MMC2 353 5758d6506fSSylwester Nawrocki #define CLK_PDMA0 362 5858d6506fSSylwester Nawrocki #define CLK_PDMA1 363 595cd3535aSKrzysztof Kozlowski #define CLK_USBH20 365 605cd3535aSKrzysztof Kozlowski #define CLK_USBD300 366 615cd3535aSKrzysztof Kozlowski #define CLK_USBD301 367 624528dd8eSKrzysztof Kozlowski #define CLK_SSS 471 63e7ef0b63STarek Dakhran 64e7ef0b63STarek Dakhran #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ 65