1835a486cSAnup Patel // SPDX-License-Identifier: GPL-2.0-or-later
2835a486cSAnup Patel /*
3835a486cSAnup Patel * Multiplex several virtual IPIs over a single HW IPI.
4835a486cSAnup Patel *
5835a486cSAnup Patel * Copyright The Asahi Linux Contributors
6835a486cSAnup Patel * Copyright (c) 2022 Ventana Micro Systems Inc.
7835a486cSAnup Patel */
8835a486cSAnup Patel
9835a486cSAnup Patel #define pr_fmt(fmt) "ipi-mux: " fmt
10835a486cSAnup Patel #include <linux/cpu.h>
11835a486cSAnup Patel #include <linux/init.h>
12835a486cSAnup Patel #include <linux/irq.h>
13835a486cSAnup Patel #include <linux/irqchip.h>
14835a486cSAnup Patel #include <linux/irqchip/chained_irq.h>
15835a486cSAnup Patel #include <linux/irqdomain.h>
16835a486cSAnup Patel #include <linux/jump_label.h>
17835a486cSAnup Patel #include <linux/percpu.h>
18835a486cSAnup Patel #include <linux/smp.h>
19835a486cSAnup Patel
20835a486cSAnup Patel struct ipi_mux_cpu {
21835a486cSAnup Patel atomic_t enable;
22835a486cSAnup Patel atomic_t bits;
23835a486cSAnup Patel };
24835a486cSAnup Patel
25835a486cSAnup Patel static struct ipi_mux_cpu __percpu *ipi_mux_pcpu;
26835a486cSAnup Patel static struct irq_domain *ipi_mux_domain;
27835a486cSAnup Patel static void (*ipi_mux_send)(unsigned int cpu);
28835a486cSAnup Patel
ipi_mux_mask(struct irq_data * d)29835a486cSAnup Patel static void ipi_mux_mask(struct irq_data *d)
30835a486cSAnup Patel {
31835a486cSAnup Patel struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
32835a486cSAnup Patel
33835a486cSAnup Patel atomic_andnot(BIT(irqd_to_hwirq(d)), &icpu->enable);
34835a486cSAnup Patel }
35835a486cSAnup Patel
ipi_mux_unmask(struct irq_data * d)36835a486cSAnup Patel static void ipi_mux_unmask(struct irq_data *d)
37835a486cSAnup Patel {
38835a486cSAnup Patel struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
39835a486cSAnup Patel u32 ibit = BIT(irqd_to_hwirq(d));
40835a486cSAnup Patel
41835a486cSAnup Patel atomic_or(ibit, &icpu->enable);
42835a486cSAnup Patel
43835a486cSAnup Patel /*
44835a486cSAnup Patel * The atomic_or() above must complete before the atomic_read()
45835a486cSAnup Patel * below to avoid racing ipi_mux_send_mask().
46835a486cSAnup Patel */
47835a486cSAnup Patel smp_mb__after_atomic();
48835a486cSAnup Patel
49835a486cSAnup Patel /* If a pending IPI was unmasked, raise a parent IPI immediately. */
50835a486cSAnup Patel if (atomic_read(&icpu->bits) & ibit)
51835a486cSAnup Patel ipi_mux_send(smp_processor_id());
52835a486cSAnup Patel }
53835a486cSAnup Patel
ipi_mux_send_mask(struct irq_data * d,const struct cpumask * mask)54835a486cSAnup Patel static void ipi_mux_send_mask(struct irq_data *d, const struct cpumask *mask)
55835a486cSAnup Patel {
56835a486cSAnup Patel struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
57835a486cSAnup Patel u32 ibit = BIT(irqd_to_hwirq(d));
58835a486cSAnup Patel unsigned long pending;
59835a486cSAnup Patel int cpu;
60835a486cSAnup Patel
61835a486cSAnup Patel for_each_cpu(cpu, mask) {
62835a486cSAnup Patel icpu = per_cpu_ptr(ipi_mux_pcpu, cpu);
63835a486cSAnup Patel
64835a486cSAnup Patel /*
65835a486cSAnup Patel * This sequence is the mirror of the one in ipi_mux_unmask();
66835a486cSAnup Patel * see the comment there. Additionally, release semantics
67835a486cSAnup Patel * ensure that the vIPI flag set is ordered after any shared
68835a486cSAnup Patel * memory accesses that precede it. This therefore also pairs
69835a486cSAnup Patel * with the atomic_fetch_andnot in ipi_mux_process().
70835a486cSAnup Patel */
71835a486cSAnup Patel pending = atomic_fetch_or_release(ibit, &icpu->bits);
72835a486cSAnup Patel
73835a486cSAnup Patel /*
74835a486cSAnup Patel * The atomic_fetch_or_release() above must complete
75835a486cSAnup Patel * before the atomic_read() below to avoid racing with
76835a486cSAnup Patel * ipi_mux_unmask().
77835a486cSAnup Patel */
78835a486cSAnup Patel smp_mb__after_atomic();
79835a486cSAnup Patel
80835a486cSAnup Patel /*
81835a486cSAnup Patel * The flag writes must complete before the physical IPI is
82835a486cSAnup Patel * issued to another CPU. This is implied by the control
83835a486cSAnup Patel * dependency on the result of atomic_read() below, which is
84835a486cSAnup Patel * itself already ordered after the vIPI flag write.
85835a486cSAnup Patel */
86835a486cSAnup Patel if (!(pending & ibit) && (atomic_read(&icpu->enable) & ibit))
87835a486cSAnup Patel ipi_mux_send(cpu);
88835a486cSAnup Patel }
89835a486cSAnup Patel }
90835a486cSAnup Patel
91835a486cSAnup Patel static const struct irq_chip ipi_mux_chip = {
92835a486cSAnup Patel .name = "IPI Mux",
93835a486cSAnup Patel .irq_mask = ipi_mux_mask,
94835a486cSAnup Patel .irq_unmask = ipi_mux_unmask,
95835a486cSAnup Patel .ipi_send_mask = ipi_mux_send_mask,
96835a486cSAnup Patel };
97835a486cSAnup Patel
ipi_mux_domain_alloc(struct irq_domain * d,unsigned int virq,unsigned int nr_irqs,void * arg)98835a486cSAnup Patel static int ipi_mux_domain_alloc(struct irq_domain *d, unsigned int virq,
99835a486cSAnup Patel unsigned int nr_irqs, void *arg)
100835a486cSAnup Patel {
101835a486cSAnup Patel int i;
102835a486cSAnup Patel
103835a486cSAnup Patel for (i = 0; i < nr_irqs; i++) {
104835a486cSAnup Patel irq_set_percpu_devid(virq + i);
105835a486cSAnup Patel irq_domain_set_info(d, virq + i, i, &ipi_mux_chip, NULL,
106835a486cSAnup Patel handle_percpu_devid_irq, NULL, NULL);
107835a486cSAnup Patel }
108835a486cSAnup Patel
109835a486cSAnup Patel return 0;
110835a486cSAnup Patel }
111835a486cSAnup Patel
112835a486cSAnup Patel static const struct irq_domain_ops ipi_mux_domain_ops = {
113835a486cSAnup Patel .alloc = ipi_mux_domain_alloc,
114835a486cSAnup Patel .free = irq_domain_free_irqs_top,
115835a486cSAnup Patel };
116835a486cSAnup Patel
117835a486cSAnup Patel /**
118835a486cSAnup Patel * ipi_mux_process - Process multiplexed virtual IPIs
119835a486cSAnup Patel */
ipi_mux_process(void)120835a486cSAnup Patel void ipi_mux_process(void)
121835a486cSAnup Patel {
122835a486cSAnup Patel struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu);
123835a486cSAnup Patel irq_hw_number_t hwirq;
124835a486cSAnup Patel unsigned long ipis;
125835a486cSAnup Patel unsigned int en;
126835a486cSAnup Patel
127835a486cSAnup Patel /*
128835a486cSAnup Patel * Reading enable mask does not need to be ordered as long as
129835a486cSAnup Patel * this function is called from interrupt handler because only
130835a486cSAnup Patel * the CPU itself can change it's own enable mask.
131835a486cSAnup Patel */
132835a486cSAnup Patel en = atomic_read(&icpu->enable);
133835a486cSAnup Patel
134835a486cSAnup Patel /*
135835a486cSAnup Patel * Clear the IPIs we are about to handle. This pairs with the
136835a486cSAnup Patel * atomic_fetch_or_release() in ipi_mux_send_mask().
137835a486cSAnup Patel */
138835a486cSAnup Patel ipis = atomic_fetch_andnot(en, &icpu->bits) & en;
139835a486cSAnup Patel
140835a486cSAnup Patel for_each_set_bit(hwirq, &ipis, BITS_PER_TYPE(int))
141835a486cSAnup Patel generic_handle_domain_irq(ipi_mux_domain, hwirq);
142835a486cSAnup Patel }
143835a486cSAnup Patel
144835a486cSAnup Patel /**
145835a486cSAnup Patel * ipi_mux_create - Create virtual IPIs multiplexed on top of a single
146835a486cSAnup Patel * parent IPI.
147835a486cSAnup Patel * @nr_ipi: number of virtual IPIs to create. This should
148835a486cSAnup Patel * be <= BITS_PER_TYPE(int)
149835a486cSAnup Patel * @mux_send: callback to trigger parent IPI for a particular CPU
150835a486cSAnup Patel *
151835a486cSAnup Patel * Returns first virq of the newly created virtual IPIs upon success
152835a486cSAnup Patel * or <=0 upon failure
153835a486cSAnup Patel */
ipi_mux_create(unsigned int nr_ipi,void (* mux_send)(unsigned int cpu))154835a486cSAnup Patel int ipi_mux_create(unsigned int nr_ipi, void (*mux_send)(unsigned int cpu))
155835a486cSAnup Patel {
156835a486cSAnup Patel struct fwnode_handle *fwnode;
157835a486cSAnup Patel struct irq_domain *domain;
158835a486cSAnup Patel int rc;
159835a486cSAnup Patel
160835a486cSAnup Patel if (ipi_mux_domain)
161835a486cSAnup Patel return -EEXIST;
162835a486cSAnup Patel
163835a486cSAnup Patel if (BITS_PER_TYPE(int) < nr_ipi || !mux_send)
164835a486cSAnup Patel return -EINVAL;
165835a486cSAnup Patel
166835a486cSAnup Patel ipi_mux_pcpu = alloc_percpu(typeof(*ipi_mux_pcpu));
167835a486cSAnup Patel if (!ipi_mux_pcpu)
168835a486cSAnup Patel return -ENOMEM;
169835a486cSAnup Patel
170835a486cSAnup Patel fwnode = irq_domain_alloc_named_fwnode("IPI-Mux");
171835a486cSAnup Patel if (!fwnode) {
172835a486cSAnup Patel pr_err("unable to create IPI Mux fwnode\n");
173835a486cSAnup Patel rc = -ENOMEM;
174835a486cSAnup Patel goto fail_free_cpu;
175835a486cSAnup Patel }
176835a486cSAnup Patel
177835a486cSAnup Patel domain = irq_domain_create_linear(fwnode, nr_ipi,
178835a486cSAnup Patel &ipi_mux_domain_ops, NULL);
179835a486cSAnup Patel if (!domain) {
180835a486cSAnup Patel pr_err("unable to add IPI Mux domain\n");
181835a486cSAnup Patel rc = -ENOMEM;
182835a486cSAnup Patel goto fail_free_fwnode;
183835a486cSAnup Patel }
184835a486cSAnup Patel
185835a486cSAnup Patel domain->flags |= IRQ_DOMAIN_FLAG_IPI_SINGLE;
186835a486cSAnup Patel irq_domain_update_bus_token(domain, DOMAIN_BUS_IPI);
187835a486cSAnup Patel
188*3d812a0fSMarc Zyngier rc = irq_domain_alloc_irqs(domain, nr_ipi, NUMA_NO_NODE, NULL);
189835a486cSAnup Patel if (rc <= 0) {
190835a486cSAnup Patel pr_err("unable to alloc IRQs from IPI Mux domain\n");
191835a486cSAnup Patel goto fail_free_domain;
192835a486cSAnup Patel }
193835a486cSAnup Patel
194835a486cSAnup Patel ipi_mux_domain = domain;
195835a486cSAnup Patel ipi_mux_send = mux_send;
196835a486cSAnup Patel
197835a486cSAnup Patel return rc;
198835a486cSAnup Patel
199835a486cSAnup Patel fail_free_domain:
200835a486cSAnup Patel irq_domain_remove(domain);
201835a486cSAnup Patel fail_free_fwnode:
202835a486cSAnup Patel irq_domain_free_fwnode(fwnode);
203835a486cSAnup Patel fail_free_cpu:
204835a486cSAnup Patel free_percpu(ipi_mux_pcpu);
205835a486cSAnup Patel return rc;
206835a486cSAnup Patel }
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