1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * arch-independent dma-mapping routines 4 * 5 * Copyright (c) 2006 SUSE Linux Products GmbH 6 * Copyright (c) 2006 Tejun Heo <teheo@suse.de> 7 */ 8 #include <linux/memblock.h> /* for max_pfn */ 9 #include <linux/acpi.h> 10 #include <linux/dma-direct.h> 11 #include <linux/dma-noncoherent.h> 12 #include <linux/export.h> 13 #include <linux/gfp.h> 14 #include <linux/of_device.h> 15 #include <linux/slab.h> 16 #include <linux/vmalloc.h> 17 18 /* 19 * Managed DMA API 20 */ 21 struct dma_devres { 22 size_t size; 23 void *vaddr; 24 dma_addr_t dma_handle; 25 unsigned long attrs; 26 }; 27 28 static void dmam_release(struct device *dev, void *res) 29 { 30 struct dma_devres *this = res; 31 32 dma_free_attrs(dev, this->size, this->vaddr, this->dma_handle, 33 this->attrs); 34 } 35 36 static int dmam_match(struct device *dev, void *res, void *match_data) 37 { 38 struct dma_devres *this = res, *match = match_data; 39 40 if (this->vaddr == match->vaddr) { 41 WARN_ON(this->size != match->size || 42 this->dma_handle != match->dma_handle); 43 return 1; 44 } 45 return 0; 46 } 47 48 /** 49 * dmam_free_coherent - Managed dma_free_coherent() 50 * @dev: Device to free coherent memory for 51 * @size: Size of allocation 52 * @vaddr: Virtual address of the memory to free 53 * @dma_handle: DMA handle of the memory to free 54 * 55 * Managed dma_free_coherent(). 56 */ 57 void dmam_free_coherent(struct device *dev, size_t size, void *vaddr, 58 dma_addr_t dma_handle) 59 { 60 struct dma_devres match_data = { size, vaddr, dma_handle }; 61 62 dma_free_coherent(dev, size, vaddr, dma_handle); 63 WARN_ON(devres_destroy(dev, dmam_release, dmam_match, &match_data)); 64 } 65 EXPORT_SYMBOL(dmam_free_coherent); 66 67 /** 68 * dmam_alloc_attrs - Managed dma_alloc_attrs() 69 * @dev: Device to allocate non_coherent memory for 70 * @size: Size of allocation 71 * @dma_handle: Out argument for allocated DMA handle 72 * @gfp: Allocation flags 73 * @attrs: Flags in the DMA_ATTR_* namespace. 74 * 75 * Managed dma_alloc_attrs(). Memory allocated using this function will be 76 * automatically released on driver detach. 77 * 78 * RETURNS: 79 * Pointer to allocated memory on success, NULL on failure. 80 */ 81 void *dmam_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, 82 gfp_t gfp, unsigned long attrs) 83 { 84 struct dma_devres *dr; 85 void *vaddr; 86 87 dr = devres_alloc(dmam_release, sizeof(*dr), gfp); 88 if (!dr) 89 return NULL; 90 91 vaddr = dma_alloc_attrs(dev, size, dma_handle, gfp, attrs); 92 if (!vaddr) { 93 devres_free(dr); 94 return NULL; 95 } 96 97 dr->vaddr = vaddr; 98 dr->dma_handle = *dma_handle; 99 dr->size = size; 100 dr->attrs = attrs; 101 102 devres_add(dev, dr); 103 104 return vaddr; 105 } 106 EXPORT_SYMBOL(dmam_alloc_attrs); 107 108 /* 109 * Create scatter-list for the already allocated DMA buffer. 110 */ 111 int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt, 112 void *cpu_addr, dma_addr_t dma_addr, size_t size, 113 unsigned long attrs) 114 { 115 struct page *page; 116 int ret; 117 118 if (!dev_is_dma_coherent(dev)) { 119 unsigned long pfn; 120 121 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN)) 122 return -ENXIO; 123 124 /* If the PFN is not valid, we do not have a struct page */ 125 pfn = arch_dma_coherent_to_pfn(dev, cpu_addr, dma_addr); 126 if (!pfn_valid(pfn)) 127 return -ENXIO; 128 page = pfn_to_page(pfn); 129 } else { 130 page = virt_to_page(cpu_addr); 131 } 132 133 ret = sg_alloc_table(sgt, 1, GFP_KERNEL); 134 if (!ret) 135 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); 136 return ret; 137 } 138 139 /* 140 * The whole dma_get_sgtable() idea is fundamentally unsafe - it seems 141 * that the intention is to allow exporting memory allocated via the 142 * coherent DMA APIs through the dma_buf API, which only accepts a 143 * scattertable. This presents a couple of problems: 144 * 1. Not all memory allocated via the coherent DMA APIs is backed by 145 * a struct page 146 * 2. Passing coherent DMA memory into the streaming APIs is not allowed 147 * as we will try to flush the memory through a different alias to that 148 * actually being used (and the flushes are redundant.) 149 */ 150 int dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt, 151 void *cpu_addr, dma_addr_t dma_addr, size_t size, 152 unsigned long attrs) 153 { 154 const struct dma_map_ops *ops = get_dma_ops(dev); 155 156 if (dma_is_direct(ops)) 157 return dma_common_get_sgtable(dev, sgt, cpu_addr, dma_addr, 158 size, attrs); 159 if (!ops->get_sgtable) 160 return -ENXIO; 161 return ops->get_sgtable(dev, sgt, cpu_addr, dma_addr, size, attrs); 162 } 163 EXPORT_SYMBOL(dma_get_sgtable_attrs); 164 165 #ifdef CONFIG_MMU 166 /* 167 * Return the page attributes used for mapping dma_alloc_* memory, either in 168 * kernel space if remapping is needed, or to userspace through dma_mmap_*. 169 */ 170 pgprot_t dma_pgprot(struct device *dev, pgprot_t prot, unsigned long attrs) 171 { 172 if (dev_is_dma_coherent(dev) || 173 (IS_ENABLED(CONFIG_DMA_NONCOHERENT_CACHE_SYNC) && 174 (attrs & DMA_ATTR_NON_CONSISTENT))) 175 return prot; 176 #ifdef CONFIG_ARCH_HAS_DMA_WRITE_COMBINE 177 if (attrs & DMA_ATTR_WRITE_COMBINE) 178 return pgprot_writecombine(prot); 179 #endif 180 return pgprot_dmacoherent(prot); 181 } 182 #endif /* CONFIG_MMU */ 183 184 /* 185 * Create userspace mapping for the DMA-coherent memory. 186 */ 187 int dma_common_mmap(struct device *dev, struct vm_area_struct *vma, 188 void *cpu_addr, dma_addr_t dma_addr, size_t size, 189 unsigned long attrs) 190 { 191 #ifdef CONFIG_MMU 192 unsigned long user_count = vma_pages(vma); 193 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT; 194 unsigned long off = vma->vm_pgoff; 195 unsigned long pfn; 196 int ret = -ENXIO; 197 198 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs); 199 200 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) 201 return ret; 202 203 if (off >= count || user_count > count - off) 204 return -ENXIO; 205 206 if (!dev_is_dma_coherent(dev)) { 207 if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN)) 208 return -ENXIO; 209 210 /* If the PFN is not valid, we do not have a struct page */ 211 pfn = arch_dma_coherent_to_pfn(dev, cpu_addr, dma_addr); 212 if (!pfn_valid(pfn)) 213 return -ENXIO; 214 } else { 215 pfn = page_to_pfn(virt_to_page(cpu_addr)); 216 } 217 218 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff, 219 user_count << PAGE_SHIFT, vma->vm_page_prot); 220 #else 221 return -ENXIO; 222 #endif /* CONFIG_MMU */ 223 } 224 225 /** 226 * dma_can_mmap - check if a given device supports dma_mmap_* 227 * @dev: device to check 228 * 229 * Returns %true if @dev supports dma_mmap_coherent() and dma_mmap_attrs() to 230 * map DMA allocations to userspace. 231 */ 232 bool dma_can_mmap(struct device *dev) 233 { 234 const struct dma_map_ops *ops = get_dma_ops(dev); 235 236 if (dma_is_direct(ops)) { 237 return IS_ENABLED(CONFIG_MMU) && 238 (dev_is_dma_coherent(dev) || 239 IS_ENABLED(CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN)); 240 } 241 242 return ops->mmap != NULL; 243 } 244 EXPORT_SYMBOL_GPL(dma_can_mmap); 245 246 /** 247 * dma_mmap_attrs - map a coherent DMA allocation into user space 248 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices 249 * @vma: vm_area_struct describing requested user mapping 250 * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs 251 * @dma_addr: device-view address returned from dma_alloc_attrs 252 * @size: size of memory originally requested in dma_alloc_attrs 253 * @attrs: attributes of mapping properties requested in dma_alloc_attrs 254 * 255 * Map a coherent DMA buffer previously allocated by dma_alloc_attrs into user 256 * space. The coherent DMA buffer must not be freed by the driver until the 257 * user space mapping has been released. 258 */ 259 int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, 260 void *cpu_addr, dma_addr_t dma_addr, size_t size, 261 unsigned long attrs) 262 { 263 const struct dma_map_ops *ops = get_dma_ops(dev); 264 265 if (dma_is_direct(ops)) 266 return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size, 267 attrs); 268 if (!ops->mmap) 269 return -ENXIO; 270 return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs); 271 } 272 EXPORT_SYMBOL(dma_mmap_attrs); 273 274 static u64 dma_default_get_required_mask(struct device *dev) 275 { 276 u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT); 277 u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT)); 278 u64 mask; 279 280 if (!high_totalram) { 281 /* convert to mask just covering totalram */ 282 low_totalram = (1 << (fls(low_totalram) - 1)); 283 low_totalram += low_totalram - 1; 284 mask = low_totalram; 285 } else { 286 high_totalram = (1 << (fls(high_totalram) - 1)); 287 high_totalram += high_totalram - 1; 288 mask = (((u64)high_totalram) << 32) + 0xffffffff; 289 } 290 return mask; 291 } 292 293 u64 dma_get_required_mask(struct device *dev) 294 { 295 const struct dma_map_ops *ops = get_dma_ops(dev); 296 297 if (dma_is_direct(ops)) 298 return dma_direct_get_required_mask(dev); 299 if (ops->get_required_mask) 300 return ops->get_required_mask(dev); 301 return dma_default_get_required_mask(dev); 302 } 303 EXPORT_SYMBOL_GPL(dma_get_required_mask); 304 305 void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, 306 gfp_t flag, unsigned long attrs) 307 { 308 const struct dma_map_ops *ops = get_dma_ops(dev); 309 void *cpu_addr; 310 311 WARN_ON_ONCE(!dev->coherent_dma_mask); 312 313 if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr)) 314 return cpu_addr; 315 316 /* let the implementation decide on the zone to allocate from: */ 317 flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); 318 319 if (dma_is_direct(ops)) 320 cpu_addr = dma_direct_alloc(dev, size, dma_handle, flag, attrs); 321 else if (ops->alloc) 322 cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs); 323 else 324 return NULL; 325 326 debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr); 327 return cpu_addr; 328 } 329 EXPORT_SYMBOL(dma_alloc_attrs); 330 331 void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr, 332 dma_addr_t dma_handle, unsigned long attrs) 333 { 334 const struct dma_map_ops *ops = get_dma_ops(dev); 335 336 if (dma_release_from_dev_coherent(dev, get_order(size), cpu_addr)) 337 return; 338 /* 339 * On non-coherent platforms which implement DMA-coherent buffers via 340 * non-cacheable remaps, ops->free() may call vunmap(). Thus getting 341 * this far in IRQ context is a) at risk of a BUG_ON() or trying to 342 * sleep on some machines, and b) an indication that the driver is 343 * probably misusing the coherent API anyway. 344 */ 345 WARN_ON(irqs_disabled()); 346 347 if (!cpu_addr) 348 return; 349 350 debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); 351 if (dma_is_direct(ops)) 352 dma_direct_free(dev, size, cpu_addr, dma_handle, attrs); 353 else if (ops->free) 354 ops->free(dev, size, cpu_addr, dma_handle, attrs); 355 } 356 EXPORT_SYMBOL(dma_free_attrs); 357 358 static inline void dma_check_mask(struct device *dev, u64 mask) 359 { 360 if (sme_active() && (mask < (((u64)sme_get_me_mask() << 1) - 1))) 361 dev_warn(dev, "SME is active, device will require DMA bounce buffers\n"); 362 } 363 364 int dma_supported(struct device *dev, u64 mask) 365 { 366 const struct dma_map_ops *ops = get_dma_ops(dev); 367 368 if (dma_is_direct(ops)) 369 return dma_direct_supported(dev, mask); 370 if (!ops->dma_supported) 371 return 1; 372 return ops->dma_supported(dev, mask); 373 } 374 EXPORT_SYMBOL(dma_supported); 375 376 #ifdef CONFIG_ARCH_HAS_DMA_SET_MASK 377 void arch_dma_set_mask(struct device *dev, u64 mask); 378 #else 379 #define arch_dma_set_mask(dev, mask) do { } while (0) 380 #endif 381 382 int dma_set_mask(struct device *dev, u64 mask) 383 { 384 /* 385 * Truncate the mask to the actually supported dma_addr_t width to 386 * avoid generating unsupportable addresses. 387 */ 388 mask = (dma_addr_t)mask; 389 390 if (!dev->dma_mask || !dma_supported(dev, mask)) 391 return -EIO; 392 393 arch_dma_set_mask(dev, mask); 394 dma_check_mask(dev, mask); 395 *dev->dma_mask = mask; 396 return 0; 397 } 398 EXPORT_SYMBOL(dma_set_mask); 399 400 #ifndef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK 401 int dma_set_coherent_mask(struct device *dev, u64 mask) 402 { 403 /* 404 * Truncate the mask to the actually supported dma_addr_t width to 405 * avoid generating unsupportable addresses. 406 */ 407 mask = (dma_addr_t)mask; 408 409 if (!dma_supported(dev, mask)) 410 return -EIO; 411 412 dma_check_mask(dev, mask); 413 dev->coherent_dma_mask = mask; 414 return 0; 415 } 416 EXPORT_SYMBOL(dma_set_coherent_mask); 417 #endif 418 419 void dma_cache_sync(struct device *dev, void *vaddr, size_t size, 420 enum dma_data_direction dir) 421 { 422 const struct dma_map_ops *ops = get_dma_ops(dev); 423 424 BUG_ON(!valid_dma_direction(dir)); 425 426 if (dma_is_direct(ops)) 427 arch_dma_cache_sync(dev, vaddr, size, dir); 428 else if (ops->cache_sync) 429 ops->cache_sync(dev, vaddr, size, dir); 430 } 431 EXPORT_SYMBOL(dma_cache_sync); 432 433 size_t dma_max_mapping_size(struct device *dev) 434 { 435 const struct dma_map_ops *ops = get_dma_ops(dev); 436 size_t size = SIZE_MAX; 437 438 if (dma_is_direct(ops)) 439 size = dma_direct_max_mapping_size(dev); 440 else if (ops && ops->max_mapping_size) 441 size = ops->max_mapping_size(dev); 442 443 return size; 444 } 445 EXPORT_SYMBOL_GPL(dma_max_mapping_size); 446 447 unsigned long dma_get_merge_boundary(struct device *dev) 448 { 449 const struct dma_map_ops *ops = get_dma_ops(dev); 450 451 if (!ops || !ops->get_merge_boundary) 452 return 0; /* can't merge */ 453 454 return ops->get_merge_boundary(dev); 455 } 456 EXPORT_SYMBOL_GPL(dma_get_merge_boundary); 457