1 /* 2 * linux/include/video/vga.h -- standard VGA chipset interaction 3 * 4 * Copyright 1999 Jeff Garzik <jgarzik@pobox.com> 5 * 6 * Copyright history from vga16fb.c: 7 * Copyright 1999 Ben Pfaff and Petr Vandrovec 8 * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm 9 * Based on VESA framebuffer (c) 1998 Gerd Knorr 10 * 11 * This file is subject to the terms and conditions of the GNU General 12 * Public License. See the file COPYING in the main directory of this 13 * archive for more details. 14 * 15 */ 16 17 #ifndef __linux_video_vga_h__ 18 #define __linux_video_vga_h__ 19 20 #include <linux/config.h> 21 #include <linux/types.h> 22 #include <asm/io.h> 23 #ifndef CONFIG_AMIGA 24 #include <asm/vga.h> 25 #else 26 /* 27 * FIXME 28 * Ugh, we don't have PCI space, so map readb() and friends to use Zorro space 29 * for MMIO accesses. This should make cirrusfb work again on Amiga 30 */ 31 #undef inb_p 32 #undef inw_p 33 #undef outb_p 34 #undef outw 35 #undef readb 36 #undef writeb 37 #undef writew 38 #define inb_p(port) 0 39 #define inw_p(port) 0 40 #define outb_p(port, val) do { } while (0) 41 #define outw(port, val) do { } while (0) 42 #define readb z_readb 43 #define writeb z_writeb 44 #define writew z_writew 45 #endif 46 #include <asm/byteorder.h> 47 48 49 /* Some of the code below is taken from SVGAlib. The original, 50 unmodified copyright notice for that code is below. */ 51 /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */ 52 /* */ 53 /* This library is free software; you can redistribute it and/or */ 54 /* modify it without any restrictions. This library is distributed */ 55 /* in the hope that it will be useful, but without any warranty. */ 56 57 /* Multi-chipset support Copyright 1993 Harm Hanemaayer */ 58 /* partially copyrighted (C) 1993 by Hartmut Schirmer */ 59 60 /* VGA data register ports */ 61 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */ 62 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */ 63 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */ 64 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */ 65 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */ 66 #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */ 67 #define VGA_MIS_R 0x3CC /* Misc Output Read Register */ 68 #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */ 69 #define VGA_FTC_R 0x3CA /* Feature Control Read Register */ 70 #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */ 71 #define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */ 72 #define VGA_PEL_D 0x3C9 /* PEL Data Register */ 73 #define VGA_PEL_MSK 0x3C6 /* PEL mask register */ 74 75 /* EGA-specific registers */ 76 #define EGA_GFX_E0 0x3CC /* Graphics enable processor 0 */ 77 #define EGA_GFX_E1 0x3CA /* Graphics enable processor 1 */ 78 79 /* VGA index register ports */ 80 #define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */ 81 #define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */ 82 #define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */ 83 #define VGA_GFX_I 0x3CE /* Graphics Controller Index */ 84 #define VGA_SEQ_I 0x3C4 /* Sequencer Index */ 85 #define VGA_PEL_IW 0x3C8 /* PEL Write Index */ 86 #define VGA_PEL_IR 0x3C7 /* PEL Read Index */ 87 88 /* standard VGA indexes max counts */ 89 #define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */ 90 #define VGA_ATT_C 0x15 /* Number of Attribute Controller Registers */ 91 #define VGA_GFX_C 0x09 /* Number of Graphics Controller Registers */ 92 #define VGA_SEQ_C 0x05 /* Number of Sequencer Registers */ 93 #define VGA_MIS_C 0x01 /* Number of Misc Output Register */ 94 95 /* VGA misc register bit masks */ 96 #define VGA_MIS_COLOR 0x01 97 #define VGA_MIS_ENB_MEM_ACCESS 0x02 98 #define VGA_MIS_DCLK_28322_720 0x04 99 #define VGA_MIS_ENB_PLL_LOAD (0x04 | 0x08) 100 #define VGA_MIS_SEL_HIGH_PAGE 0x20 101 102 /* VGA CRT controller register indices */ 103 #define VGA_CRTC_H_TOTAL 0 104 #define VGA_CRTC_H_DISP 1 105 #define VGA_CRTC_H_BLANK_START 2 106 #define VGA_CRTC_H_BLANK_END 3 107 #define VGA_CRTC_H_SYNC_START 4 108 #define VGA_CRTC_H_SYNC_END 5 109 #define VGA_CRTC_V_TOTAL 6 110 #define VGA_CRTC_OVERFLOW 7 111 #define VGA_CRTC_PRESET_ROW 8 112 #define VGA_CRTC_MAX_SCAN 9 113 #define VGA_CRTC_CURSOR_START 0x0A 114 #define VGA_CRTC_CURSOR_END 0x0B 115 #define VGA_CRTC_START_HI 0x0C 116 #define VGA_CRTC_START_LO 0x0D 117 #define VGA_CRTC_CURSOR_HI 0x0E 118 #define VGA_CRTC_CURSOR_LO 0x0F 119 #define VGA_CRTC_V_SYNC_START 0x10 120 #define VGA_CRTC_V_SYNC_END 0x11 121 #define VGA_CRTC_V_DISP_END 0x12 122 #define VGA_CRTC_OFFSET 0x13 123 #define VGA_CRTC_UNDERLINE 0x14 124 #define VGA_CRTC_V_BLANK_START 0x15 125 #define VGA_CRTC_V_BLANK_END 0x16 126 #define VGA_CRTC_MODE 0x17 127 #define VGA_CRTC_LINE_COMPARE 0x18 128 #define VGA_CRTC_REGS VGA_CRT_C 129 130 /* VGA CRT controller bit masks */ 131 #define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */ 132 #define VGA_CR17_H_V_SIGNALS_ENABLED 0x80 133 134 /* VGA attribute controller register indices */ 135 #define VGA_ATC_PALETTE0 0x00 136 #define VGA_ATC_PALETTE1 0x01 137 #define VGA_ATC_PALETTE2 0x02 138 #define VGA_ATC_PALETTE3 0x03 139 #define VGA_ATC_PALETTE4 0x04 140 #define VGA_ATC_PALETTE5 0x05 141 #define VGA_ATC_PALETTE6 0x06 142 #define VGA_ATC_PALETTE7 0x07 143 #define VGA_ATC_PALETTE8 0x08 144 #define VGA_ATC_PALETTE9 0x09 145 #define VGA_ATC_PALETTEA 0x0A 146 #define VGA_ATC_PALETTEB 0x0B 147 #define VGA_ATC_PALETTEC 0x0C 148 #define VGA_ATC_PALETTED 0x0D 149 #define VGA_ATC_PALETTEE 0x0E 150 #define VGA_ATC_PALETTEF 0x0F 151 #define VGA_ATC_MODE 0x10 152 #define VGA_ATC_OVERSCAN 0x11 153 #define VGA_ATC_PLANE_ENABLE 0x12 154 #define VGA_ATC_PEL 0x13 155 #define VGA_ATC_COLOR_PAGE 0x14 156 157 #define VGA_AR_ENABLE_DISPLAY 0x20 158 159 /* VGA sequencer register indices */ 160 #define VGA_SEQ_RESET 0x00 161 #define VGA_SEQ_CLOCK_MODE 0x01 162 #define VGA_SEQ_PLANE_WRITE 0x02 163 #define VGA_SEQ_CHARACTER_MAP 0x03 164 #define VGA_SEQ_MEMORY_MODE 0x04 165 166 /* VGA sequencer register bit masks */ 167 #define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */ 168 #define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */ 169 #define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */ 170 #define VGA_SR04_EXT_MEM 0x02 /* bit 1: allows complete mem access to 256K */ 171 #define VGA_SR04_SEQ_MODE 0x04 /* bit 2: directs system to use a sequential addressing mode */ 172 #define VGA_SR04_CHN_4M 0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */ 173 174 /* VGA graphics controller register indices */ 175 #define VGA_GFX_SR_VALUE 0x00 176 #define VGA_GFX_SR_ENABLE 0x01 177 #define VGA_GFX_COMPARE_VALUE 0x02 178 #define VGA_GFX_DATA_ROTATE 0x03 179 #define VGA_GFX_PLANE_READ 0x04 180 #define VGA_GFX_MODE 0x05 181 #define VGA_GFX_MISC 0x06 182 #define VGA_GFX_COMPARE_MASK 0x07 183 #define VGA_GFX_BIT_MASK 0x08 184 185 /* VGA graphics controller bit masks */ 186 #define VGA_GR06_GRAPHICS_MODE 0x01 187 188 /* macro for composing an 8-bit VGA register index and value 189 * into a single 16-bit quantity */ 190 #define VGA_OUT16VAL(v, r) (((v) << 8) | (r)) 191 192 /* decide whether we should enable the faster 16-bit VGA register writes */ 193 #ifdef __LITTLE_ENDIAN 194 #define VGA_OUTW_WRITE 195 #endif 196 197 /* VGA State Save and Restore */ 198 #define VGA_SAVE_FONT0 1 /* save/restore plane 2 fonts */ 199 #define VGA_SAVE_FONT1 2 /* save/restore plane 3 fonts */ 200 #define VGA_SAVE_TEXT 4 /* save/restore plane 0/1 fonts */ 201 #define VGA_SAVE_FONTS 7 /* save/restore all fonts */ 202 #define VGA_SAVE_MODE 8 /* save/restore video mode */ 203 #define VGA_SAVE_CMAP 16 /* save/restore color map/DAC */ 204 205 struct vgastate { 206 void __iomem *vgabase; /* mmio base, if supported */ 207 unsigned long membase; /* VGA window base, 0 for default - 0xA000 */ 208 __u32 memsize; /* VGA window size, 0 for default 64K */ 209 __u32 flags; /* what state[s] to save (see VGA_SAVE_*) */ 210 __u32 depth; /* current fb depth, not important */ 211 __u32 num_attr; /* number of att registers, 0 for default */ 212 __u32 num_crtc; /* number of crt registers, 0 for default */ 213 __u32 num_gfx; /* number of gfx registers, 0 for default */ 214 __u32 num_seq; /* number of seq registers, 0 for default */ 215 void *vidstate; 216 }; 217 218 extern int save_vga(struct vgastate *state); 219 extern int restore_vga(struct vgastate *state); 220 221 /* 222 * generic VGA port read/write 223 */ 224 225 static inline unsigned char vga_io_r (unsigned short port) 226 { 227 return inb_p(port); 228 } 229 230 static inline void vga_io_w (unsigned short port, unsigned char val) 231 { 232 outb_p(val, port); 233 } 234 235 static inline void vga_io_w_fast (unsigned short port, unsigned char reg, 236 unsigned char val) 237 { 238 outw(VGA_OUT16VAL (val, reg), port); 239 } 240 241 static inline unsigned char vga_mm_r (void __iomem *regbase, unsigned short port) 242 { 243 return readb (regbase + port); 244 } 245 246 static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val) 247 { 248 writeb (val, regbase + port); 249 } 250 251 static inline void vga_mm_w_fast (void __iomem *regbase, unsigned short port, 252 unsigned char reg, unsigned char val) 253 { 254 writew (VGA_OUT16VAL (val, reg), regbase + port); 255 } 256 257 static inline unsigned char vga_r (void __iomem *regbase, unsigned short port) 258 { 259 if (regbase) 260 return vga_mm_r (regbase, port); 261 else 262 return vga_io_r (port); 263 } 264 265 static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val) 266 { 267 if (regbase) 268 vga_mm_w (regbase, port, val); 269 else 270 vga_io_w (port, val); 271 } 272 273 274 static inline void vga_w_fast (void __iomem *regbase, unsigned short port, 275 unsigned char reg, unsigned char val) 276 { 277 if (regbase) 278 vga_mm_w_fast (regbase, port, reg, val); 279 else 280 vga_io_w_fast (port, reg, val); 281 } 282 283 284 /* 285 * VGA CRTC register read/write 286 */ 287 288 static inline unsigned char vga_rcrt (void __iomem *regbase, unsigned char reg) 289 { 290 vga_w (regbase, VGA_CRT_IC, reg); 291 return vga_r (regbase, VGA_CRT_DC); 292 } 293 294 static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) 295 { 296 #ifdef VGA_OUTW_WRITE 297 vga_w_fast (regbase, VGA_CRT_IC, reg, val); 298 #else 299 vga_w (regbase, VGA_CRT_IC, reg); 300 vga_w (regbase, VGA_CRT_DC, val); 301 #endif /* VGA_OUTW_WRITE */ 302 } 303 304 static inline unsigned char vga_io_rcrt (unsigned char reg) 305 { 306 vga_io_w (VGA_CRT_IC, reg); 307 return vga_io_r (VGA_CRT_DC); 308 } 309 310 static inline void vga_io_wcrt (unsigned char reg, unsigned char val) 311 { 312 #ifdef VGA_OUTW_WRITE 313 vga_io_w_fast (VGA_CRT_IC, reg, val); 314 #else 315 vga_io_w (VGA_CRT_IC, reg); 316 vga_io_w (VGA_CRT_DC, val); 317 #endif /* VGA_OUTW_WRITE */ 318 } 319 320 static inline unsigned char vga_mm_rcrt (void __iomem *regbase, unsigned char reg) 321 { 322 vga_mm_w (regbase, VGA_CRT_IC, reg); 323 return vga_mm_r (regbase, VGA_CRT_DC); 324 } 325 326 static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val) 327 { 328 #ifdef VGA_OUTW_WRITE 329 vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val); 330 #else 331 vga_mm_w (regbase, VGA_CRT_IC, reg); 332 vga_mm_w (regbase, VGA_CRT_DC, val); 333 #endif /* VGA_OUTW_WRITE */ 334 } 335 336 337 /* 338 * VGA sequencer register read/write 339 */ 340 341 static inline unsigned char vga_rseq (void __iomem *regbase, unsigned char reg) 342 { 343 vga_w (regbase, VGA_SEQ_I, reg); 344 return vga_r (regbase, VGA_SEQ_D); 345 } 346 347 static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) 348 { 349 #ifdef VGA_OUTW_WRITE 350 vga_w_fast (regbase, VGA_SEQ_I, reg, val); 351 #else 352 vga_w (regbase, VGA_SEQ_I, reg); 353 vga_w (regbase, VGA_SEQ_D, val); 354 #endif /* VGA_OUTW_WRITE */ 355 } 356 357 static inline unsigned char vga_io_rseq (unsigned char reg) 358 { 359 vga_io_w (VGA_SEQ_I, reg); 360 return vga_io_r (VGA_SEQ_D); 361 } 362 363 static inline void vga_io_wseq (unsigned char reg, unsigned char val) 364 { 365 #ifdef VGA_OUTW_WRITE 366 vga_io_w_fast (VGA_SEQ_I, reg, val); 367 #else 368 vga_io_w (VGA_SEQ_I, reg); 369 vga_io_w (VGA_SEQ_D, val); 370 #endif /* VGA_OUTW_WRITE */ 371 } 372 373 static inline unsigned char vga_mm_rseq (void __iomem *regbase, unsigned char reg) 374 { 375 vga_mm_w (regbase, VGA_SEQ_I, reg); 376 return vga_mm_r (regbase, VGA_SEQ_D); 377 } 378 379 static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val) 380 { 381 #ifdef VGA_OUTW_WRITE 382 vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val); 383 #else 384 vga_mm_w (regbase, VGA_SEQ_I, reg); 385 vga_mm_w (regbase, VGA_SEQ_D, val); 386 #endif /* VGA_OUTW_WRITE */ 387 } 388 389 /* 390 * VGA graphics controller register read/write 391 */ 392 393 static inline unsigned char vga_rgfx (void __iomem *regbase, unsigned char reg) 394 { 395 vga_w (regbase, VGA_GFX_I, reg); 396 return vga_r (regbase, VGA_GFX_D); 397 } 398 399 static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) 400 { 401 #ifdef VGA_OUTW_WRITE 402 vga_w_fast (regbase, VGA_GFX_I, reg, val); 403 #else 404 vga_w (regbase, VGA_GFX_I, reg); 405 vga_w (regbase, VGA_GFX_D, val); 406 #endif /* VGA_OUTW_WRITE */ 407 } 408 409 static inline unsigned char vga_io_rgfx (unsigned char reg) 410 { 411 vga_io_w (VGA_GFX_I, reg); 412 return vga_io_r (VGA_GFX_D); 413 } 414 415 static inline void vga_io_wgfx (unsigned char reg, unsigned char val) 416 { 417 #ifdef VGA_OUTW_WRITE 418 vga_io_w_fast (VGA_GFX_I, reg, val); 419 #else 420 vga_io_w (VGA_GFX_I, reg); 421 vga_io_w (VGA_GFX_D, val); 422 #endif /* VGA_OUTW_WRITE */ 423 } 424 425 static inline unsigned char vga_mm_rgfx (void __iomem *regbase, unsigned char reg) 426 { 427 vga_mm_w (regbase, VGA_GFX_I, reg); 428 return vga_mm_r (regbase, VGA_GFX_D); 429 } 430 431 static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val) 432 { 433 #ifdef VGA_OUTW_WRITE 434 vga_mm_w_fast (regbase, VGA_GFX_I, reg, val); 435 #else 436 vga_mm_w (regbase, VGA_GFX_I, reg); 437 vga_mm_w (regbase, VGA_GFX_D, val); 438 #endif /* VGA_OUTW_WRITE */ 439 } 440 441 442 /* 443 * VGA attribute controller register read/write 444 */ 445 446 static inline unsigned char vga_rattr (void __iomem *regbase, unsigned char reg) 447 { 448 vga_w (regbase, VGA_ATT_IW, reg); 449 return vga_r (regbase, VGA_ATT_R); 450 } 451 452 static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) 453 { 454 vga_w (regbase, VGA_ATT_IW, reg); 455 vga_w (regbase, VGA_ATT_W, val); 456 } 457 458 static inline unsigned char vga_io_rattr (unsigned char reg) 459 { 460 vga_io_w (VGA_ATT_IW, reg); 461 return vga_io_r (VGA_ATT_R); 462 } 463 464 static inline void vga_io_wattr (unsigned char reg, unsigned char val) 465 { 466 vga_io_w (VGA_ATT_IW, reg); 467 vga_io_w (VGA_ATT_W, val); 468 } 469 470 static inline unsigned char vga_mm_rattr (void __iomem *regbase, unsigned char reg) 471 { 472 vga_mm_w (regbase, VGA_ATT_IW, reg); 473 return vga_mm_r (regbase, VGA_ATT_R); 474 } 475 476 static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val) 477 { 478 vga_mm_w (regbase, VGA_ATT_IW, reg); 479 vga_mm_w (regbase, VGA_ATT_W, val); 480 } 481 482 #endif /* __linux_video_vga_h__ */ 483