1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2638772c7SLennert Buytenhek /* 3638772c7SLennert Buytenhek * Copyright (C) 2009 Marvell International Ltd. 4638772c7SLennert Buytenhek */ 5638772c7SLennert Buytenhek 6638772c7SLennert Buytenhek #ifndef __ASM_MACH_PXA168FB_H 7638772c7SLennert Buytenhek #define __ASM_MACH_PXA168FB_H 8638772c7SLennert Buytenhek 9638772c7SLennert Buytenhek #include <linux/fb.h> 10638772c7SLennert Buytenhek #include <linux/interrupt.h> 11638772c7SLennert Buytenhek 12638772c7SLennert Buytenhek /* Dumb interface */ 13638772c7SLennert Buytenhek #define PIN_MODE_DUMB_24 0 14638772c7SLennert Buytenhek #define PIN_MODE_DUMB_18_SPI 1 15638772c7SLennert Buytenhek #define PIN_MODE_DUMB_18_GPIO 2 16638772c7SLennert Buytenhek #define PIN_MODE_DUMB_16_SPI 3 17638772c7SLennert Buytenhek #define PIN_MODE_DUMB_16_GPIO 4 18638772c7SLennert Buytenhek #define PIN_MODE_DUMB_12_SPI_GPIO 5 19638772c7SLennert Buytenhek #define PIN_MODE_SMART_18_SPI 6 20638772c7SLennert Buytenhek #define PIN_MODE_SMART_16_SPI 7 21638772c7SLennert Buytenhek #define PIN_MODE_SMART_8_SPI_GPIO 8 22638772c7SLennert Buytenhek 23638772c7SLennert Buytenhek /* Dumb interface pin allocation */ 24638772c7SLennert Buytenhek #define DUMB_MODE_RGB565 0 25638772c7SLennert Buytenhek #define DUMB_MODE_RGB565_UPPER 1 26638772c7SLennert Buytenhek #define DUMB_MODE_RGB666 2 27638772c7SLennert Buytenhek #define DUMB_MODE_RGB666_UPPER 3 28638772c7SLennert Buytenhek #define DUMB_MODE_RGB444 4 29638772c7SLennert Buytenhek #define DUMB_MODE_RGB444_UPPER 5 30638772c7SLennert Buytenhek #define DUMB_MODE_RGB888 6 31638772c7SLennert Buytenhek 32638772c7SLennert Buytenhek /* default fb buffer size WVGA-32bits */ 33638772c7SLennert Buytenhek #define DEFAULT_FB_SIZE (800 * 480 * 4) 34638772c7SLennert Buytenhek 35638772c7SLennert Buytenhek /* 36638772c7SLennert Buytenhek * Buffer pixel format 37638772c7SLennert Buytenhek * bit0 is for rb swap. 38638772c7SLennert Buytenhek * bit12 is for Y UorV swap 39638772c7SLennert Buytenhek */ 40638772c7SLennert Buytenhek #define PIX_FMT_RGB565 0 41638772c7SLennert Buytenhek #define PIX_FMT_BGR565 1 42638772c7SLennert Buytenhek #define PIX_FMT_RGB1555 2 43638772c7SLennert Buytenhek #define PIX_FMT_BGR1555 3 44638772c7SLennert Buytenhek #define PIX_FMT_RGB888PACK 4 45638772c7SLennert Buytenhek #define PIX_FMT_BGR888PACK 5 46638772c7SLennert Buytenhek #define PIX_FMT_RGB888UNPACK 6 47638772c7SLennert Buytenhek #define PIX_FMT_BGR888UNPACK 7 48638772c7SLennert Buytenhek #define PIX_FMT_RGBA888 8 49638772c7SLennert Buytenhek #define PIX_FMT_BGRA888 9 50638772c7SLennert Buytenhek #define PIX_FMT_YUV422PACK 10 51638772c7SLennert Buytenhek #define PIX_FMT_YVU422PACK 11 52638772c7SLennert Buytenhek #define PIX_FMT_YUV422PLANAR 12 53638772c7SLennert Buytenhek #define PIX_FMT_YVU422PLANAR 13 54638772c7SLennert Buytenhek #define PIX_FMT_YUV420PLANAR 14 55638772c7SLennert Buytenhek #define PIX_FMT_YVU420PLANAR 15 56638772c7SLennert Buytenhek #define PIX_FMT_PSEUDOCOLOR 20 57638772c7SLennert Buytenhek #define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK) 58638772c7SLennert Buytenhek 59638772c7SLennert Buytenhek /* 60638772c7SLennert Buytenhek * PXA LCD controller private state. 61638772c7SLennert Buytenhek */ 62638772c7SLennert Buytenhek struct pxa168fb_info { 63638772c7SLennert Buytenhek struct device *dev; 64638772c7SLennert Buytenhek struct clk *clk; 65638772c7SLennert Buytenhek struct fb_info *info; 66638772c7SLennert Buytenhek 67638772c7SLennert Buytenhek void __iomem *reg_base; 68638772c7SLennert Buytenhek dma_addr_t fb_start_dma; 69638772c7SLennert Buytenhek u32 pseudo_palette[16]; 70638772c7SLennert Buytenhek 71638772c7SLennert Buytenhek int pix_fmt; 72638772c7SLennert Buytenhek unsigned is_blanked:1; 73638772c7SLennert Buytenhek unsigned panel_rbswap:1; 74638772c7SLennert Buytenhek unsigned active:1; 75638772c7SLennert Buytenhek }; 76638772c7SLennert Buytenhek 77638772c7SLennert Buytenhek /* 78638772c7SLennert Buytenhek * PXA fb machine information 79638772c7SLennert Buytenhek */ 80638772c7SLennert Buytenhek struct pxa168fb_mach_info { 81638772c7SLennert Buytenhek char id[16]; 82638772c7SLennert Buytenhek 83638772c7SLennert Buytenhek int num_modes; 84638772c7SLennert Buytenhek struct fb_videomode *modes; 85638772c7SLennert Buytenhek 86638772c7SLennert Buytenhek /* 87638772c7SLennert Buytenhek * Pix_fmt 88638772c7SLennert Buytenhek */ 89638772c7SLennert Buytenhek unsigned pix_fmt; 90638772c7SLennert Buytenhek 91638772c7SLennert Buytenhek /* 92638772c7SLennert Buytenhek * I/O pin allocation. 93638772c7SLennert Buytenhek */ 94638772c7SLennert Buytenhek unsigned io_pin_allocation_mode:4; 95638772c7SLennert Buytenhek 96638772c7SLennert Buytenhek /* 97638772c7SLennert Buytenhek * Dumb panel -- assignment of R/G/B component info to the 24 98638772c7SLennert Buytenhek * available external data lanes. 99638772c7SLennert Buytenhek */ 100638772c7SLennert Buytenhek unsigned dumb_mode:4; 101638772c7SLennert Buytenhek unsigned panel_rgb_reverse_lanes:1; 102638772c7SLennert Buytenhek 103638772c7SLennert Buytenhek /* 104638772c7SLennert Buytenhek * Dumb panel -- GPIO output data. 105638772c7SLennert Buytenhek */ 106638772c7SLennert Buytenhek unsigned gpio_output_mask:8; 107638772c7SLennert Buytenhek unsigned gpio_output_data:8; 108638772c7SLennert Buytenhek 109638772c7SLennert Buytenhek /* 110638772c7SLennert Buytenhek * Dumb panel -- configurable output signal polarity. 111638772c7SLennert Buytenhek */ 112638772c7SLennert Buytenhek unsigned invert_composite_blank:1; 113638772c7SLennert Buytenhek unsigned invert_pix_val_ena:1; 114638772c7SLennert Buytenhek unsigned invert_pixclock:1; 115638772c7SLennert Buytenhek unsigned panel_rbswap:1; 116638772c7SLennert Buytenhek unsigned active:1; 117638772c7SLennert Buytenhek unsigned enable_lcd:1; 118638772c7SLennert Buytenhek }; 119638772c7SLennert Buytenhek 120638772c7SLennert Buytenhek #endif /* __ASM_MACH_PXA168FB_H */ 121