xref: /openbmc/linux/include/video/atmel_lcdc.h (revision 8af2c2869fd129bce0d0dfd86c6364c1096f9eff)
114340586SNicolas Ferre /*
214340586SNicolas Ferre  *  Header file for AT91/AT32 LCD Controller
314340586SNicolas Ferre  *
414340586SNicolas Ferre  *  Data structure and register user interface
514340586SNicolas Ferre  *
614340586SNicolas Ferre  *  Copyright (C) 2007 Atmel Corporation
714340586SNicolas Ferre  *
814340586SNicolas Ferre  * This program is free software; you can redistribute it and/or modify
914340586SNicolas Ferre  * it under the terms of the GNU General Public License as published by
1014340586SNicolas Ferre  * the Free Software Foundation; either version 2 of the License, or
1114340586SNicolas Ferre  * (at your option) any later version.
1214340586SNicolas Ferre  *
1314340586SNicolas Ferre  * This program is distributed in the hope that it will be useful,
1414340586SNicolas Ferre  * but WITHOUT ANY WARRANTY; without even the implied warranty of
1514340586SNicolas Ferre  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1614340586SNicolas Ferre  * GNU General Public License for more details.
1714340586SNicolas Ferre  *
1814340586SNicolas Ferre  * You should have received a copy of the GNU General Public License
1914340586SNicolas Ferre  * along with this program; if not, write to the Free Software
2014340586SNicolas Ferre  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2114340586SNicolas Ferre  */
2214340586SNicolas Ferre #ifndef __ATMEL_LCDC_H__
2314340586SNicolas Ferre #define __ATMEL_LCDC_H__
2414340586SNicolas Ferre 
2544ccac13SAdrian Bunk #include <linux/workqueue.h>
26fd085801SNicolas Ferre 
27fd085801SNicolas Ferre /* Way LCD wires are connected to the chip:
28fd085801SNicolas Ferre  * Some Atmel chips use BGR color mode (instead of standard RGB)
29fd085801SNicolas Ferre  * A swapped wiring onboard can bring to RGB mode.
30fd085801SNicolas Ferre  */
31fd085801SNicolas Ferre #define ATMEL_LCDC_WIRING_BGR	0
32fd085801SNicolas Ferre #define ATMEL_LCDC_WIRING_RGB	1
33fd085801SNicolas Ferre 
34fd085801SNicolas Ferre 
35a9a84c37SDavid Brownell  /* LCD Controller info data structure, stored in device platform_data */
36*8af2c286SJean-Christophe PLAGNIOL-VILLARD struct atmel_lcdfb_pdata {
3714340586SNicolas Ferre 	unsigned int		guard_time;
38a9a84c37SDavid Brownell 	bool			lcdcon_is_backlight;
397cdcdb69SAndreas Bießmann 	bool			lcdcon_pol_negative;
40a9a84c37SDavid Brownell 	u8			default_bpp;
41fd085801SNicolas Ferre 	u8			lcd_wiring_mode;
4214340586SNicolas Ferre 	unsigned int		default_lcdcon2;
4314340586SNicolas Ferre 	unsigned int		default_dmacon;
4414340586SNicolas Ferre 	void (*atmel_lcdfb_power_control)(int on);
4514340586SNicolas Ferre 	struct fb_monspecs	*default_monspecs;
4614340586SNicolas Ferre };
4714340586SNicolas Ferre 
4814340586SNicolas Ferre #define ATMEL_LCDC_DMABADDR1	0x00
4914340586SNicolas Ferre #define ATMEL_LCDC_DMABADDR2	0x04
5014340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMPT1	0x08
5114340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMPT2	0x0c
5214340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMADD1	0x10
5314340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMADD2	0x14
5414340586SNicolas Ferre 
5514340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMCFG	0x18
5614340586SNicolas Ferre #define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
5714340586SNicolas Ferre #define	ATMEL_LCDC_BLENGTH_OFFSET	24
5814340586SNicolas Ferre #define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
5914340586SNicolas Ferre 
6014340586SNicolas Ferre #define ATMEL_LCDC_DMACON	0x1c
6114340586SNicolas Ferre #define	ATMEL_LCDC_DMAEN	(0x1 << 0)
6214340586SNicolas Ferre #define	ATMEL_LCDC_DMARST	(0x1 << 1)
6314340586SNicolas Ferre #define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
6414340586SNicolas Ferre #define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
6514340586SNicolas Ferre #define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
6614340586SNicolas Ferre 
6714340586SNicolas Ferre #define ATMEL_LCDC_DMA2DCFG	0x20
6814340586SNicolas Ferre #define		ATMEL_LCDC_ADDRINC_OFFSET	0
6914340586SNicolas Ferre #define		ATMEL_LCDC_ADDRINC		(0xffff)
7014340586SNicolas Ferre #define		ATMEL_LCDC_PIXELOFF_OFFSET	24
7114340586SNicolas Ferre #define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
7214340586SNicolas Ferre 
7314340586SNicolas Ferre #define ATMEL_LCDC_LCDCON1	0x0800
7414340586SNicolas Ferre #define	ATMEL_LCDC_BYPASS	(1     <<  0)
7514340586SNicolas Ferre #define	ATMEL_LCDC_CLKVAL_OFFSET	12
7614340586SNicolas Ferre #define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
7714340586SNicolas Ferre #define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
7814340586SNicolas Ferre 
7914340586SNicolas Ferre #define ATMEL_LCDC_LCDCON2	0x0804
8014340586SNicolas Ferre #define	ATMEL_LCDC_DISTYPE	(3 << 0)
8114340586SNicolas Ferre #define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
8214340586SNicolas Ferre #define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
8314340586SNicolas Ferre #define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
8414340586SNicolas Ferre #define	ATMEL_LCDC_SCANMOD	(1 << 2)
8514340586SNicolas Ferre #define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
8614340586SNicolas Ferre #define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
8714340586SNicolas Ferre #define	ATMEL_LCDC_IFWIDTH	(3 << 3)
8814340586SNicolas Ferre #define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
8914340586SNicolas Ferre #define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
9014340586SNicolas Ferre #define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
9114340586SNicolas Ferre #define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
9214340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
9314340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
9414340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
9514340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
9614340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
9714340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
9814340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
9914340586SNicolas Ferre #define	ATMEL_LCDC_INVVD	(1 << 8)
10014340586SNicolas Ferre #define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
10114340586SNicolas Ferre #define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
10214340586SNicolas Ferre #define	ATMEL_LCDC_INVFRAME	(1 << 9 )
10314340586SNicolas Ferre #define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
10414340586SNicolas Ferre #define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
10514340586SNicolas Ferre #define	ATMEL_LCDC_INVLINE	(1 << 10)
10614340586SNicolas Ferre #define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
10714340586SNicolas Ferre #define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
10814340586SNicolas Ferre #define	ATMEL_LCDC_INVCLK	(1 << 11)
10914340586SNicolas Ferre #define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
11014340586SNicolas Ferre #define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
11114340586SNicolas Ferre #define	ATMEL_LCDC_INVDVAL	(1 << 12)
11214340586SNicolas Ferre #define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
11314340586SNicolas Ferre #define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
11414340586SNicolas Ferre #define	ATMEL_LCDC_CLKMOD	(1 << 15)
11514340586SNicolas Ferre #define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
11614340586SNicolas Ferre #define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
11714340586SNicolas Ferre #define	ATMEL_LCDC_MEMOR	(1 << 31)
11814340586SNicolas Ferre #define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
11914340586SNicolas Ferre #define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
12014340586SNicolas Ferre 
12114340586SNicolas Ferre #define ATMEL_LCDC_TIM1		0x0808
122162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VFP		(0xffU <<  0)
12314340586SNicolas Ferre #define	ATMEL_LCDC_VBP_OFFSET		8
124162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
12514340586SNicolas Ferre #define	ATMEL_LCDC_VPW_OFFSET		16
126162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
12714340586SNicolas Ferre #define	ATMEL_LCDC_VHDLY_OFFSET		24
128162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
12914340586SNicolas Ferre 
13014340586SNicolas Ferre #define ATMEL_LCDC_TIM2		0x080c
131162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_HBP		(0xffU  <<  0)
13214340586SNicolas Ferre #define	ATMEL_LCDC_HPW_OFFSET		8
133162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
13414340586SNicolas Ferre #define	ATMEL_LCDC_HFP_OFFSET		21
135162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
13614340586SNicolas Ferre 
13714340586SNicolas Ferre #define ATMEL_LCDC_LCDFRMCFG	0x0810
13814340586SNicolas Ferre #define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
13914340586SNicolas Ferre #define	ATMEL_LCDC_HOZVAL_OFFSET	21
14014340586SNicolas Ferre #define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
14114340586SNicolas Ferre 
14214340586SNicolas Ferre #define ATMEL_LCDC_FIFO		0x0814
14314340586SNicolas Ferre #define	ATMEL_LCDC_FIFOTH	(0xffff)
14414340586SNicolas Ferre 
14514340586SNicolas Ferre #define ATMEL_LCDC_MVAL		0x0818
14614340586SNicolas Ferre 
14714340586SNicolas Ferre #define ATMEL_LCDC_DP1_2	0x081c
14814340586SNicolas Ferre #define ATMEL_LCDC_DP4_7	0x0820
14914340586SNicolas Ferre #define ATMEL_LCDC_DP3_5	0x0824
15014340586SNicolas Ferre #define ATMEL_LCDC_DP2_3	0x0828
15114340586SNicolas Ferre #define ATMEL_LCDC_DP5_7	0x082c
15214340586SNicolas Ferre #define ATMEL_LCDC_DP3_4	0x0830
15314340586SNicolas Ferre #define ATMEL_LCDC_DP4_5	0x0834
15414340586SNicolas Ferre #define ATMEL_LCDC_DP6_7	0x0838
15514340586SNicolas Ferre #define	ATMEL_LCDC_DP1_2_VAL	(0xff)
15614340586SNicolas Ferre #define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
15714340586SNicolas Ferre #define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
15814340586SNicolas Ferre #define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
15914340586SNicolas Ferre #define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
16014340586SNicolas Ferre #define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
16114340586SNicolas Ferre #define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
16214340586SNicolas Ferre #define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
16314340586SNicolas Ferre 
16414340586SNicolas Ferre #define ATMEL_LCDC_PWRCON	0x083c
16514340586SNicolas Ferre #define	ATMEL_LCDC_PWR		(1    <<  0)
16614340586SNicolas Ferre #define	ATMEL_LCDC_GUARDT_OFFSET	1
16714340586SNicolas Ferre #define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
16814340586SNicolas Ferre #define	ATMEL_LCDC_BUSY		(1    << 31)
16914340586SNicolas Ferre 
17014340586SNicolas Ferre #define ATMEL_LCDC_CONTRAST_CTR	0x0840
17114340586SNicolas Ferre #define	ATMEL_LCDC_PS		(3 << 0)
17214340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV1		(0 << 0)
17314340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV2		(1 << 0)
17414340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV4		(2 << 0)
17514340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV8		(3 << 0)
17614340586SNicolas Ferre #define	ATMEL_LCDC_POL		(1 << 2)
17714340586SNicolas Ferre #define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
17814340586SNicolas Ferre #define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
17914340586SNicolas Ferre #define	ATMEL_LCDC_ENA		(1 << 3)
18014340586SNicolas Ferre #define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
18114340586SNicolas Ferre #define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
18214340586SNicolas Ferre 
18314340586SNicolas Ferre #define ATMEL_LCDC_CONTRAST_VAL	0x0844
18414340586SNicolas Ferre #define	ATMEL_LCDC_CVAL	(0xff)
18514340586SNicolas Ferre 
18614340586SNicolas Ferre #define ATMEL_LCDC_IER		0x0848
18714340586SNicolas Ferre #define ATMEL_LCDC_IDR		0x084c
18814340586SNicolas Ferre #define ATMEL_LCDC_IMR		0x0850
18914340586SNicolas Ferre #define ATMEL_LCDC_ISR		0x0854
19014340586SNicolas Ferre #define ATMEL_LCDC_ICR		0x0858
19114340586SNicolas Ferre #define	ATMEL_LCDC_LNI		(1 << 0)
19214340586SNicolas Ferre #define	ATMEL_LCDC_LSTLNI	(1 << 1)
19314340586SNicolas Ferre #define	ATMEL_LCDC_EOFI		(1 << 2)
19414340586SNicolas Ferre #define	ATMEL_LCDC_UFLWI	(1 << 4)
19514340586SNicolas Ferre #define	ATMEL_LCDC_OWRI		(1 << 5)
19614340586SNicolas Ferre #define	ATMEL_LCDC_MERI		(1 << 6)
19714340586SNicolas Ferre 
19814340586SNicolas Ferre #define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
19914340586SNicolas Ferre 
20014340586SNicolas Ferre #endif /* __ATMEL_LCDC_H__ */
201