xref: /openbmc/linux/include/video/atmel_lcdc.h (revision 44ccac13c7f4728cf2992d49384671a176db74dd)
114340586SNicolas Ferre /*
214340586SNicolas Ferre  *  Header file for AT91/AT32 LCD Controller
314340586SNicolas Ferre  *
414340586SNicolas Ferre  *  Data structure and register user interface
514340586SNicolas Ferre  *
614340586SNicolas Ferre  *  Copyright (C) 2007 Atmel Corporation
714340586SNicolas Ferre  *
814340586SNicolas Ferre  * This program is free software; you can redistribute it and/or modify
914340586SNicolas Ferre  * it under the terms of the GNU General Public License as published by
1014340586SNicolas Ferre  * the Free Software Foundation; either version 2 of the License, or
1114340586SNicolas Ferre  * (at your option) any later version.
1214340586SNicolas Ferre  *
1314340586SNicolas Ferre  * This program is distributed in the hope that it will be useful,
1414340586SNicolas Ferre  * but WITHOUT ANY WARRANTY; without even the implied warranty of
1514340586SNicolas Ferre  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1614340586SNicolas Ferre  * GNU General Public License for more details.
1714340586SNicolas Ferre  *
1814340586SNicolas Ferre  * You should have received a copy of the GNU General Public License
1914340586SNicolas Ferre  * along with this program; if not, write to the Free Software
2014340586SNicolas Ferre  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2114340586SNicolas Ferre  */
2214340586SNicolas Ferre #ifndef __ATMEL_LCDC_H__
2314340586SNicolas Ferre #define __ATMEL_LCDC_H__
2414340586SNicolas Ferre 
25*44ccac13SAdrian Bunk #include <linux/workqueue.h>
26fd085801SNicolas Ferre 
27fd085801SNicolas Ferre /* Way LCD wires are connected to the chip:
28fd085801SNicolas Ferre  * Some Atmel chips use BGR color mode (instead of standard RGB)
29fd085801SNicolas Ferre  * A swapped wiring onboard can bring to RGB mode.
30fd085801SNicolas Ferre  */
31fd085801SNicolas Ferre #define ATMEL_LCDC_WIRING_BGR	0
32fd085801SNicolas Ferre #define ATMEL_LCDC_WIRING_RGB	1
33fd085801SNicolas Ferre 
34fd085801SNicolas Ferre 
35a9a84c37SDavid Brownell  /* LCD Controller info data structure, stored in device platform_data */
3614340586SNicolas Ferre struct atmel_lcdfb_info {
3714340586SNicolas Ferre 	spinlock_t		lock;
3814340586SNicolas Ferre 	struct fb_info		*info;
3914340586SNicolas Ferre 	void __iomem		*mmio;
4014340586SNicolas Ferre 	unsigned long		irq_base;
41d22579b8SNicolas Ferre 	struct work_struct	task;
4214340586SNicolas Ferre 
4314340586SNicolas Ferre 	unsigned int		guard_time;
4414340586SNicolas Ferre 	struct platform_device	*pdev;
4514340586SNicolas Ferre 	struct clk		*bus_clk;
4614340586SNicolas Ferre 	struct clk		*lcdc_clk;
47a9a84c37SDavid Brownell 
48a9a84c37SDavid Brownell #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
49a9a84c37SDavid Brownell 	struct backlight_device	*backlight;
50a9a84c37SDavid Brownell 	u8			bl_power;
51a9a84c37SDavid Brownell #endif
52a9a84c37SDavid Brownell 	bool			lcdcon_is_backlight;
53cf19a37eSDavid Brownell 	u8			saved_lcdcon;
54a9a84c37SDavid Brownell 
55a9a84c37SDavid Brownell 	u8			default_bpp;
56fd085801SNicolas Ferre 	u8			lcd_wiring_mode;
5714340586SNicolas Ferre 	unsigned int		default_lcdcon2;
5814340586SNicolas Ferre 	unsigned int		default_dmacon;
5914340586SNicolas Ferre 	void (*atmel_lcdfb_power_control)(int on);
6014340586SNicolas Ferre 	struct fb_monspecs	*default_monspecs;
6114340586SNicolas Ferre 	u32			pseudo_palette[16];
6214340586SNicolas Ferre };
6314340586SNicolas Ferre 
6414340586SNicolas Ferre #define ATMEL_LCDC_DMABADDR1	0x00
6514340586SNicolas Ferre #define ATMEL_LCDC_DMABADDR2	0x04
6614340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMPT1	0x08
6714340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMPT2	0x0c
6814340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMADD1	0x10
6914340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMADD2	0x14
7014340586SNicolas Ferre 
7114340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMCFG	0x18
7214340586SNicolas Ferre #define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
7314340586SNicolas Ferre #define	ATMEL_LCDC_BLENGTH_OFFSET	24
7414340586SNicolas Ferre #define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
7514340586SNicolas Ferre 
7614340586SNicolas Ferre #define ATMEL_LCDC_DMACON	0x1c
7714340586SNicolas Ferre #define	ATMEL_LCDC_DMAEN	(0x1 << 0)
7814340586SNicolas Ferre #define	ATMEL_LCDC_DMARST	(0x1 << 1)
7914340586SNicolas Ferre #define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
8014340586SNicolas Ferre #define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
8114340586SNicolas Ferre #define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
8214340586SNicolas Ferre 
8314340586SNicolas Ferre #define ATMEL_LCDC_DMA2DCFG	0x20
8414340586SNicolas Ferre #define		ATMEL_LCDC_ADDRINC_OFFSET	0
8514340586SNicolas Ferre #define		ATMEL_LCDC_ADDRINC		(0xffff)
8614340586SNicolas Ferre #define		ATMEL_LCDC_PIXELOFF_OFFSET	24
8714340586SNicolas Ferre #define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
8814340586SNicolas Ferre 
8914340586SNicolas Ferre #define ATMEL_LCDC_LCDCON1	0x0800
9014340586SNicolas Ferre #define	ATMEL_LCDC_BYPASS	(1     <<  0)
9114340586SNicolas Ferre #define	ATMEL_LCDC_CLKVAL_OFFSET	12
9214340586SNicolas Ferre #define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
9314340586SNicolas Ferre #define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
9414340586SNicolas Ferre 
9514340586SNicolas Ferre #define ATMEL_LCDC_LCDCON2	0x0804
9614340586SNicolas Ferre #define	ATMEL_LCDC_DISTYPE	(3 << 0)
9714340586SNicolas Ferre #define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
9814340586SNicolas Ferre #define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
9914340586SNicolas Ferre #define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
10014340586SNicolas Ferre #define	ATMEL_LCDC_SCANMOD	(1 << 2)
10114340586SNicolas Ferre #define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
10214340586SNicolas Ferre #define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
10314340586SNicolas Ferre #define	ATMEL_LCDC_IFWIDTH	(3 << 3)
10414340586SNicolas Ferre #define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
10514340586SNicolas Ferre #define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
10614340586SNicolas Ferre #define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
10714340586SNicolas Ferre #define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
10814340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
10914340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
11014340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
11114340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
11214340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
11314340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
11414340586SNicolas Ferre #define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
11514340586SNicolas Ferre #define	ATMEL_LCDC_INVVD	(1 << 8)
11614340586SNicolas Ferre #define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
11714340586SNicolas Ferre #define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
11814340586SNicolas Ferre #define	ATMEL_LCDC_INVFRAME	(1 << 9 )
11914340586SNicolas Ferre #define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
12014340586SNicolas Ferre #define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
12114340586SNicolas Ferre #define	ATMEL_LCDC_INVLINE	(1 << 10)
12214340586SNicolas Ferre #define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
12314340586SNicolas Ferre #define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
12414340586SNicolas Ferre #define	ATMEL_LCDC_INVCLK	(1 << 11)
12514340586SNicolas Ferre #define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
12614340586SNicolas Ferre #define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
12714340586SNicolas Ferre #define	ATMEL_LCDC_INVDVAL	(1 << 12)
12814340586SNicolas Ferre #define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
12914340586SNicolas Ferre #define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
13014340586SNicolas Ferre #define	ATMEL_LCDC_CLKMOD	(1 << 15)
13114340586SNicolas Ferre #define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
13214340586SNicolas Ferre #define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
13314340586SNicolas Ferre #define	ATMEL_LCDC_MEMOR	(1 << 31)
13414340586SNicolas Ferre #define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
13514340586SNicolas Ferre #define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
13614340586SNicolas Ferre 
13714340586SNicolas Ferre #define ATMEL_LCDC_TIM1		0x0808
138162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VFP		(0xffU <<  0)
13914340586SNicolas Ferre #define	ATMEL_LCDC_VBP_OFFSET		8
140162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
14114340586SNicolas Ferre #define	ATMEL_LCDC_VPW_OFFSET		16
142162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
14314340586SNicolas Ferre #define	ATMEL_LCDC_VHDLY_OFFSET		24
144162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
14514340586SNicolas Ferre 
14614340586SNicolas Ferre #define ATMEL_LCDC_TIM2		0x080c
147162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_HBP		(0xffU  <<  0)
14814340586SNicolas Ferre #define	ATMEL_LCDC_HPW_OFFSET		8
149162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
15014340586SNicolas Ferre #define	ATMEL_LCDC_HFP_OFFSET		21
151162b3a08SHaavard Skinnemoen #define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
15214340586SNicolas Ferre 
15314340586SNicolas Ferre #define ATMEL_LCDC_LCDFRMCFG	0x0810
15414340586SNicolas Ferre #define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
15514340586SNicolas Ferre #define	ATMEL_LCDC_HOZVAL_OFFSET	21
15614340586SNicolas Ferre #define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
15714340586SNicolas Ferre 
15814340586SNicolas Ferre #define ATMEL_LCDC_FIFO		0x0814
15914340586SNicolas Ferre #define	ATMEL_LCDC_FIFOTH	(0xffff)
16014340586SNicolas Ferre 
16114340586SNicolas Ferre #define ATMEL_LCDC_MVAL		0x0818
16214340586SNicolas Ferre 
16314340586SNicolas Ferre #define ATMEL_LCDC_DP1_2	0x081c
16414340586SNicolas Ferre #define ATMEL_LCDC_DP4_7	0x0820
16514340586SNicolas Ferre #define ATMEL_LCDC_DP3_5	0x0824
16614340586SNicolas Ferre #define ATMEL_LCDC_DP2_3	0x0828
16714340586SNicolas Ferre #define ATMEL_LCDC_DP5_7	0x082c
16814340586SNicolas Ferre #define ATMEL_LCDC_DP3_4	0x0830
16914340586SNicolas Ferre #define ATMEL_LCDC_DP4_5	0x0834
17014340586SNicolas Ferre #define ATMEL_LCDC_DP6_7	0x0838
17114340586SNicolas Ferre #define	ATMEL_LCDC_DP1_2_VAL	(0xff)
17214340586SNicolas Ferre #define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
17314340586SNicolas Ferre #define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
17414340586SNicolas Ferre #define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
17514340586SNicolas Ferre #define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
17614340586SNicolas Ferre #define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
17714340586SNicolas Ferre #define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
17814340586SNicolas Ferre #define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
17914340586SNicolas Ferre 
18014340586SNicolas Ferre #define ATMEL_LCDC_PWRCON	0x083c
18114340586SNicolas Ferre #define	ATMEL_LCDC_PWR		(1    <<  0)
18214340586SNicolas Ferre #define	ATMEL_LCDC_GUARDT_OFFSET	1
18314340586SNicolas Ferre #define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
18414340586SNicolas Ferre #define	ATMEL_LCDC_BUSY		(1    << 31)
18514340586SNicolas Ferre 
18614340586SNicolas Ferre #define ATMEL_LCDC_CONTRAST_CTR	0x0840
18714340586SNicolas Ferre #define	ATMEL_LCDC_PS		(3 << 0)
18814340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV1		(0 << 0)
18914340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV2		(1 << 0)
19014340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV4		(2 << 0)
19114340586SNicolas Ferre #define		ATMEL_LCDC_PS_DIV8		(3 << 0)
19214340586SNicolas Ferre #define	ATMEL_LCDC_POL		(1 << 2)
19314340586SNicolas Ferre #define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
19414340586SNicolas Ferre #define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
19514340586SNicolas Ferre #define	ATMEL_LCDC_ENA		(1 << 3)
19614340586SNicolas Ferre #define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
19714340586SNicolas Ferre #define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
19814340586SNicolas Ferre 
19914340586SNicolas Ferre #define ATMEL_LCDC_CONTRAST_VAL	0x0844
20014340586SNicolas Ferre #define	ATMEL_LCDC_CVAL	(0xff)
20114340586SNicolas Ferre 
20214340586SNicolas Ferre #define ATMEL_LCDC_IER		0x0848
20314340586SNicolas Ferre #define ATMEL_LCDC_IDR		0x084c
20414340586SNicolas Ferre #define ATMEL_LCDC_IMR		0x0850
20514340586SNicolas Ferre #define ATMEL_LCDC_ISR		0x0854
20614340586SNicolas Ferre #define ATMEL_LCDC_ICR		0x0858
20714340586SNicolas Ferre #define	ATMEL_LCDC_LNI		(1 << 0)
20814340586SNicolas Ferre #define	ATMEL_LCDC_LSTLNI	(1 << 1)
20914340586SNicolas Ferre #define	ATMEL_LCDC_EOFI		(1 << 2)
21014340586SNicolas Ferre #define	ATMEL_LCDC_UFLWI	(1 << 4)
21114340586SNicolas Ferre #define	ATMEL_LCDC_OWRI		(1 << 5)
21214340586SNicolas Ferre #define	ATMEL_LCDC_MERI		(1 << 6)
21314340586SNicolas Ferre 
21414340586SNicolas Ferre #define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
21514340586SNicolas Ferre 
21614340586SNicolas Ferre #endif /* __ATMEL_LCDC_H__ */
217