1*14340586SNicolas Ferre /* 2*14340586SNicolas Ferre * Header file for AT91/AT32 LCD Controller 3*14340586SNicolas Ferre * 4*14340586SNicolas Ferre * Data structure and register user interface 5*14340586SNicolas Ferre * 6*14340586SNicolas Ferre * Copyright (C) 2007 Atmel Corporation 7*14340586SNicolas Ferre * 8*14340586SNicolas Ferre * This program is free software; you can redistribute it and/or modify 9*14340586SNicolas Ferre * it under the terms of the GNU General Public License as published by 10*14340586SNicolas Ferre * the Free Software Foundation; either version 2 of the License, or 11*14340586SNicolas Ferre * (at your option) any later version. 12*14340586SNicolas Ferre * 13*14340586SNicolas Ferre * This program is distributed in the hope that it will be useful, 14*14340586SNicolas Ferre * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*14340586SNicolas Ferre * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*14340586SNicolas Ferre * GNU General Public License for more details. 17*14340586SNicolas Ferre * 18*14340586SNicolas Ferre * You should have received a copy of the GNU General Public License 19*14340586SNicolas Ferre * along with this program; if not, write to the Free Software 20*14340586SNicolas Ferre * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21*14340586SNicolas Ferre */ 22*14340586SNicolas Ferre #ifndef __ATMEL_LCDC_H__ 23*14340586SNicolas Ferre #define __ATMEL_LCDC_H__ 24*14340586SNicolas Ferre 25*14340586SNicolas Ferre /* LCD Controller info data structure */ 26*14340586SNicolas Ferre struct atmel_lcdfb_info { 27*14340586SNicolas Ferre spinlock_t lock; 28*14340586SNicolas Ferre struct fb_info *info; 29*14340586SNicolas Ferre void __iomem *mmio; 30*14340586SNicolas Ferre unsigned long irq_base; 31*14340586SNicolas Ferre 32*14340586SNicolas Ferre unsigned int guard_time; 33*14340586SNicolas Ferre struct platform_device *pdev; 34*14340586SNicolas Ferre struct clk *bus_clk; 35*14340586SNicolas Ferre struct clk *lcdc_clk; 36*14340586SNicolas Ferre unsigned int default_bpp; 37*14340586SNicolas Ferre unsigned int default_lcdcon2; 38*14340586SNicolas Ferre unsigned int default_dmacon; 39*14340586SNicolas Ferre void (*atmel_lcdfb_power_control)(int on); 40*14340586SNicolas Ferre struct fb_monspecs *default_monspecs; 41*14340586SNicolas Ferre u32 pseudo_palette[16]; 42*14340586SNicolas Ferre }; 43*14340586SNicolas Ferre 44*14340586SNicolas Ferre #define ATMEL_LCDC_DMABADDR1 0x00 45*14340586SNicolas Ferre #define ATMEL_LCDC_DMABADDR2 0x04 46*14340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMPT1 0x08 47*14340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMPT2 0x0c 48*14340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMADD1 0x10 49*14340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMADD2 0x14 50*14340586SNicolas Ferre 51*14340586SNicolas Ferre #define ATMEL_LCDC_DMAFRMCFG 0x18 52*14340586SNicolas Ferre #define ATMEL_LCDC_FRSIZE (0x7fffff << 0) 53*14340586SNicolas Ferre #define ATMEL_LCDC_BLENGTH_OFFSET 24 54*14340586SNicolas Ferre #define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET) 55*14340586SNicolas Ferre 56*14340586SNicolas Ferre #define ATMEL_LCDC_DMACON 0x1c 57*14340586SNicolas Ferre #define ATMEL_LCDC_DMAEN (0x1 << 0) 58*14340586SNicolas Ferre #define ATMEL_LCDC_DMARST (0x1 << 1) 59*14340586SNicolas Ferre #define ATMEL_LCDC_DMABUSY (0x1 << 2) 60*14340586SNicolas Ferre #define ATMEL_LCDC_DMAUPDT (0x1 << 3) 61*14340586SNicolas Ferre #define ATMEL_LCDC_DMA2DEN (0x1 << 4) 62*14340586SNicolas Ferre 63*14340586SNicolas Ferre #define ATMEL_LCDC_DMA2DCFG 0x20 64*14340586SNicolas Ferre #define ATMEL_LCDC_ADDRINC_OFFSET 0 65*14340586SNicolas Ferre #define ATMEL_LCDC_ADDRINC (0xffff) 66*14340586SNicolas Ferre #define ATMEL_LCDC_PIXELOFF_OFFSET 24 67*14340586SNicolas Ferre #define ATMEL_LCDC_PIXELOFF (0x1f << 24) 68*14340586SNicolas Ferre 69*14340586SNicolas Ferre #define ATMEL_LCDC_LCDCON1 0x0800 70*14340586SNicolas Ferre #define ATMEL_LCDC_BYPASS (1 << 0) 71*14340586SNicolas Ferre #define ATMEL_LCDC_CLKVAL_OFFSET 12 72*14340586SNicolas Ferre #define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET) 73*14340586SNicolas Ferre #define ATMEL_LCDC_LINCNT (0x7ff << 21) 74*14340586SNicolas Ferre 75*14340586SNicolas Ferre #define ATMEL_LCDC_LCDCON2 0x0804 76*14340586SNicolas Ferre #define ATMEL_LCDC_DISTYPE (3 << 0) 77*14340586SNicolas Ferre #define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0) 78*14340586SNicolas Ferre #define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0) 79*14340586SNicolas Ferre #define ATMEL_LCDC_DISTYPE_TFT (2 << 0) 80*14340586SNicolas Ferre #define ATMEL_LCDC_SCANMOD (1 << 2) 81*14340586SNicolas Ferre #define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2) 82*14340586SNicolas Ferre #define ATMEL_LCDC_SCANMOD_DUAL (1 << 2) 83*14340586SNicolas Ferre #define ATMEL_LCDC_IFWIDTH (3 << 3) 84*14340586SNicolas Ferre #define ATMEL_LCDC_IFWIDTH_4 (0 << 3) 85*14340586SNicolas Ferre #define ATMEL_LCDC_IFWIDTH_8 (1 << 3) 86*14340586SNicolas Ferre #define ATMEL_LCDC_IFWIDTH_16 (2 << 3) 87*14340586SNicolas Ferre #define ATMEL_LCDC_PIXELSIZE (7 << 5) 88*14340586SNicolas Ferre #define ATMEL_LCDC_PIXELSIZE_1 (0 << 5) 89*14340586SNicolas Ferre #define ATMEL_LCDC_PIXELSIZE_2 (1 << 5) 90*14340586SNicolas Ferre #define ATMEL_LCDC_PIXELSIZE_4 (2 << 5) 91*14340586SNicolas Ferre #define ATMEL_LCDC_PIXELSIZE_8 (3 << 5) 92*14340586SNicolas Ferre #define ATMEL_LCDC_PIXELSIZE_16 (4 << 5) 93*14340586SNicolas Ferre #define ATMEL_LCDC_PIXELSIZE_24 (5 << 5) 94*14340586SNicolas Ferre #define ATMEL_LCDC_PIXELSIZE_32 (6 << 5) 95*14340586SNicolas Ferre #define ATMEL_LCDC_INVVD (1 << 8) 96*14340586SNicolas Ferre #define ATMEL_LCDC_INVVD_NORMAL (0 << 8) 97*14340586SNicolas Ferre #define ATMEL_LCDC_INVVD_INVERTED (1 << 8) 98*14340586SNicolas Ferre #define ATMEL_LCDC_INVFRAME (1 << 9 ) 99*14340586SNicolas Ferre #define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9) 100*14340586SNicolas Ferre #define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9) 101*14340586SNicolas Ferre #define ATMEL_LCDC_INVLINE (1 << 10) 102*14340586SNicolas Ferre #define ATMEL_LCDC_INVLINE_NORMAL (0 << 10) 103*14340586SNicolas Ferre #define ATMEL_LCDC_INVLINE_INVERTED (1 << 10) 104*14340586SNicolas Ferre #define ATMEL_LCDC_INVCLK (1 << 11) 105*14340586SNicolas Ferre #define ATMEL_LCDC_INVCLK_NORMAL (0 << 11) 106*14340586SNicolas Ferre #define ATMEL_LCDC_INVCLK_INVERTED (1 << 11) 107*14340586SNicolas Ferre #define ATMEL_LCDC_INVDVAL (1 << 12) 108*14340586SNicolas Ferre #define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12) 109*14340586SNicolas Ferre #define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12) 110*14340586SNicolas Ferre #define ATMEL_LCDC_CLKMOD (1 << 15) 111*14340586SNicolas Ferre #define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15) 112*14340586SNicolas Ferre #define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15) 113*14340586SNicolas Ferre #define ATMEL_LCDC_MEMOR (1 << 31) 114*14340586SNicolas Ferre #define ATMEL_LCDC_MEMOR_BIG (0 << 31) 115*14340586SNicolas Ferre #define ATMEL_LCDC_MEMOR_LITTLE (1 << 31) 116*14340586SNicolas Ferre 117*14340586SNicolas Ferre #define ATMEL_LCDC_TIM1 0x0808 118*14340586SNicolas Ferre #define ATMEL_LCDC_VFP (0xff << 0) 119*14340586SNicolas Ferre #define ATMEL_LCDC_VBP_OFFSET 8 120*14340586SNicolas Ferre #define ATMEL_LCDC_VBP (0xff << ATMEL_LCDC_VBP_OFFSET) 121*14340586SNicolas Ferre #define ATMEL_LCDC_VPW_OFFSET 16 122*14340586SNicolas Ferre #define ATMEL_LCDC_VPW (0x3f << ATMEL_LCDC_VPW_OFFSET) 123*14340586SNicolas Ferre #define ATMEL_LCDC_VHDLY_OFFSET 24 124*14340586SNicolas Ferre #define ATMEL_LCDC_VHDLY (0xf << ATMEL_LCDC_VHDLY_OFFSET) 125*14340586SNicolas Ferre 126*14340586SNicolas Ferre #define ATMEL_LCDC_TIM2 0x080c 127*14340586SNicolas Ferre #define ATMEL_LCDC_HBP (0xff << 0) 128*14340586SNicolas Ferre #define ATMEL_LCDC_HPW_OFFSET 8 129*14340586SNicolas Ferre #define ATMEL_LCDC_HPW (0x3f << ATMEL_LCDC_HPW_OFFSET) 130*14340586SNicolas Ferre #define ATMEL_LCDC_HFP_OFFSET 21 131*14340586SNicolas Ferre #define ATMEL_LCDC_HFP (0x7ff << ATMEL_LCDC_HFP_OFFSET) 132*14340586SNicolas Ferre 133*14340586SNicolas Ferre #define ATMEL_LCDC_LCDFRMCFG 0x0810 134*14340586SNicolas Ferre #define ATMEL_LCDC_LINEVAL (0x7ff << 0) 135*14340586SNicolas Ferre #define ATMEL_LCDC_HOZVAL_OFFSET 21 136*14340586SNicolas Ferre #define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET) 137*14340586SNicolas Ferre 138*14340586SNicolas Ferre #define ATMEL_LCDC_FIFO 0x0814 139*14340586SNicolas Ferre #define ATMEL_LCDC_FIFOTH (0xffff) 140*14340586SNicolas Ferre 141*14340586SNicolas Ferre #define ATMEL_LCDC_MVAL 0x0818 142*14340586SNicolas Ferre 143*14340586SNicolas Ferre #define ATMEL_LCDC_DP1_2 0x081c 144*14340586SNicolas Ferre #define ATMEL_LCDC_DP4_7 0x0820 145*14340586SNicolas Ferre #define ATMEL_LCDC_DP3_5 0x0824 146*14340586SNicolas Ferre #define ATMEL_LCDC_DP2_3 0x0828 147*14340586SNicolas Ferre #define ATMEL_LCDC_DP5_7 0x082c 148*14340586SNicolas Ferre #define ATMEL_LCDC_DP3_4 0x0830 149*14340586SNicolas Ferre #define ATMEL_LCDC_DP4_5 0x0834 150*14340586SNicolas Ferre #define ATMEL_LCDC_DP6_7 0x0838 151*14340586SNicolas Ferre #define ATMEL_LCDC_DP1_2_VAL (0xff) 152*14340586SNicolas Ferre #define ATMEL_LCDC_DP4_7_VAL (0xfffffff) 153*14340586SNicolas Ferre #define ATMEL_LCDC_DP3_5_VAL (0xfffff) 154*14340586SNicolas Ferre #define ATMEL_LCDC_DP2_3_VAL (0xfff) 155*14340586SNicolas Ferre #define ATMEL_LCDC_DP5_7_VAL (0xfffffff) 156*14340586SNicolas Ferre #define ATMEL_LCDC_DP3_4_VAL (0xffff) 157*14340586SNicolas Ferre #define ATMEL_LCDC_DP4_5_VAL (0xfffff) 158*14340586SNicolas Ferre #define ATMEL_LCDC_DP6_7_VAL (0xfffffff) 159*14340586SNicolas Ferre 160*14340586SNicolas Ferre #define ATMEL_LCDC_PWRCON 0x083c 161*14340586SNicolas Ferre #define ATMEL_LCDC_PWR (1 << 0) 162*14340586SNicolas Ferre #define ATMEL_LCDC_GUARDT_OFFSET 1 163*14340586SNicolas Ferre #define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET) 164*14340586SNicolas Ferre #define ATMEL_LCDC_BUSY (1 << 31) 165*14340586SNicolas Ferre 166*14340586SNicolas Ferre #define ATMEL_LCDC_CONTRAST_CTR 0x0840 167*14340586SNicolas Ferre #define ATMEL_LCDC_PS (3 << 0) 168*14340586SNicolas Ferre #define ATMEL_LCDC_PS_DIV1 (0 << 0) 169*14340586SNicolas Ferre #define ATMEL_LCDC_PS_DIV2 (1 << 0) 170*14340586SNicolas Ferre #define ATMEL_LCDC_PS_DIV4 (2 << 0) 171*14340586SNicolas Ferre #define ATMEL_LCDC_PS_DIV8 (3 << 0) 172*14340586SNicolas Ferre #define ATMEL_LCDC_POL (1 << 2) 173*14340586SNicolas Ferre #define ATMEL_LCDC_POL_NEGATIVE (0 << 2) 174*14340586SNicolas Ferre #define ATMEL_LCDC_POL_POSITIVE (1 << 2) 175*14340586SNicolas Ferre #define ATMEL_LCDC_ENA (1 << 3) 176*14340586SNicolas Ferre #define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3) 177*14340586SNicolas Ferre #define ATMEL_LCDC_ENA_PWMENABLE (1 << 3) 178*14340586SNicolas Ferre 179*14340586SNicolas Ferre #define ATMEL_LCDC_CONTRAST_VAL 0x0844 180*14340586SNicolas Ferre #define ATMEL_LCDC_CVAL (0xff) 181*14340586SNicolas Ferre 182*14340586SNicolas Ferre #define ATMEL_LCDC_IER 0x0848 183*14340586SNicolas Ferre #define ATMEL_LCDC_IDR 0x084c 184*14340586SNicolas Ferre #define ATMEL_LCDC_IMR 0x0850 185*14340586SNicolas Ferre #define ATMEL_LCDC_ISR 0x0854 186*14340586SNicolas Ferre #define ATMEL_LCDC_ICR 0x0858 187*14340586SNicolas Ferre #define ATMEL_LCDC_LNI (1 << 0) 188*14340586SNicolas Ferre #define ATMEL_LCDC_LSTLNI (1 << 1) 189*14340586SNicolas Ferre #define ATMEL_LCDC_EOFI (1 << 2) 190*14340586SNicolas Ferre #define ATMEL_LCDC_UFLWI (1 << 4) 191*14340586SNicolas Ferre #define ATMEL_LCDC_OWRI (1 << 5) 192*14340586SNicolas Ferre #define ATMEL_LCDC_MERI (1 << 6) 193*14340586SNicolas Ferre 194*14340586SNicolas Ferre #define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4)) 195*14340586SNicolas Ferre 196*14340586SNicolas Ferre #endif /* __ATMEL_LCDC_H__ */ 197