1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #ifndef _UFSHCD_H 13 #define _UFSHCD_H 14 15 #include <linux/bitfield.h> 16 #include <linux/blk-crypto-profile.h> 17 #include <linux/blk-mq.h> 18 #include <linux/devfreq.h> 19 #include <linux/msi.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/dma-direction.h> 22 #include <scsi/scsi_device.h> 23 #include <scsi/scsi_host.h> 24 #include <ufs/unipro.h> 25 #include <ufs/ufs.h> 26 #include <ufs/ufs_quirks.h> 27 #include <ufs/ufshci.h> 28 29 #define UFSHCD "ufshcd" 30 31 struct ufs_hba; 32 33 enum dev_cmd_type { 34 DEV_CMD_TYPE_NOP = 0x0, 35 DEV_CMD_TYPE_QUERY = 0x1, 36 DEV_CMD_TYPE_RPMB = 0x2, 37 }; 38 39 enum ufs_event_type { 40 /* uic specific errors */ 41 UFS_EVT_PA_ERR = 0, 42 UFS_EVT_DL_ERR, 43 UFS_EVT_NL_ERR, 44 UFS_EVT_TL_ERR, 45 UFS_EVT_DME_ERR, 46 47 /* fatal errors */ 48 UFS_EVT_AUTO_HIBERN8_ERR, 49 UFS_EVT_FATAL_ERR, 50 UFS_EVT_LINK_STARTUP_FAIL, 51 UFS_EVT_RESUME_ERR, 52 UFS_EVT_SUSPEND_ERR, 53 UFS_EVT_WL_SUSP_ERR, 54 UFS_EVT_WL_RES_ERR, 55 56 /* abnormal events */ 57 UFS_EVT_DEV_RESET, 58 UFS_EVT_HOST_RESET, 59 UFS_EVT_ABORT, 60 61 UFS_EVT_CNT, 62 }; 63 64 /** 65 * struct uic_command - UIC command structure 66 * @command: UIC command 67 * @argument1: UIC command argument 1 68 * @argument2: UIC command argument 2 69 * @argument3: UIC command argument 3 70 * @cmd_active: Indicate if UIC command is outstanding 71 * @done: UIC command completion 72 */ 73 struct uic_command { 74 u32 command; 75 u32 argument1; 76 u32 argument2; 77 u32 argument3; 78 int cmd_active; 79 struct completion done; 80 }; 81 82 /* Used to differentiate the power management options */ 83 enum ufs_pm_op { 84 UFS_RUNTIME_PM, 85 UFS_SYSTEM_PM, 86 UFS_SHUTDOWN_PM, 87 }; 88 89 /* Host <-> Device UniPro Link state */ 90 enum uic_link_state { 91 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 92 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 93 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 94 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ 95 }; 96 97 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) 98 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ 99 UIC_LINK_ACTIVE_STATE) 100 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ 101 UIC_LINK_HIBERN8_STATE) 102 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ 103 UIC_LINK_BROKEN_STATE) 104 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) 105 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ 106 UIC_LINK_ACTIVE_STATE) 107 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ 108 UIC_LINK_HIBERN8_STATE) 109 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ 110 UIC_LINK_BROKEN_STATE) 111 112 #define ufshcd_set_ufs_dev_active(h) \ 113 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) 114 #define ufshcd_set_ufs_dev_sleep(h) \ 115 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) 116 #define ufshcd_set_ufs_dev_poweroff(h) \ 117 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) 118 #define ufshcd_set_ufs_dev_deepsleep(h) \ 119 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) 120 #define ufshcd_is_ufs_dev_active(h) \ 121 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) 122 #define ufshcd_is_ufs_dev_sleep(h) \ 123 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) 124 #define ufshcd_is_ufs_dev_poweroff(h) \ 125 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) 126 #define ufshcd_is_ufs_dev_deepsleep(h) \ 127 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) 128 129 /* 130 * UFS Power management levels. 131 * Each level is in increasing order of power savings, except DeepSleep 132 * which is lower than PowerDown with power on but not PowerDown with 133 * power off. 134 */ 135 enum ufs_pm_level { 136 UFS_PM_LVL_0, 137 UFS_PM_LVL_1, 138 UFS_PM_LVL_2, 139 UFS_PM_LVL_3, 140 UFS_PM_LVL_4, 141 UFS_PM_LVL_5, 142 UFS_PM_LVL_6, 143 UFS_PM_LVL_MAX 144 }; 145 146 struct ufs_pm_lvl_states { 147 enum ufs_dev_pwr_mode dev_state; 148 enum uic_link_state link_state; 149 }; 150 151 /** 152 * struct ufshcd_lrb - local reference block 153 * @utr_descriptor_ptr: UTRD address of the command 154 * @ucd_req_ptr: UCD address of the command 155 * @ucd_rsp_ptr: Response UPIU address for this command 156 * @ucd_prdt_ptr: PRDT address of the command 157 * @utrd_dma_addr: UTRD dma address for debug 158 * @ucd_prdt_dma_addr: PRDT dma address for debug 159 * @ucd_rsp_dma_addr: UPIU response dma address for debug 160 * @ucd_req_dma_addr: UPIU request dma address for debug 161 * @cmd: pointer to SCSI command 162 * @scsi_status: SCSI status of the command 163 * @command_type: SCSI, UFS, Query. 164 * @task_tag: Task tag of the command 165 * @lun: LUN of the command 166 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) 167 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) 168 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) 169 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) 170 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) 171 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) 172 * @data_unit_num: the data unit number for the first block for inline crypto 173 * @req_abort_skip: skip request abort task flag 174 */ 175 struct ufshcd_lrb { 176 struct utp_transfer_req_desc *utr_descriptor_ptr; 177 struct utp_upiu_req *ucd_req_ptr; 178 struct utp_upiu_rsp *ucd_rsp_ptr; 179 struct ufshcd_sg_entry *ucd_prdt_ptr; 180 181 dma_addr_t utrd_dma_addr; 182 dma_addr_t ucd_req_dma_addr; 183 dma_addr_t ucd_rsp_dma_addr; 184 dma_addr_t ucd_prdt_dma_addr; 185 186 struct scsi_cmnd *cmd; 187 int scsi_status; 188 189 int command_type; 190 int task_tag; 191 u8 lun; /* UPIU LUN id field is only 8-bit wide */ 192 bool intr_cmd; 193 ktime_t issue_time_stamp; 194 u64 issue_time_stamp_local_clock; 195 ktime_t compl_time_stamp; 196 u64 compl_time_stamp_local_clock; 197 #ifdef CONFIG_SCSI_UFS_CRYPTO 198 int crypto_key_slot; 199 u64 data_unit_num; 200 #endif 201 202 bool req_abort_skip; 203 }; 204 205 /** 206 * struct ufs_query_req - parameters for building a query request 207 * @query_func: UPIU header query function 208 * @upiu_req: the query request data 209 */ 210 struct ufs_query_req { 211 u8 query_func; 212 struct utp_upiu_query upiu_req; 213 }; 214 215 /** 216 * struct ufs_query_resp - UPIU QUERY 217 * @response: device response code 218 * @upiu_res: query response data 219 */ 220 struct ufs_query_res { 221 struct utp_upiu_query upiu_res; 222 }; 223 224 /** 225 * struct ufs_query - holds relevant data structures for query request 226 * @request: request upiu and function 227 * @descriptor: buffer for sending/receiving descriptor 228 * @response: response upiu and response 229 */ 230 struct ufs_query { 231 struct ufs_query_req request; 232 u8 *descriptor; 233 struct ufs_query_res response; 234 }; 235 236 /** 237 * struct ufs_dev_cmd - all assosiated fields with device management commands 238 * @type: device management command type - Query, NOP OUT 239 * @lock: lock to allow one command at a time 240 * @complete: internal commands completion 241 * @query: Device management query information 242 */ 243 struct ufs_dev_cmd { 244 enum dev_cmd_type type; 245 struct mutex lock; 246 struct completion *complete; 247 struct ufs_query query; 248 }; 249 250 /** 251 * struct ufs_clk_info - UFS clock related info 252 * @list: list headed by hba->clk_list_head 253 * @clk: clock node 254 * @name: clock name 255 * @max_freq: maximum frequency supported by the clock 256 * @min_freq: min frequency that can be used for clock scaling 257 * @curr_freq: indicates the current frequency that it is set to 258 * @keep_link_active: indicates that the clk should not be disabled if 259 * link is active 260 * @enabled: variable to check against multiple enable/disable 261 */ 262 struct ufs_clk_info { 263 struct list_head list; 264 struct clk *clk; 265 const char *name; 266 u32 max_freq; 267 u32 min_freq; 268 u32 curr_freq; 269 bool keep_link_active; 270 bool enabled; 271 }; 272 273 enum ufs_notify_change_status { 274 PRE_CHANGE, 275 POST_CHANGE, 276 }; 277 278 struct ufs_pa_layer_attr { 279 u32 gear_rx; 280 u32 gear_tx; 281 u32 lane_rx; 282 u32 lane_tx; 283 u32 pwr_rx; 284 u32 pwr_tx; 285 u32 hs_rate; 286 }; 287 288 struct ufs_pwr_mode_info { 289 bool is_valid; 290 struct ufs_pa_layer_attr info; 291 }; 292 293 /** 294 * struct ufs_hba_variant_ops - variant specific callbacks 295 * @name: variant name 296 * @init: called when the driver is initialized 297 * @exit: called to cleanup everything done in init 298 * @set_dma_mask: For setting another DMA mask than indicated by the 64AS 299 * capability bit. 300 * @get_ufs_hci_version: called to get UFS HCI version 301 * @clk_scale_notify: notifies that clks are scaled up/down 302 * @setup_clocks: called before touching any of the controller registers 303 * @hce_enable_notify: called before and after HCE enable bit is set to allow 304 * variant specific Uni-Pro initialization. 305 * @link_startup_notify: called before and after Link startup is carried out 306 * to allow variant specific Uni-Pro initialization. 307 * @pwr_change_notify: called before and after a power mode change 308 * is carried out to allow vendor spesific capabilities 309 * to be set. PRE_CHANGE can modify final_params based 310 * on desired_pwr_mode, but POST_CHANGE must not alter 311 * the final_params parameter 312 * @setup_xfer_req: called before any transfer request is issued 313 * to set some things 314 * @setup_task_mgmt: called before any task management request is issued 315 * to set some things 316 * @hibern8_notify: called around hibern8 enter/exit 317 * @apply_dev_quirks: called to apply device specific quirks 318 * @fixup_dev_quirks: called to modify device specific quirks 319 * @suspend: called during host controller PM callback 320 * @resume: called during host controller PM callback 321 * @dbg_register_dump: used to dump controller debug information 322 * @phy_initialization: used to initialize phys 323 * @device_reset: called to issue a reset pulse on the UFS device 324 * @config_scaling_param: called to configure clock scaling parameters 325 * @program_key: program or evict an inline encryption key 326 * @event_notify: called to notify important events 327 * @mcq_config_resource: called to configure MCQ platform resources 328 * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode 329 * @op_runtime_config: called to config Operation and runtime regs Pointers 330 * @get_outstanding_cqs: called to get outstanding completion queues 331 * @config_esi: called to config Event Specific Interrupt 332 */ 333 struct ufs_hba_variant_ops { 334 const char *name; 335 int (*init)(struct ufs_hba *); 336 void (*exit)(struct ufs_hba *); 337 u32 (*get_ufs_hci_version)(struct ufs_hba *); 338 int (*set_dma_mask)(struct ufs_hba *); 339 int (*clk_scale_notify)(struct ufs_hba *, bool, 340 enum ufs_notify_change_status); 341 int (*setup_clocks)(struct ufs_hba *, bool, 342 enum ufs_notify_change_status); 343 int (*hce_enable_notify)(struct ufs_hba *, 344 enum ufs_notify_change_status); 345 int (*link_startup_notify)(struct ufs_hba *, 346 enum ufs_notify_change_status); 347 int (*pwr_change_notify)(struct ufs_hba *, 348 enum ufs_notify_change_status status, 349 struct ufs_pa_layer_attr *desired_pwr_mode, 350 struct ufs_pa_layer_attr *final_params); 351 void (*setup_xfer_req)(struct ufs_hba *hba, int tag, 352 bool is_scsi_cmd); 353 void (*setup_task_mgmt)(struct ufs_hba *, int, u8); 354 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, 355 enum ufs_notify_change_status); 356 int (*apply_dev_quirks)(struct ufs_hba *hba); 357 void (*fixup_dev_quirks)(struct ufs_hba *hba); 358 int (*suspend)(struct ufs_hba *, enum ufs_pm_op, 359 enum ufs_notify_change_status); 360 int (*resume)(struct ufs_hba *, enum ufs_pm_op); 361 void (*dbg_register_dump)(struct ufs_hba *hba); 362 int (*phy_initialization)(struct ufs_hba *); 363 int (*device_reset)(struct ufs_hba *hba); 364 void (*config_scaling_param)(struct ufs_hba *hba, 365 struct devfreq_dev_profile *profile, 366 struct devfreq_simple_ondemand_data *data); 367 int (*program_key)(struct ufs_hba *hba, 368 const union ufs_crypto_cfg_entry *cfg, int slot); 369 void (*event_notify)(struct ufs_hba *hba, 370 enum ufs_event_type evt, void *data); 371 int (*mcq_config_resource)(struct ufs_hba *hba); 372 int (*get_hba_mac)(struct ufs_hba *hba); 373 int (*op_runtime_config)(struct ufs_hba *hba); 374 int (*get_outstanding_cqs)(struct ufs_hba *hba, 375 unsigned long *ocqs); 376 int (*config_esi)(struct ufs_hba *hba); 377 }; 378 379 /* clock gating state */ 380 enum clk_gating_state { 381 CLKS_OFF, 382 CLKS_ON, 383 REQ_CLKS_OFF, 384 REQ_CLKS_ON, 385 }; 386 387 /** 388 * struct ufs_clk_gating - UFS clock gating related info 389 * @gate_work: worker to turn off clocks after some delay as specified in 390 * delay_ms 391 * @ungate_work: worker to turn on clocks that will be used in case of 392 * interrupt context 393 * @state: the current clocks state 394 * @delay_ms: gating delay in ms 395 * @is_suspended: clk gating is suspended when set to 1 which can be used 396 * during suspend/resume 397 * @delay_attr: sysfs attribute to control delay_attr 398 * @enable_attr: sysfs attribute to enable/disable clock gating 399 * @is_enabled: Indicates the current status of clock gating 400 * @is_initialized: Indicates whether clock gating is initialized or not 401 * @active_reqs: number of requests that are pending and should be waited for 402 * completion before gating clocks. 403 * @clk_gating_workq: workqueue for clock gating work. 404 */ 405 struct ufs_clk_gating { 406 struct delayed_work gate_work; 407 struct work_struct ungate_work; 408 enum clk_gating_state state; 409 unsigned long delay_ms; 410 bool is_suspended; 411 struct device_attribute delay_attr; 412 struct device_attribute enable_attr; 413 bool is_enabled; 414 bool is_initialized; 415 int active_reqs; 416 struct workqueue_struct *clk_gating_workq; 417 }; 418 419 /** 420 * struct ufs_clk_scaling - UFS clock scaling related data 421 * @active_reqs: number of requests that are pending. If this is zero when 422 * devfreq ->target() function is called then schedule "suspend_work" to 423 * suspend devfreq. 424 * @tot_busy_t: Total busy time in current polling window 425 * @window_start_t: Start time (in jiffies) of the current polling window 426 * @busy_start_t: Start time of current busy period 427 * @enable_attr: sysfs attribute to enable/disable clock scaling 428 * @saved_pwr_info: UFS power mode may also be changed during scaling and this 429 * one keeps track of previous power mode. 430 * @workq: workqueue to schedule devfreq suspend/resume work 431 * @suspend_work: worker to suspend devfreq 432 * @resume_work: worker to resume devfreq 433 * @min_gear: lowest HS gear to scale down to 434 * @is_enabled: tracks if scaling is currently enabled or not, controlled by 435 * clkscale_enable sysfs node 436 * @is_allowed: tracks if scaling is currently allowed or not, used to block 437 * clock scaling which is not invoked from devfreq governor 438 * @is_initialized: Indicates whether clock scaling is initialized or not 439 * @is_busy_started: tracks if busy period has started or not 440 * @is_suspended: tracks if devfreq is suspended or not 441 */ 442 struct ufs_clk_scaling { 443 int active_reqs; 444 unsigned long tot_busy_t; 445 ktime_t window_start_t; 446 ktime_t busy_start_t; 447 struct device_attribute enable_attr; 448 struct ufs_pa_layer_attr saved_pwr_info; 449 struct workqueue_struct *workq; 450 struct work_struct suspend_work; 451 struct work_struct resume_work; 452 u32 min_gear; 453 bool is_enabled; 454 bool is_allowed; 455 bool is_initialized; 456 bool is_busy_started; 457 bool is_suspended; 458 }; 459 460 #define UFS_EVENT_HIST_LENGTH 8 461 /** 462 * struct ufs_event_hist - keeps history of errors 463 * @pos: index to indicate cyclic buffer position 464 * @val: cyclic buffer for registers value 465 * @tstamp: cyclic buffer for time stamp 466 * @cnt: error counter 467 */ 468 struct ufs_event_hist { 469 int pos; 470 u32 val[UFS_EVENT_HIST_LENGTH]; 471 u64 tstamp[UFS_EVENT_HIST_LENGTH]; 472 unsigned long long cnt; 473 }; 474 475 /** 476 * struct ufs_stats - keeps usage/err statistics 477 * @last_intr_status: record the last interrupt status. 478 * @last_intr_ts: record the last interrupt timestamp. 479 * @hibern8_exit_cnt: Counter to keep track of number of exits, 480 * reset this after link-startup. 481 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. 482 * Clear after the first successful command completion. 483 * @event: array with event history. 484 */ 485 struct ufs_stats { 486 u32 last_intr_status; 487 u64 last_intr_ts; 488 489 u32 hibern8_exit_cnt; 490 u64 last_hibern8_exit_tstamp; 491 struct ufs_event_hist event[UFS_EVT_CNT]; 492 }; 493 494 /** 495 * enum ufshcd_state - UFS host controller state 496 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command 497 * processing. 498 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process 499 * SCSI commands. 500 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. 501 * SCSI commands may be submitted to the controller. 502 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail 503 * newly submitted SCSI commands with error code DID_BAD_TARGET. 504 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery 505 * failed. Fail all SCSI commands with error code DID_ERROR. 506 */ 507 enum ufshcd_state { 508 UFSHCD_STATE_RESET, 509 UFSHCD_STATE_OPERATIONAL, 510 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, 511 UFSHCD_STATE_EH_SCHEDULED_FATAL, 512 UFSHCD_STATE_ERROR, 513 }; 514 515 enum ufshcd_quirks { 516 /* Interrupt aggregation support is broken */ 517 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, 518 519 /* 520 * delay before each dme command is required as the unipro 521 * layer has shown instabilities 522 */ 523 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, 524 525 /* 526 * If UFS host controller is having issue in processing LCC (Line 527 * Control Command) coming from device then enable this quirk. 528 * When this quirk is enabled, host controller driver should disable 529 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 530 * attribute of device to 0). 531 */ 532 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, 533 534 /* 535 * The attribute PA_RXHSUNTERMCAP specifies whether or not the 536 * inbound Link supports unterminated line in HS mode. Setting this 537 * attribute to 1 fixes moving to HS gear. 538 */ 539 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, 540 541 /* 542 * This quirk needs to be enabled if the host controller only allows 543 * accessing the peer dme attributes in AUTO mode (FAST AUTO or 544 * SLOW AUTO). 545 */ 546 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, 547 548 /* 549 * This quirk needs to be enabled if the host controller doesn't 550 * advertise the correct version in UFS_VER register. If this quirk 551 * is enabled, standard UFS host driver will call the vendor specific 552 * ops (get_ufs_hci_version) to get the correct version. 553 */ 554 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, 555 556 /* 557 * Clear handling for transfer/task request list is just opposite. 558 */ 559 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, 560 561 /* 562 * This quirk needs to be enabled if host controller doesn't allow 563 * that the interrupt aggregation timer and counter are reset by s/w. 564 */ 565 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, 566 567 /* 568 * This quirks needs to be enabled if host controller cannot be 569 * enabled via HCE register. 570 */ 571 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, 572 573 /* 574 * This quirk needs to be enabled if the host controller regards 575 * resolution of the values of PRDTO and PRDTL in UTRD as byte. 576 */ 577 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, 578 579 /* 580 * This quirk needs to be enabled if the host controller reports 581 * OCS FATAL ERROR with device error through sense data 582 */ 583 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, 584 585 /* 586 * This quirk needs to be enabled if the host controller has 587 * auto-hibernate capability but it doesn't work. 588 */ 589 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, 590 591 /* 592 * This quirk needs to disable manual flush for write booster 593 */ 594 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, 595 596 /* 597 * This quirk needs to disable unipro timeout values 598 * before power mode change 599 */ 600 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, 601 602 /* 603 * Align DMA SG entries on a 4 KiB boundary. 604 */ 605 UFSHCD_QUIRK_4KB_DMA_ALIGNMENT = 1 << 14, 606 607 /* 608 * This quirk needs to be enabled if the host controller does not 609 * support UIC command 610 */ 611 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, 612 613 /* 614 * This quirk needs to be enabled if the host controller cannot 615 * support physical host configuration. 616 */ 617 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, 618 619 /* 620 * This quirk needs to be enabled if the host controller has 621 * auto-hibernate capability but it's FASTAUTO only. 622 */ 623 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, 624 625 /* 626 * This quirk needs to be enabled if the host controller needs 627 * to reinit the device after switching to maximum gear. 628 */ 629 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, 630 631 /* 632 * Some host raises interrupt (per queue) in addition to 633 * CQES (traditional) when ESI is disabled. 634 * Enable this quirk will disable CQES and use per queue interrupt. 635 */ 636 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20, 637 638 /* 639 * Some host does not implement SQ Run Time Command (SQRTC) register 640 * thus need this quirk to skip related flow. 641 */ 642 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21, 643 }; 644 645 enum ufshcd_caps { 646 /* Allow dynamic clk gating */ 647 UFSHCD_CAP_CLK_GATING = 1 << 0, 648 649 /* Allow hiberb8 with clk gating */ 650 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, 651 652 /* Allow dynamic clk scaling */ 653 UFSHCD_CAP_CLK_SCALING = 1 << 2, 654 655 /* Allow auto bkops to enabled during runtime suspend */ 656 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, 657 658 /* 659 * This capability allows host controller driver to use the UFS HCI's 660 * interrupt aggregation capability. 661 * CAUTION: Enabling this might reduce overall UFS throughput. 662 */ 663 UFSHCD_CAP_INTR_AGGR = 1 << 4, 664 665 /* 666 * This capability allows the device auto-bkops to be always enabled 667 * except during suspend (both runtime and suspend). 668 * Enabling this capability means that device will always be allowed 669 * to do background operation when it's active but it might degrade 670 * the performance of ongoing read/write operations. 671 */ 672 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, 673 674 /* 675 * This capability allows host controller driver to automatically 676 * enable runtime power management by itself instead of waiting 677 * for userspace to control the power management. 678 */ 679 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, 680 681 /* 682 * This capability allows the host controller driver to turn-on 683 * WriteBooster, if the underlying device supports it and is 684 * provisioned to be used. This would increase the write performance. 685 */ 686 UFSHCD_CAP_WB_EN = 1 << 7, 687 688 /* 689 * This capability allows the host controller driver to use the 690 * inline crypto engine, if it is present 691 */ 692 UFSHCD_CAP_CRYPTO = 1 << 8, 693 694 /* 695 * This capability allows the controller regulators to be put into 696 * lpm mode aggressively during clock gating. 697 * This would increase power savings. 698 */ 699 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, 700 701 /* 702 * This capability allows the host controller driver to use DeepSleep, 703 * if it is supported by the UFS device. The host controller driver must 704 * support device hardware reset via the hba->device_reset() callback, 705 * in order to exit DeepSleep state. 706 */ 707 UFSHCD_CAP_DEEPSLEEP = 1 << 10, 708 709 /* 710 * This capability allows the host controller driver to use temperature 711 * notification if it is supported by the UFS device. 712 */ 713 UFSHCD_CAP_TEMP_NOTIF = 1 << 11, 714 715 /* 716 * Enable WriteBooster when scaling up the clock and disable 717 * WriteBooster when scaling the clock down. 718 */ 719 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, 720 }; 721 722 struct ufs_hba_variant_params { 723 struct devfreq_dev_profile devfreq_profile; 724 struct devfreq_simple_ondemand_data ondemand_data; 725 u16 hba_enable_delay_us; 726 u32 wb_flush_threshold; 727 }; 728 729 struct ufs_hba_monitor { 730 unsigned long chunk_size; 731 732 unsigned long nr_sec_rw[2]; 733 ktime_t total_busy[2]; 734 735 unsigned long nr_req[2]; 736 /* latencies*/ 737 ktime_t lat_sum[2]; 738 ktime_t lat_max[2]; 739 ktime_t lat_min[2]; 740 741 u32 nr_queued[2]; 742 ktime_t busy_start_ts[2]; 743 744 ktime_t enabled_ts; 745 bool enabled; 746 }; 747 748 /** 749 * struct ufshcd_res_info_t - MCQ related resource regions 750 * 751 * @name: resource name 752 * @resource: pointer to resource region 753 * @base: register base address 754 */ 755 struct ufshcd_res_info { 756 const char *name; 757 struct resource *resource; 758 void __iomem *base; 759 }; 760 761 enum ufshcd_res { 762 RES_UFS, 763 RES_MCQ, 764 RES_MCQ_SQD, 765 RES_MCQ_SQIS, 766 RES_MCQ_CQD, 767 RES_MCQ_CQIS, 768 RES_MCQ_VS, 769 RES_MAX, 770 }; 771 772 /** 773 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers 774 * 775 * @offset: Doorbell Address Offset 776 * @stride: Steps proportional to queue [0...31] 777 * @base: base address 778 */ 779 struct ufshcd_mcq_opr_info_t { 780 unsigned long offset; 781 unsigned long stride; 782 void __iomem *base; 783 }; 784 785 enum ufshcd_mcq_opr { 786 OPR_SQD, 787 OPR_SQIS, 788 OPR_CQD, 789 OPR_CQIS, 790 OPR_MAX, 791 }; 792 793 /** 794 * struct ufs_hba - per adapter private structure 795 * @mmio_base: UFSHCI base register address 796 * @ucdl_base_addr: UFS Command Descriptor base address 797 * @utrdl_base_addr: UTP Transfer Request Descriptor base address 798 * @utmrdl_base_addr: UTP Task Management Descriptor base address 799 * @ucdl_dma_addr: UFS Command Descriptor DMA address 800 * @utrdl_dma_addr: UTRDL DMA address 801 * @utmrdl_dma_addr: UTMRDL DMA address 802 * @host: Scsi_Host instance of the driver 803 * @dev: device handle 804 * @ufs_device_wlun: WLUN that controls the entire UFS device. 805 * @hwmon_device: device instance registered with the hwmon core. 806 * @curr_dev_pwr_mode: active UFS device power mode. 807 * @uic_link_state: active state of the link to the UFS device. 808 * @rpm_lvl: desired UFS power management level during runtime PM. 809 * @spm_lvl: desired UFS power management level during system PM. 810 * @pm_op_in_progress: whether or not a PM operation is in progress. 811 * @ahit: value of Auto-Hibernate Idle Timer register. 812 * @lrb: local reference block 813 * @outstanding_tasks: Bits representing outstanding task requests 814 * @outstanding_lock: Protects @outstanding_reqs. 815 * @outstanding_reqs: Bits representing outstanding transfer requests 816 * @capabilities: UFS Controller Capabilities 817 * @mcq_capabilities: UFS Multi Circular Queue capabilities 818 * @nutrs: Transfer Request Queue depth supported by controller 819 * @nutmrs: Task Management Queue depth supported by controller 820 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. 821 * @ufs_version: UFS Version to which controller complies 822 * @vops: pointer to variant specific operations 823 * @vps: pointer to variant specific parameters 824 * @priv: pointer to variant specific private data 825 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) 826 * @irq: Irq number of the controller 827 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. 828 * @dev_ref_clk_freq: reference clock frequency 829 * @quirks: bitmask with information about deviations from the UFSHCI standard. 830 * @dev_quirks: bitmask with information about deviations from the UFS standard. 831 * @tmf_tag_set: TMF tag set. 832 * @tmf_queue: Used to allocate TMF tags. 833 * @tmf_rqs: array with pointers to TMF requests while these are in progress. 834 * @active_uic_cmd: handle of active UIC command 835 * @uic_cmd_mutex: mutex for UIC command 836 * @uic_async_done: completion used during UIC processing 837 * @ufshcd_state: UFSHCD state 838 * @eh_flags: Error handling flags 839 * @intr_mask: Interrupt Mask Bits 840 * @ee_ctrl_mask: Exception event control mask 841 * @ee_drv_mask: Exception event mask for driver 842 * @ee_usr_mask: Exception event mask for user (set via debugfs) 843 * @ee_ctrl_mutex: Used to serialize exception event information. 844 * @is_powered: flag to check if HBA is powered 845 * @shutting_down: flag to check if shutdown has been invoked 846 * @host_sem: semaphore used to serialize concurrent contexts 847 * @eh_wq: Workqueue that eh_work works on 848 * @eh_work: Worker to handle UFS errors that require s/w attention 849 * @eeh_work: Worker to handle exception events 850 * @errors: HBA errors 851 * @uic_error: UFS interconnect layer error status 852 * @saved_err: sticky error mask 853 * @saved_uic_err: sticky UIC error mask 854 * @ufs_stats: various error counters 855 * @force_reset: flag to force eh_work perform a full reset 856 * @force_pmc: flag to force a power mode change 857 * @silence_err_logs: flag to silence error logs 858 * @dev_cmd: ufs device management command information 859 * @last_dme_cmd_tstamp: time stamp of the last completed DME command 860 * @nop_out_timeout: NOP OUT timeout value 861 * @dev_info: information about the UFS device 862 * @auto_bkops_enabled: to track whether bkops is enabled in device 863 * @vreg_info: UFS device voltage regulator information 864 * @clk_list_head: UFS host controller clocks list node head 865 * @req_abort_count: number of times ufshcd_abort() has been called 866 * @lanes_per_direction: number of lanes per data direction between the UFS 867 * controller and the UFS device. 868 * @pwr_info: holds current power mode 869 * @max_pwr_info: keeps the device max valid pwm 870 * @clk_gating: information related to clock gating 871 * @caps: bitmask with information about UFS controller capabilities 872 * @devfreq: frequency scaling information owned by the devfreq core 873 * @clk_scaling: frequency scaling information owned by the UFS driver 874 * @system_suspending: system suspend has been started and system resume has 875 * not yet finished. 876 * @is_sys_suspended: UFS device has been suspended because of system suspend 877 * @urgent_bkops_lvl: keeps track of urgent bkops level for device 878 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for 879 * device is known or not. 880 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling 881 * @clk_scaling_lock: used to serialize device commands and clock scaling 882 * @desc_size: descriptor sizes reported by device 883 * @scsi_block_reqs_cnt: reference counting for scsi block requests 884 * @bsg_dev: struct device associated with the BSG queue 885 * @bsg_queue: BSG queue associated with the UFS controller 886 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power 887 * management) after the UFS device has finished a WriteBooster buffer 888 * flush or auto BKOP. 889 * @monitor: statistics about UFS commands 890 * @crypto_capabilities: Content of crypto capabilities register (0x100) 891 * @crypto_cap_array: Array of crypto capabilities 892 * @crypto_cfg_register: Start of the crypto cfg array 893 * @crypto_profile: the crypto profile of this hba (if applicable) 894 * @debugfs_root: UFS controller debugfs root directory 895 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay 896 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore 897 * ee_ctrl_mask 898 * @luns_avail: number of regular and well known LUNs supported by the UFS 899 * device 900 * @nr_hw_queues: number of hardware queues configured 901 * @nr_queues: number of Queues of different queue types 902 * @complete_put: whether or not to call ufshcd_rpm_put() from inside 903 * ufshcd_resume_complete() 904 * @ext_iid_sup: is EXT_IID is supported by UFSHC 905 * @mcq_sup: is mcq supported by UFSHC 906 * @mcq_enabled: is mcq ready to accept requests 907 * @res: array of resource info of MCQ registers 908 * @mcq_base: Multi circular queue registers base address 909 * @uhq: array of supported hardware queues 910 * @dev_cmd_queue: Queue for issuing device management commands 911 */ 912 struct ufs_hba { 913 void __iomem *mmio_base; 914 915 /* Virtual memory reference */ 916 struct utp_transfer_cmd_desc *ucdl_base_addr; 917 struct utp_transfer_req_desc *utrdl_base_addr; 918 struct utp_task_req_desc *utmrdl_base_addr; 919 920 /* DMA memory reference */ 921 dma_addr_t ucdl_dma_addr; 922 dma_addr_t utrdl_dma_addr; 923 dma_addr_t utmrdl_dma_addr; 924 925 struct Scsi_Host *host; 926 struct device *dev; 927 struct scsi_device *ufs_device_wlun; 928 929 #ifdef CONFIG_SCSI_UFS_HWMON 930 struct device *hwmon_device; 931 #endif 932 933 enum ufs_dev_pwr_mode curr_dev_pwr_mode; 934 enum uic_link_state uic_link_state; 935 /* Desired UFS power management level during runtime PM */ 936 enum ufs_pm_level rpm_lvl; 937 /* Desired UFS power management level during system PM */ 938 enum ufs_pm_level spm_lvl; 939 int pm_op_in_progress; 940 941 /* Auto-Hibernate Idle Timer register value */ 942 u32 ahit; 943 944 struct ufshcd_lrb *lrb; 945 946 unsigned long outstanding_tasks; 947 spinlock_t outstanding_lock; 948 unsigned long outstanding_reqs; 949 950 u32 capabilities; 951 int nutrs; 952 u32 mcq_capabilities; 953 int nutmrs; 954 u32 reserved_slot; 955 u32 ufs_version; 956 const struct ufs_hba_variant_ops *vops; 957 struct ufs_hba_variant_params *vps; 958 void *priv; 959 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 960 size_t sg_entry_size; 961 #endif 962 unsigned int irq; 963 bool is_irq_enabled; 964 enum ufs_ref_clk_freq dev_ref_clk_freq; 965 966 unsigned int quirks; /* Deviations from standard UFSHCI spec. */ 967 968 /* Device deviations from standard UFS device spec. */ 969 unsigned int dev_quirks; 970 971 struct blk_mq_tag_set tmf_tag_set; 972 struct request_queue *tmf_queue; 973 struct request **tmf_rqs; 974 975 struct uic_command *active_uic_cmd; 976 struct mutex uic_cmd_mutex; 977 struct completion *uic_async_done; 978 979 enum ufshcd_state ufshcd_state; 980 u32 eh_flags; 981 u32 intr_mask; 982 u16 ee_ctrl_mask; 983 u16 ee_drv_mask; 984 u16 ee_usr_mask; 985 struct mutex ee_ctrl_mutex; 986 bool is_powered; 987 bool shutting_down; 988 struct semaphore host_sem; 989 990 /* Work Queues */ 991 struct workqueue_struct *eh_wq; 992 struct work_struct eh_work; 993 struct work_struct eeh_work; 994 995 /* HBA Errors */ 996 u32 errors; 997 u32 uic_error; 998 u32 saved_err; 999 u32 saved_uic_err; 1000 struct ufs_stats ufs_stats; 1001 bool force_reset; 1002 bool force_pmc; 1003 bool silence_err_logs; 1004 1005 /* Device management request data */ 1006 struct ufs_dev_cmd dev_cmd; 1007 ktime_t last_dme_cmd_tstamp; 1008 int nop_out_timeout; 1009 1010 /* Keeps information of the UFS device connected to this host */ 1011 struct ufs_dev_info dev_info; 1012 bool auto_bkops_enabled; 1013 struct ufs_vreg_info vreg_info; 1014 struct list_head clk_list_head; 1015 1016 /* Number of requests aborts */ 1017 int req_abort_count; 1018 1019 /* Number of lanes available (1 or 2) for Rx/Tx */ 1020 u32 lanes_per_direction; 1021 struct ufs_pa_layer_attr pwr_info; 1022 struct ufs_pwr_mode_info max_pwr_info; 1023 1024 struct ufs_clk_gating clk_gating; 1025 /* Control to enable/disable host capabilities */ 1026 u32 caps; 1027 1028 struct devfreq *devfreq; 1029 struct ufs_clk_scaling clk_scaling; 1030 bool system_suspending; 1031 bool is_sys_suspended; 1032 1033 enum bkops_status urgent_bkops_lvl; 1034 bool is_urgent_bkops_lvl_checked; 1035 1036 struct mutex wb_mutex; 1037 struct rw_semaphore clk_scaling_lock; 1038 atomic_t scsi_block_reqs_cnt; 1039 1040 struct device bsg_dev; 1041 struct request_queue *bsg_queue; 1042 struct delayed_work rpm_dev_flush_recheck_work; 1043 1044 struct ufs_hba_monitor monitor; 1045 1046 #ifdef CONFIG_SCSI_UFS_CRYPTO 1047 union ufs_crypto_capabilities crypto_capabilities; 1048 union ufs_crypto_cap_entry *crypto_cap_array; 1049 u32 crypto_cfg_register; 1050 struct blk_crypto_profile crypto_profile; 1051 #endif 1052 #ifdef CONFIG_DEBUG_FS 1053 struct dentry *debugfs_root; 1054 struct delayed_work debugfs_ee_work; 1055 u32 debugfs_ee_rate_limit_ms; 1056 #endif 1057 u32 luns_avail; 1058 unsigned int nr_hw_queues; 1059 unsigned int nr_queues[HCTX_MAX_TYPES]; 1060 bool complete_put; 1061 bool ext_iid_sup; 1062 bool scsi_host_added; 1063 bool mcq_sup; 1064 bool lsdb_sup; 1065 bool mcq_enabled; 1066 struct ufshcd_res_info res[RES_MAX]; 1067 void __iomem *mcq_base; 1068 struct ufs_hw_queue *uhq; 1069 struct ufs_hw_queue *dev_cmd_queue; 1070 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX]; 1071 }; 1072 1073 /** 1074 * struct ufs_hw_queue - per hardware queue structure 1075 * @mcq_sq_head: base address of submission queue head pointer 1076 * @mcq_sq_tail: base address of submission queue tail pointer 1077 * @mcq_cq_head: base address of completion queue head pointer 1078 * @mcq_cq_tail: base address of completion queue tail pointer 1079 * @sqe_base_addr: submission queue entry base address 1080 * @sqe_dma_addr: submission queue dma address 1081 * @cqe_base_addr: completion queue base address 1082 * @cqe_dma_addr: completion queue dma address 1083 * @max_entries: max number of slots in this hardware queue 1084 * @id: hardware queue ID 1085 * @sq_tp_slot: current slot to which SQ tail pointer is pointing 1086 * @sq_lock: serialize submission queue access 1087 * @cq_tail_slot: current slot to which CQ tail pointer is pointing 1088 * @cq_head_slot: current slot to which CQ head pointer is pointing 1089 * @cq_lock: Synchronize between multiple polling instances 1090 * @sq_mutex: prevent submission queue concurrent access 1091 */ 1092 struct ufs_hw_queue { 1093 void __iomem *mcq_sq_head; 1094 void __iomem *mcq_sq_tail; 1095 void __iomem *mcq_cq_head; 1096 void __iomem *mcq_cq_tail; 1097 1098 struct utp_transfer_req_desc *sqe_base_addr; 1099 dma_addr_t sqe_dma_addr; 1100 struct cq_entry *cqe_base_addr; 1101 dma_addr_t cqe_dma_addr; 1102 u32 max_entries; 1103 u32 id; 1104 u32 sq_tail_slot; 1105 spinlock_t sq_lock; 1106 u32 cq_tail_slot; 1107 u32 cq_head_slot; 1108 spinlock_t cq_lock; 1109 /* prevent concurrent access to submission queue */ 1110 struct mutex sq_mutex; 1111 }; 1112 1113 static inline bool is_mcq_enabled(struct ufs_hba *hba) 1114 { 1115 return hba->mcq_enabled; 1116 } 1117 1118 static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba, 1119 enum ufshcd_mcq_opr opr, int idx) 1120 { 1121 return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx; 1122 } 1123 1124 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 1125 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1126 { 1127 return hba->sg_entry_size; 1128 } 1129 1130 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) 1131 { 1132 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); 1133 hba->sg_entry_size = sg_entry_size; 1134 } 1135 #else 1136 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1137 { 1138 return sizeof(struct ufshcd_sg_entry); 1139 } 1140 1141 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ 1142 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) 1143 #endif 1144 1145 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba) 1146 { 1147 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); 1148 } 1149 1150 /* Returns true if clocks can be gated. Otherwise false */ 1151 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) 1152 { 1153 return hba->caps & UFSHCD_CAP_CLK_GATING; 1154 } 1155 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) 1156 { 1157 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1158 } 1159 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) 1160 { 1161 return hba->caps & UFSHCD_CAP_CLK_SCALING; 1162 } 1163 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 1164 { 1165 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1166 } 1167 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) 1168 { 1169 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; 1170 } 1171 1172 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) 1173 { 1174 return (hba->caps & UFSHCD_CAP_INTR_AGGR) && 1175 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); 1176 } 1177 1178 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) 1179 { 1180 return !!(ufshcd_is_link_hibern8(hba) && 1181 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); 1182 } 1183 1184 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) 1185 { 1186 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && 1187 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); 1188 } 1189 1190 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) 1191 { 1192 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); 1193 } 1194 1195 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) 1196 { 1197 return hba->caps & UFSHCD_CAP_WB_EN; 1198 } 1199 1200 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) 1201 { 1202 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; 1203 } 1204 1205 #define ufsmcq_writel(hba, val, reg) \ 1206 writel((val), (hba)->mcq_base + (reg)) 1207 #define ufsmcq_readl(hba, reg) \ 1208 readl((hba)->mcq_base + (reg)) 1209 1210 #define ufsmcq_writelx(hba, val, reg) \ 1211 writel_relaxed((val), (hba)->mcq_base + (reg)) 1212 #define ufsmcq_readlx(hba, reg) \ 1213 readl_relaxed((hba)->mcq_base + (reg)) 1214 1215 #define ufshcd_writel(hba, val, reg) \ 1216 writel((val), (hba)->mmio_base + (reg)) 1217 #define ufshcd_readl(hba, reg) \ 1218 readl((hba)->mmio_base + (reg)) 1219 1220 /** 1221 * ufshcd_rmwl - perform read/modify/write for a controller register 1222 * @hba: per adapter instance 1223 * @mask: mask to apply on read value 1224 * @val: actual value to write 1225 * @reg: register address 1226 */ 1227 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 1228 { 1229 u32 tmp; 1230 1231 tmp = ufshcd_readl(hba, reg); 1232 tmp &= ~mask; 1233 tmp |= (val & mask); 1234 ufshcd_writel(hba, tmp, reg); 1235 } 1236 1237 int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1238 void ufshcd_dealloc_host(struct ufs_hba *); 1239 int ufshcd_hba_enable(struct ufs_hba *hba); 1240 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); 1241 int ufshcd_link_recovery(struct ufs_hba *hba); 1242 int ufshcd_make_hba_operational(struct ufs_hba *hba); 1243 void ufshcd_remove(struct ufs_hba *); 1244 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); 1245 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); 1246 void ufshcd_delay_us(unsigned long us, unsigned long tolerance); 1247 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); 1248 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); 1249 void ufshcd_hba_stop(struct ufs_hba *hba); 1250 void ufshcd_schedule_eh_work(struct ufs_hba *hba); 1251 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); 1252 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); 1253 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); 1254 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, 1255 struct ufs_hw_queue *hwq); 1256 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); 1257 void ufshcd_mcq_enable_esi(struct ufs_hba *hba); 1258 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); 1259 1260 /** 1261 * ufshcd_set_variant - set variant specific data to the hba 1262 * @hba: per adapter instance 1263 * @variant: pointer to variant specific data 1264 */ 1265 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) 1266 { 1267 BUG_ON(!hba); 1268 hba->priv = variant; 1269 } 1270 1271 /** 1272 * ufshcd_get_variant - get variant specific data from the hba 1273 * @hba: per adapter instance 1274 */ 1275 static inline void *ufshcd_get_variant(struct ufs_hba *hba) 1276 { 1277 BUG_ON(!hba); 1278 return hba->priv; 1279 } 1280 1281 #ifdef CONFIG_PM 1282 extern int ufshcd_runtime_suspend(struct device *dev); 1283 extern int ufshcd_runtime_resume(struct device *dev); 1284 #endif 1285 #ifdef CONFIG_PM_SLEEP 1286 extern int ufshcd_system_suspend(struct device *dev); 1287 extern int ufshcd_system_resume(struct device *dev); 1288 extern int ufshcd_system_freeze(struct device *dev); 1289 extern int ufshcd_system_thaw(struct device *dev); 1290 extern int ufshcd_system_restore(struct device *dev); 1291 #endif 1292 1293 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 1294 int agreed_gear, 1295 int adapt_val); 1296 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 1297 u8 attr_set, u32 mib_val, u8 peer); 1298 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 1299 u32 *mib_val, u8 peer); 1300 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, 1301 struct ufs_pa_layer_attr *desired_pwr_mode); 1302 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); 1303 1304 /* UIC command interfaces for DME primitives */ 1305 #define DME_LOCAL 0 1306 #define DME_PEER 1 1307 #define ATTR_SET_NOR 0 /* NORMAL */ 1308 #define ATTR_SET_ST 1 /* STATIC */ 1309 1310 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 1311 u32 mib_val) 1312 { 1313 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1314 mib_val, DME_LOCAL); 1315 } 1316 1317 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, 1318 u32 mib_val) 1319 { 1320 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1321 mib_val, DME_LOCAL); 1322 } 1323 1324 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 1325 u32 mib_val) 1326 { 1327 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1328 mib_val, DME_PEER); 1329 } 1330 1331 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, 1332 u32 mib_val) 1333 { 1334 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1335 mib_val, DME_PEER); 1336 } 1337 1338 static inline int ufshcd_dme_get(struct ufs_hba *hba, 1339 u32 attr_sel, u32 *mib_val) 1340 { 1341 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 1342 } 1343 1344 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 1345 u32 attr_sel, u32 *mib_val) 1346 { 1347 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 1348 } 1349 1350 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) 1351 { 1352 return (pwr_info->pwr_rx == FAST_MODE || 1353 pwr_info->pwr_rx == FASTAUTO_MODE) && 1354 (pwr_info->pwr_tx == FAST_MODE || 1355 pwr_info->pwr_tx == FASTAUTO_MODE); 1356 } 1357 1358 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) 1359 { 1360 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); 1361 } 1362 1363 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba); 1364 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); 1365 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 1366 const struct ufs_dev_quirk *fixups); 1367 #define SD_ASCII_STD true 1368 #define SD_RAW false 1369 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 1370 u8 **buf, bool ascii); 1371 1372 void ufshcd_hold(struct ufs_hba *hba); 1373 void ufshcd_release(struct ufs_hba *hba); 1374 1375 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); 1376 1377 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); 1378 1379 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); 1380 1381 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); 1382 1383 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 1384 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, 1385 struct ufs_ehs *ehs_rsp, int sg_cnt, 1386 struct scatterlist *sg_list, enum dma_data_direction dir); 1387 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); 1388 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); 1389 int ufshcd_suspend_prepare(struct device *dev); 1390 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); 1391 void ufshcd_resume_complete(struct device *dev); 1392 bool ufshcd_is_hba_active(struct ufs_hba *hba); 1393 1394 /* Wrapper functions for safely calling variant operations */ 1395 static inline int ufshcd_vops_init(struct ufs_hba *hba) 1396 { 1397 if (hba->vops && hba->vops->init) 1398 return hba->vops->init(hba); 1399 1400 return 0; 1401 } 1402 1403 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) 1404 { 1405 if (hba->vops && hba->vops->phy_initialization) 1406 return hba->vops->phy_initialization(hba); 1407 1408 return 0; 1409 } 1410 1411 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; 1412 1413 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1414 const char *prefix); 1415 1416 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); 1417 int ufshcd_write_ee_control(struct ufs_hba *hba); 1418 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 1419 const u16 *other_mask, u16 set, u16 clr); 1420 1421 #endif /* End of Header */ 1422