1*1a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 23a9cf8efSRajeev Kumar /* 39d7dd6cdSRajeev Kumar * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com) 43a9cf8efSRajeev Kumar */ 53a9cf8efSRajeev Kumar 63a9cf8efSRajeev Kumar #ifndef __SOUND_DESIGNWARE_I2S_H 73a9cf8efSRajeev Kumar #define __SOUND_DESIGNWARE_I2S_H 83a9cf8efSRajeev Kumar 93a9cf8efSRajeev Kumar #include <linux/dmaengine.h> 103a9cf8efSRajeev Kumar #include <linux/types.h> 113a9cf8efSRajeev Kumar 123a9cf8efSRajeev Kumar /* 133a9cf8efSRajeev Kumar * struct i2s_clk_config_data - represent i2s clk configuration data 143a9cf8efSRajeev Kumar * @chan_nr: number of channel 153a9cf8efSRajeev Kumar * @data_width: number of bits per sample (8/16/24/32 bit) 163a9cf8efSRajeev Kumar * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz) 173a9cf8efSRajeev Kumar */ 183a9cf8efSRajeev Kumar struct i2s_clk_config_data { 193a9cf8efSRajeev Kumar int chan_nr; 203a9cf8efSRajeev Kumar u32 data_width; 213a9cf8efSRajeev Kumar u32 sample_rate; 223a9cf8efSRajeev Kumar }; 233a9cf8efSRajeev Kumar 243a9cf8efSRajeev Kumar struct dw_i2s_dev; 253a9cf8efSRajeev Kumar 263a9cf8efSRajeev Kumar struct i2s_platform_data { 271d957d86SMaruthi Srinivas Bayyavarapu #define DWC_I2S_PLAY (1 << 0) 281d957d86SMaruthi Srinivas Bayyavarapu #define DWC_I2S_RECORD (1 << 1) 293a9cf8efSRajeev Kumar #define DW_I2S_SLAVE (1 << 2) 303a9cf8efSRajeev Kumar #define DW_I2S_MASTER (1 << 3) 313a9cf8efSRajeev Kumar unsigned int cap; 323a9cf8efSRajeev Kumar int channel; 333a9cf8efSRajeev Kumar u32 snd_fmts; 34e164835aSMaruthi Srinivas Bayyavarapu u32 snd_rates; 35a242cac1SMaruthi Srinivas Bayyavarapu 36286345eeSVijendar Mukunda #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0) 37e164835aSMaruthi Srinivas Bayyavarapu #define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1) 38e164835aSMaruthi Srinivas Bayyavarapu #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2) 39e164835aSMaruthi Srinivas Bayyavarapu unsigned int quirks; 40e164835aSMaruthi Srinivas Bayyavarapu unsigned int i2s_reg_comp1; 413a9cf8efSRajeev Kumar unsigned int i2s_reg_comp2; 423a9cf8efSRajeev Kumar 433a9cf8efSRajeev Kumar void *play_dma_data; 443a9cf8efSRajeev Kumar void *capture_dma_data; 453a9cf8efSRajeev Kumar bool (*filter)(struct dma_chan *chan, void *slave); 463a9cf8efSRajeev Kumar int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); 473a9cf8efSRajeev Kumar int (*i2s_pd_init)(struct dw_i2s_dev *dev); 483a9cf8efSRajeev Kumar }; 493a9cf8efSRajeev Kumar 503a9cf8efSRajeev Kumar struct i2s_dma_data { 513a9cf8efSRajeev Kumar void *data; 523a9cf8efSRajeev Kumar dma_addr_t addr; 533a9cf8efSRajeev Kumar u32 max_burst; 543a9cf8efSRajeev Kumar enum dma_slave_buswidth addr_width; 553a9cf8efSRajeev Kumar bool (*filter)(struct dma_chan *chan, void *slave); 563a9cf8efSRajeev Kumar }; 573a9cf8efSRajeev Kumar 583a9cf8efSRajeev Kumar /* I2S DMA registers */ 593a9cf8efSRajeev Kumar #define I2S_RXDMA 0x01C0 603a9cf8efSRajeev Kumar #define I2S_TXDMA 0x01C8 613a9cf8efSRajeev Kumar 623a9cf8efSRajeev Kumar #define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */ 633a9cf8efSRajeev Kumar #define FOUR_CHANNEL_SUPPORT 4 /* up to 3.1 */ 643a9cf8efSRajeev Kumar #define SIX_CHANNEL_SUPPORT 6 /* up to 5.1 */ 65 #define EIGHT_CHANNEL_SUPPORT 8 /* up to 7.1 */ 66 67 #endif /* __SOUND_DESIGNWARE_I2S_H */ 68