1*9aeba629SKrzysztof Helt #ifndef _ACI_H_ 2*9aeba629SKrzysztof Helt #define _ACI_H_ 3*9aeba629SKrzysztof Helt 4*9aeba629SKrzysztof Helt #define ACI_REG_COMMAND 0 /* write register offset */ 5*9aeba629SKrzysztof Helt #define ACI_REG_STATUS 1 /* read register offset */ 6*9aeba629SKrzysztof Helt #define ACI_REG_BUSY 2 /* busy register offset */ 7*9aeba629SKrzysztof Helt #define ACI_REG_RDS 2 /* PCM20: RDS register offset */ 8*9aeba629SKrzysztof Helt #define ACI_MINTIME 500 /* ACI time out limit */ 9*9aeba629SKrzysztof Helt 10*9aeba629SKrzysztof Helt #define ACI_SET_MUTE 0x0d 11*9aeba629SKrzysztof Helt #define ACI_SET_POWERAMP 0x0f 12*9aeba629SKrzysztof Helt #define ACI_SET_TUNERMUTE 0xa3 13*9aeba629SKrzysztof Helt #define ACI_SET_TUNERMONO 0xa4 14*9aeba629SKrzysztof Helt #define ACI_SET_IDE 0xd0 15*9aeba629SKrzysztof Helt #define ACI_SET_WSS 0xd1 16*9aeba629SKrzysztof Helt #define ACI_SET_SOLOMODE 0xd2 17*9aeba629SKrzysztof Helt #define ACI_SET_PREAMP 0x03 18*9aeba629SKrzysztof Helt #define ACI_GET_PREAMP 0x21 19*9aeba629SKrzysztof Helt #define ACI_WRITE_TUNE 0xa7 20*9aeba629SKrzysztof Helt #define ACI_READ_TUNERSTEREO 0xa8 21*9aeba629SKrzysztof Helt #define ACI_READ_TUNERSTATION 0xa9 22*9aeba629SKrzysztof Helt #define ACI_READ_VERSION 0xf1 23*9aeba629SKrzysztof Helt #define ACI_READ_IDCODE 0xf2 24*9aeba629SKrzysztof Helt #define ACI_INIT 0xff 25*9aeba629SKrzysztof Helt #define ACI_STATUS 0xf0 26*9aeba629SKrzysztof Helt #define ACI_S_GENERAL 0x00 27*9aeba629SKrzysztof Helt #define ACI_ERROR_OP 0xdf 28*9aeba629SKrzysztof Helt 29*9aeba629SKrzysztof Helt /* ACI Mixer */ 30*9aeba629SKrzysztof Helt 31*9aeba629SKrzysztof Helt /* These are the values for the right channel GET registers. 32*9aeba629SKrzysztof Helt Add an offset of 0x01 for the left channel register. 33*9aeba629SKrzysztof Helt (left=right+0x01) */ 34*9aeba629SKrzysztof Helt 35*9aeba629SKrzysztof Helt #define ACI_GET_MASTER 0x03 36*9aeba629SKrzysztof Helt #define ACI_GET_MIC 0x05 37*9aeba629SKrzysztof Helt #define ACI_GET_LINE 0x07 38*9aeba629SKrzysztof Helt #define ACI_GET_CD 0x09 39*9aeba629SKrzysztof Helt #define ACI_GET_SYNTH 0x0b 40*9aeba629SKrzysztof Helt #define ACI_GET_PCM 0x0d 41*9aeba629SKrzysztof Helt #define ACI_GET_LINE1 0x10 /* Radio on PCM20 */ 42*9aeba629SKrzysztof Helt #define ACI_GET_LINE2 0x12 43*9aeba629SKrzysztof Helt 44*9aeba629SKrzysztof Helt #define ACI_GET_EQ1 0x22 /* from Bass ... */ 45*9aeba629SKrzysztof Helt #define ACI_GET_EQ2 0x24 46*9aeba629SKrzysztof Helt #define ACI_GET_EQ3 0x26 47*9aeba629SKrzysztof Helt #define ACI_GET_EQ4 0x28 48*9aeba629SKrzysztof Helt #define ACI_GET_EQ5 0x2a 49*9aeba629SKrzysztof Helt #define ACI_GET_EQ6 0x2c 50*9aeba629SKrzysztof Helt #define ACI_GET_EQ7 0x2e /* ... to Treble */ 51*9aeba629SKrzysztof Helt 52*9aeba629SKrzysztof Helt /* And these are the values for the right channel SET registers. 53*9aeba629SKrzysztof Helt For left channel access you have to add an offset of 0x08. 54*9aeba629SKrzysztof Helt MASTER is an exception, which needs an offset of 0x01 */ 55*9aeba629SKrzysztof Helt 56*9aeba629SKrzysztof Helt #define ACI_SET_MASTER 0x00 57*9aeba629SKrzysztof Helt #define ACI_SET_MIC 0x30 58*9aeba629SKrzysztof Helt #define ACI_SET_LINE 0x31 59*9aeba629SKrzysztof Helt #define ACI_SET_CD 0x34 60*9aeba629SKrzysztof Helt #define ACI_SET_SYNTH 0x33 61*9aeba629SKrzysztof Helt #define ACI_SET_PCM 0x32 62*9aeba629SKrzysztof Helt #define ACI_SET_LINE1 0x35 /* Radio on PCM20 */ 63*9aeba629SKrzysztof Helt #define ACI_SET_LINE2 0x36 64*9aeba629SKrzysztof Helt 65*9aeba629SKrzysztof Helt #define ACI_SET_EQ1 0x40 /* from Bass ... */ 66*9aeba629SKrzysztof Helt #define ACI_SET_EQ2 0x41 67*9aeba629SKrzysztof Helt #define ACI_SET_EQ3 0x42 68*9aeba629SKrzysztof Helt #define ACI_SET_EQ4 0x43 69*9aeba629SKrzysztof Helt #define ACI_SET_EQ5 0x44 70*9aeba629SKrzysztof Helt #define ACI_SET_EQ6 0x45 71*9aeba629SKrzysztof Helt #define ACI_SET_EQ7 0x46 /* ... to Treble */ 72*9aeba629SKrzysztof Helt 73*9aeba629SKrzysztof Helt #endif /* _ACI_H_ */ 74