1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 29aeba629SKrzysztof Helt #ifndef _ACI_H_ 39aeba629SKrzysztof Helt #define _ACI_H_ 49aeba629SKrzysztof Helt 59aeba629SKrzysztof Helt #define ACI_REG_COMMAND 0 /* write register offset */ 69aeba629SKrzysztof Helt #define ACI_REG_STATUS 1 /* read register offset */ 79aeba629SKrzysztof Helt #define ACI_REG_BUSY 2 /* busy register offset */ 89aeba629SKrzysztof Helt #define ACI_REG_RDS 2 /* PCM20: RDS register offset */ 99aeba629SKrzysztof Helt #define ACI_MINTIME 500 /* ACI time out limit */ 109aeba629SKrzysztof Helt 119aeba629SKrzysztof Helt #define ACI_SET_MUTE 0x0d 129aeba629SKrzysztof Helt #define ACI_SET_POWERAMP 0x0f 139aeba629SKrzysztof Helt #define ACI_SET_TUNERMUTE 0xa3 149aeba629SKrzysztof Helt #define ACI_SET_TUNERMONO 0xa4 159aeba629SKrzysztof Helt #define ACI_SET_IDE 0xd0 169aeba629SKrzysztof Helt #define ACI_SET_WSS 0xd1 179aeba629SKrzysztof Helt #define ACI_SET_SOLOMODE 0xd2 189aeba629SKrzysztof Helt #define ACI_SET_PREAMP 0x03 199aeba629SKrzysztof Helt #define ACI_GET_PREAMP 0x21 209aeba629SKrzysztof Helt #define ACI_WRITE_TUNE 0xa7 219aeba629SKrzysztof Helt #define ACI_READ_TUNERSTEREO 0xa8 229aeba629SKrzysztof Helt #define ACI_READ_TUNERSTATION 0xa9 239aeba629SKrzysztof Helt #define ACI_READ_VERSION 0xf1 249aeba629SKrzysztof Helt #define ACI_READ_IDCODE 0xf2 259aeba629SKrzysztof Helt #define ACI_INIT 0xff 269aeba629SKrzysztof Helt #define ACI_STATUS 0xf0 279aeba629SKrzysztof Helt #define ACI_S_GENERAL 0x00 289aeba629SKrzysztof Helt #define ACI_ERROR_OP 0xdf 299aeba629SKrzysztof Helt 309aeba629SKrzysztof Helt /* ACI Mixer */ 319aeba629SKrzysztof Helt 329aeba629SKrzysztof Helt /* These are the values for the right channel GET registers. 339aeba629SKrzysztof Helt Add an offset of 0x01 for the left channel register. 349aeba629SKrzysztof Helt (left=right+0x01) */ 359aeba629SKrzysztof Helt 369aeba629SKrzysztof Helt #define ACI_GET_MASTER 0x03 379aeba629SKrzysztof Helt #define ACI_GET_MIC 0x05 389aeba629SKrzysztof Helt #define ACI_GET_LINE 0x07 399aeba629SKrzysztof Helt #define ACI_GET_CD 0x09 409aeba629SKrzysztof Helt #define ACI_GET_SYNTH 0x0b 419aeba629SKrzysztof Helt #define ACI_GET_PCM 0x0d 429aeba629SKrzysztof Helt #define ACI_GET_LINE1 0x10 /* Radio on PCM20 */ 439aeba629SKrzysztof Helt #define ACI_GET_LINE2 0x12 449aeba629SKrzysztof Helt 459aeba629SKrzysztof Helt #define ACI_GET_EQ1 0x22 /* from Bass ... */ 469aeba629SKrzysztof Helt #define ACI_GET_EQ2 0x24 479aeba629SKrzysztof Helt #define ACI_GET_EQ3 0x26 489aeba629SKrzysztof Helt #define ACI_GET_EQ4 0x28 499aeba629SKrzysztof Helt #define ACI_GET_EQ5 0x2a 509aeba629SKrzysztof Helt #define ACI_GET_EQ6 0x2c 519aeba629SKrzysztof Helt #define ACI_GET_EQ7 0x2e /* ... to Treble */ 529aeba629SKrzysztof Helt 539aeba629SKrzysztof Helt /* And these are the values for the right channel SET registers. 549aeba629SKrzysztof Helt For left channel access you have to add an offset of 0x08. 559aeba629SKrzysztof Helt MASTER is an exception, which needs an offset of 0x01 */ 569aeba629SKrzysztof Helt 579aeba629SKrzysztof Helt #define ACI_SET_MASTER 0x00 589aeba629SKrzysztof Helt #define ACI_SET_MIC 0x30 599aeba629SKrzysztof Helt #define ACI_SET_LINE 0x31 609aeba629SKrzysztof Helt #define ACI_SET_CD 0x34 619aeba629SKrzysztof Helt #define ACI_SET_SYNTH 0x33 629aeba629SKrzysztof Helt #define ACI_SET_PCM 0x32 639aeba629SKrzysztof Helt #define ACI_SET_LINE1 0x35 /* Radio on PCM20 */ 649aeba629SKrzysztof Helt #define ACI_SET_LINE2 0x36 659aeba629SKrzysztof Helt 669aeba629SKrzysztof Helt #define ACI_SET_EQ1 0x40 /* from Bass ... */ 679aeba629SKrzysztof Helt #define ACI_SET_EQ2 0x41 689aeba629SKrzysztof Helt #define ACI_SET_EQ3 0x42 699aeba629SKrzysztof Helt #define ACI_SET_EQ4 0x43 709aeba629SKrzysztof Helt #define ACI_SET_EQ5 0x44 719aeba629SKrzysztof Helt #define ACI_SET_EQ6 0x45 729aeba629SKrzysztof Helt #define ACI_SET_EQ7 0x46 /* ... to Treble */ 739aeba629SKrzysztof Helt 749dc9120cSKrzysztof Helt struct snd_miro_aci { 759dc9120cSKrzysztof Helt unsigned long aci_port; 769dc9120cSKrzysztof Helt int aci_vendor; 779dc9120cSKrzysztof Helt int aci_product; 789dc9120cSKrzysztof Helt int aci_version; 799dc9120cSKrzysztof Helt int aci_amp; 809dc9120cSKrzysztof Helt int aci_preamp; 819dc9120cSKrzysztof Helt int aci_solomode; 829dc9120cSKrzysztof Helt 839dc9120cSKrzysztof Helt struct mutex aci_mutex; 849dc9120cSKrzysztof Helt }; 859dc9120cSKrzysztof Helt 869dc9120cSKrzysztof Helt int snd_aci_cmd(struct snd_miro_aci *aci, int write1, int write2, int write3); 879dc9120cSKrzysztof Helt 889dc9120cSKrzysztof Helt struct snd_miro_aci *snd_aci_get_aci(void); 899dc9120cSKrzysztof Helt 909aeba629SKrzysztof Helt #endif /* _ACI_H_ */ 919dc9120cSKrzysztof Helt 92