1*2afbf43aSAbel Vesa /* SPDX-License-Identifier: GPL-2.0 */ 2*2afbf43aSAbel Vesa /* 3*2afbf43aSAbel Vesa * Copyright (c) 2023, Linaro Limited 4*2afbf43aSAbel Vesa */ 5*2afbf43aSAbel Vesa 6*2afbf43aSAbel Vesa #ifndef __QCOM_ICE_H__ 7*2afbf43aSAbel Vesa #define __QCOM_ICE_H__ 8*2afbf43aSAbel Vesa 9*2afbf43aSAbel Vesa #include <linux/types.h> 10*2afbf43aSAbel Vesa 11*2afbf43aSAbel Vesa struct qcom_ice; 12*2afbf43aSAbel Vesa 13*2afbf43aSAbel Vesa enum qcom_ice_crypto_key_size { 14*2afbf43aSAbel Vesa QCOM_ICE_CRYPTO_KEY_SIZE_INVALID = 0x0, 15*2afbf43aSAbel Vesa QCOM_ICE_CRYPTO_KEY_SIZE_128 = 0x1, 16*2afbf43aSAbel Vesa QCOM_ICE_CRYPTO_KEY_SIZE_192 = 0x2, 17*2afbf43aSAbel Vesa QCOM_ICE_CRYPTO_KEY_SIZE_256 = 0x3, 18*2afbf43aSAbel Vesa QCOM_ICE_CRYPTO_KEY_SIZE_512 = 0x4, 19*2afbf43aSAbel Vesa }; 20*2afbf43aSAbel Vesa 21*2afbf43aSAbel Vesa enum qcom_ice_crypto_alg { 22*2afbf43aSAbel Vesa QCOM_ICE_CRYPTO_ALG_AES_XTS = 0x0, 23*2afbf43aSAbel Vesa QCOM_ICE_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, 24*2afbf43aSAbel Vesa QCOM_ICE_CRYPTO_ALG_AES_ECB = 0x2, 25*2afbf43aSAbel Vesa QCOM_ICE_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, 26*2afbf43aSAbel Vesa }; 27*2afbf43aSAbel Vesa 28*2afbf43aSAbel Vesa int qcom_ice_enable(struct qcom_ice *ice); 29*2afbf43aSAbel Vesa int qcom_ice_resume(struct qcom_ice *ice); 30*2afbf43aSAbel Vesa int qcom_ice_suspend(struct qcom_ice *ice); 31*2afbf43aSAbel Vesa int qcom_ice_program_key(struct qcom_ice *ice, 32*2afbf43aSAbel Vesa u8 algorithm_id, u8 key_size, 33*2afbf43aSAbel Vesa const u8 crypto_key[], u8 data_unit_size, 34*2afbf43aSAbel Vesa int slot); 35*2afbf43aSAbel Vesa int qcom_ice_evict_key(struct qcom_ice *ice, int slot); 36*2afbf43aSAbel Vesa struct qcom_ice *of_qcom_ice_get(struct device *dev); 37*2afbf43aSAbel Vesa #endif /* __QCOM_ICE_H__ */ 38