1*7aa1aa6eSZhao Qiang /* 2*7aa1aa6eSZhao Qiang * Internal header file for UCC FAST unit routines. 3*7aa1aa6eSZhao Qiang * 4*7aa1aa6eSZhao Qiang * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. 5*7aa1aa6eSZhao Qiang * 6*7aa1aa6eSZhao Qiang * Authors: Shlomi Gridish <gridish@freescale.com> 7*7aa1aa6eSZhao Qiang * Li Yang <leoli@freescale.com> 8*7aa1aa6eSZhao Qiang * 9*7aa1aa6eSZhao Qiang * This program is free software; you can redistribute it and/or modify it 10*7aa1aa6eSZhao Qiang * under the terms of the GNU General Public License as published by the 11*7aa1aa6eSZhao Qiang * Free Software Foundation; either version 2 of the License, or (at your 12*7aa1aa6eSZhao Qiang * option) any later version. 13*7aa1aa6eSZhao Qiang */ 14*7aa1aa6eSZhao Qiang #ifndef __UCC_FAST_H__ 15*7aa1aa6eSZhao Qiang #define __UCC_FAST_H__ 16*7aa1aa6eSZhao Qiang 17*7aa1aa6eSZhao Qiang #include <linux/kernel.h> 18*7aa1aa6eSZhao Qiang 19*7aa1aa6eSZhao Qiang #include <soc/fsl/qe/immap_qe.h> 20*7aa1aa6eSZhao Qiang #include <soc/fsl/qe/qe.h> 21*7aa1aa6eSZhao Qiang 22*7aa1aa6eSZhao Qiang #include <soc/fsl/qe/ucc.h> 23*7aa1aa6eSZhao Qiang 24*7aa1aa6eSZhao Qiang /* Receive BD's status */ 25*7aa1aa6eSZhao Qiang #define R_E 0x80000000 /* buffer empty */ 26*7aa1aa6eSZhao Qiang #define R_W 0x20000000 /* wrap bit */ 27*7aa1aa6eSZhao Qiang #define R_I 0x10000000 /* interrupt on reception */ 28*7aa1aa6eSZhao Qiang #define R_L 0x08000000 /* last */ 29*7aa1aa6eSZhao Qiang #define R_F 0x04000000 /* first */ 30*7aa1aa6eSZhao Qiang 31*7aa1aa6eSZhao Qiang /* transmit BD's status */ 32*7aa1aa6eSZhao Qiang #define T_R 0x80000000 /* ready bit */ 33*7aa1aa6eSZhao Qiang #define T_W 0x20000000 /* wrap bit */ 34*7aa1aa6eSZhao Qiang #define T_I 0x10000000 /* interrupt on completion */ 35*7aa1aa6eSZhao Qiang #define T_L 0x08000000 /* last */ 36*7aa1aa6eSZhao Qiang 37*7aa1aa6eSZhao Qiang /* Rx Data buffer must be 4 bytes aligned in most cases */ 38*7aa1aa6eSZhao Qiang #define UCC_FAST_RX_ALIGN 4 39*7aa1aa6eSZhao Qiang #define UCC_FAST_MRBLR_ALIGNMENT 4 40*7aa1aa6eSZhao Qiang #define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8 41*7aa1aa6eSZhao Qiang 42*7aa1aa6eSZhao Qiang /* Sizes */ 43*7aa1aa6eSZhao Qiang #define UCC_FAST_URFS_MIN_VAL 0x88 44*7aa1aa6eSZhao Qiang #define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8 45*7aa1aa6eSZhao Qiang 46*7aa1aa6eSZhao Qiang /* ucc_fast_channel_protocol_mode - UCC FAST mode */ 47*7aa1aa6eSZhao Qiang enum ucc_fast_channel_protocol_mode { 48*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000, 49*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001, 50*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002, 51*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003, 52*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004, 53*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005, 54*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006, 55*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007, 56*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008, 57*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009, 58*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A, 59*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B, 60*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C, 61*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D, 62*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E, 63*7aa1aa6eSZhao Qiang UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F 64*7aa1aa6eSZhao Qiang }; 65*7aa1aa6eSZhao Qiang 66*7aa1aa6eSZhao Qiang /* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */ 67*7aa1aa6eSZhao Qiang enum ucc_fast_transparent_txrx { 68*7aa1aa6eSZhao Qiang UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000, 69*7aa1aa6eSZhao Qiang UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000 70*7aa1aa6eSZhao Qiang }; 71*7aa1aa6eSZhao Qiang 72*7aa1aa6eSZhao Qiang /* UCC fast diagnostic mode */ 73*7aa1aa6eSZhao Qiang enum ucc_fast_diag_mode { 74*7aa1aa6eSZhao Qiang UCC_FAST_DIAGNOSTIC_NORMAL = 0x0, 75*7aa1aa6eSZhao Qiang UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000, 76*7aa1aa6eSZhao Qiang UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000, 77*7aa1aa6eSZhao Qiang UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000 78*7aa1aa6eSZhao Qiang }; 79*7aa1aa6eSZhao Qiang 80*7aa1aa6eSZhao Qiang /* UCC fast Sync length (transparent mode only) */ 81*7aa1aa6eSZhao Qiang enum ucc_fast_sync_len { 82*7aa1aa6eSZhao Qiang UCC_FAST_SYNC_LEN_NOT_USED = 0x0, 83*7aa1aa6eSZhao Qiang UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000, 84*7aa1aa6eSZhao Qiang UCC_FAST_SYNC_LEN_8_BIT = 0x00008000, 85*7aa1aa6eSZhao Qiang UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000 86*7aa1aa6eSZhao Qiang }; 87*7aa1aa6eSZhao Qiang 88*7aa1aa6eSZhao Qiang /* UCC fast RTS mode */ 89*7aa1aa6eSZhao Qiang enum ucc_fast_ready_to_send { 90*7aa1aa6eSZhao Qiang UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000, 91*7aa1aa6eSZhao Qiang UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000 92*7aa1aa6eSZhao Qiang }; 93*7aa1aa6eSZhao Qiang 94*7aa1aa6eSZhao Qiang /* UCC fast receiver decoding mode */ 95*7aa1aa6eSZhao Qiang enum ucc_fast_rx_decoding_method { 96*7aa1aa6eSZhao Qiang UCC_FAST_RX_ENCODING_NRZ = 0x00000000, 97*7aa1aa6eSZhao Qiang UCC_FAST_RX_ENCODING_NRZI = 0x00000800, 98*7aa1aa6eSZhao Qiang UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000, 99*7aa1aa6eSZhao Qiang UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800 100*7aa1aa6eSZhao Qiang }; 101*7aa1aa6eSZhao Qiang 102*7aa1aa6eSZhao Qiang /* UCC fast transmitter encoding mode */ 103*7aa1aa6eSZhao Qiang enum ucc_fast_tx_encoding_method { 104*7aa1aa6eSZhao Qiang UCC_FAST_TX_ENCODING_NRZ = 0x00000000, 105*7aa1aa6eSZhao Qiang UCC_FAST_TX_ENCODING_NRZI = 0x00000100, 106*7aa1aa6eSZhao Qiang UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200, 107*7aa1aa6eSZhao Qiang UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300 108*7aa1aa6eSZhao Qiang }; 109*7aa1aa6eSZhao Qiang 110*7aa1aa6eSZhao Qiang /* UCC fast CRC length */ 111*7aa1aa6eSZhao Qiang enum ucc_fast_transparent_tcrc { 112*7aa1aa6eSZhao Qiang UCC_FAST_16_BIT_CRC = 0x00000000, 113*7aa1aa6eSZhao Qiang UCC_FAST_CRC_RESERVED0 = 0x00000040, 114*7aa1aa6eSZhao Qiang UCC_FAST_32_BIT_CRC = 0x00000080, 115*7aa1aa6eSZhao Qiang UCC_FAST_CRC_RESERVED1 = 0x000000C0 116*7aa1aa6eSZhao Qiang }; 117*7aa1aa6eSZhao Qiang 118*7aa1aa6eSZhao Qiang /* Fast UCC initialization structure */ 119*7aa1aa6eSZhao Qiang struct ucc_fast_info { 120*7aa1aa6eSZhao Qiang int ucc_num; 121*7aa1aa6eSZhao Qiang enum qe_clock rx_clock; 122*7aa1aa6eSZhao Qiang enum qe_clock tx_clock; 123*7aa1aa6eSZhao Qiang u32 regs; 124*7aa1aa6eSZhao Qiang int irq; 125*7aa1aa6eSZhao Qiang u32 uccm_mask; 126*7aa1aa6eSZhao Qiang int bd_mem_part; 127*7aa1aa6eSZhao Qiang int brkpt_support; 128*7aa1aa6eSZhao Qiang int grant_support; 129*7aa1aa6eSZhao Qiang int tsa; 130*7aa1aa6eSZhao Qiang int cdp; 131*7aa1aa6eSZhao Qiang int cds; 132*7aa1aa6eSZhao Qiang int ctsp; 133*7aa1aa6eSZhao Qiang int ctss; 134*7aa1aa6eSZhao Qiang int tci; 135*7aa1aa6eSZhao Qiang int txsy; 136*7aa1aa6eSZhao Qiang int rtsm; 137*7aa1aa6eSZhao Qiang int revd; 138*7aa1aa6eSZhao Qiang int rsyn; 139*7aa1aa6eSZhao Qiang u16 max_rx_buf_length; 140*7aa1aa6eSZhao Qiang u16 urfs; 141*7aa1aa6eSZhao Qiang u16 urfet; 142*7aa1aa6eSZhao Qiang u16 urfset; 143*7aa1aa6eSZhao Qiang u16 utfs; 144*7aa1aa6eSZhao Qiang u16 utfet; 145*7aa1aa6eSZhao Qiang u16 utftt; 146*7aa1aa6eSZhao Qiang u16 ufpt; 147*7aa1aa6eSZhao Qiang enum ucc_fast_channel_protocol_mode mode; 148*7aa1aa6eSZhao Qiang enum ucc_fast_transparent_txrx ttx_trx; 149*7aa1aa6eSZhao Qiang enum ucc_fast_tx_encoding_method tenc; 150*7aa1aa6eSZhao Qiang enum ucc_fast_rx_decoding_method renc; 151*7aa1aa6eSZhao Qiang enum ucc_fast_transparent_tcrc tcrc; 152*7aa1aa6eSZhao Qiang enum ucc_fast_sync_len synl; 153*7aa1aa6eSZhao Qiang }; 154*7aa1aa6eSZhao Qiang 155*7aa1aa6eSZhao Qiang struct ucc_fast_private { 156*7aa1aa6eSZhao Qiang struct ucc_fast_info *uf_info; 157*7aa1aa6eSZhao Qiang struct ucc_fast __iomem *uf_regs; /* a pointer to the UCC regs. */ 158*7aa1aa6eSZhao Qiang u32 __iomem *p_ucce; /* a pointer to the event register in memory. */ 159*7aa1aa6eSZhao Qiang u32 __iomem *p_uccm; /* a pointer to the mask register in memory. */ 160*7aa1aa6eSZhao Qiang #ifdef CONFIG_UGETH_TX_ON_DEMAND 161*7aa1aa6eSZhao Qiang u16 __iomem *p_utodr; /* pointer to the transmit on demand register */ 162*7aa1aa6eSZhao Qiang #endif 163*7aa1aa6eSZhao Qiang int enabled_tx; /* Whether channel is enabled for Tx (ENT) */ 164*7aa1aa6eSZhao Qiang int enabled_rx; /* Whether channel is enabled for Rx (ENR) */ 165*7aa1aa6eSZhao Qiang int stopped_tx; /* Whether channel has been stopped for Tx 166*7aa1aa6eSZhao Qiang (STOP_TX, etc.) */ 167*7aa1aa6eSZhao Qiang int stopped_rx; /* Whether channel has been stopped for Rx */ 168*7aa1aa6eSZhao Qiang u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx 169*7aa1aa6eSZhao Qiang virtual fifo */ 170*7aa1aa6eSZhao Qiang u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx 171*7aa1aa6eSZhao Qiang virtual fifo */ 172*7aa1aa6eSZhao Qiang #ifdef STATISTICS 173*7aa1aa6eSZhao Qiang u32 tx_frames; /* Transmitted frames counter. */ 174*7aa1aa6eSZhao Qiang u32 rx_frames; /* Received frames counter (only frames 175*7aa1aa6eSZhao Qiang passed to application). */ 176*7aa1aa6eSZhao Qiang u32 tx_discarded; /* Discarded tx frames counter (frames that 177*7aa1aa6eSZhao Qiang were discarded by the driver due to errors). 178*7aa1aa6eSZhao Qiang */ 179*7aa1aa6eSZhao Qiang u32 rx_discarded; /* Discarded rx frames counter (frames that 180*7aa1aa6eSZhao Qiang were discarded by the driver due to errors). 181*7aa1aa6eSZhao Qiang */ 182*7aa1aa6eSZhao Qiang #endif /* STATISTICS */ 183*7aa1aa6eSZhao Qiang u16 mrblr; /* maximum receive buffer length */ 184*7aa1aa6eSZhao Qiang }; 185*7aa1aa6eSZhao Qiang 186*7aa1aa6eSZhao Qiang /* ucc_fast_init 187*7aa1aa6eSZhao Qiang * Initializes Fast UCC according to user provided parameters. 188*7aa1aa6eSZhao Qiang * 189*7aa1aa6eSZhao Qiang * uf_info - (In) pointer to the fast UCC info structure. 190*7aa1aa6eSZhao Qiang * uccf_ret - (Out) pointer to the fast UCC structure. 191*7aa1aa6eSZhao Qiang */ 192*7aa1aa6eSZhao Qiang int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret); 193*7aa1aa6eSZhao Qiang 194*7aa1aa6eSZhao Qiang /* ucc_fast_free 195*7aa1aa6eSZhao Qiang * Frees all resources for fast UCC. 196*7aa1aa6eSZhao Qiang * 197*7aa1aa6eSZhao Qiang * uccf - (In) pointer to the fast UCC structure. 198*7aa1aa6eSZhao Qiang */ 199*7aa1aa6eSZhao Qiang void ucc_fast_free(struct ucc_fast_private * uccf); 200*7aa1aa6eSZhao Qiang 201*7aa1aa6eSZhao Qiang /* ucc_fast_enable 202*7aa1aa6eSZhao Qiang * Enables a fast UCC port. 203*7aa1aa6eSZhao Qiang * This routine enables Tx and/or Rx through the General UCC Mode Register. 204*7aa1aa6eSZhao Qiang * 205*7aa1aa6eSZhao Qiang * uccf - (In) pointer to the fast UCC structure. 206*7aa1aa6eSZhao Qiang * mode - (In) TX, RX, or both. 207*7aa1aa6eSZhao Qiang */ 208*7aa1aa6eSZhao Qiang void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode); 209*7aa1aa6eSZhao Qiang 210*7aa1aa6eSZhao Qiang /* ucc_fast_disable 211*7aa1aa6eSZhao Qiang * Disables a fast UCC port. 212*7aa1aa6eSZhao Qiang * This routine disables Tx and/or Rx through the General UCC Mode Register. 213*7aa1aa6eSZhao Qiang * 214*7aa1aa6eSZhao Qiang * uccf - (In) pointer to the fast UCC structure. 215*7aa1aa6eSZhao Qiang * mode - (In) TX, RX, or both. 216*7aa1aa6eSZhao Qiang */ 217*7aa1aa6eSZhao Qiang void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode); 218*7aa1aa6eSZhao Qiang 219*7aa1aa6eSZhao Qiang /* ucc_fast_irq 220*7aa1aa6eSZhao Qiang * Handles interrupts on fast UCC. 221*7aa1aa6eSZhao Qiang * Called from the general interrupt routine to handle interrupts on fast UCC. 222*7aa1aa6eSZhao Qiang * 223*7aa1aa6eSZhao Qiang * uccf - (In) pointer to the fast UCC structure. 224*7aa1aa6eSZhao Qiang */ 225*7aa1aa6eSZhao Qiang void ucc_fast_irq(struct ucc_fast_private * uccf); 226*7aa1aa6eSZhao Qiang 227*7aa1aa6eSZhao Qiang /* ucc_fast_transmit_on_demand 228*7aa1aa6eSZhao Qiang * Immediately forces a poll of the transmitter for data to be sent. 229*7aa1aa6eSZhao Qiang * Typically, the hardware performs a periodic poll for data that the 230*7aa1aa6eSZhao Qiang * transmit routine has set up to be transmitted. In cases where 231*7aa1aa6eSZhao Qiang * this polling cycle is not soon enough, this optional routine can 232*7aa1aa6eSZhao Qiang * be invoked to force a poll right away, instead. Proper use for 233*7aa1aa6eSZhao Qiang * each transmission for which this functionality is desired is to 234*7aa1aa6eSZhao Qiang * call the transmit routine and then this routine right after. 235*7aa1aa6eSZhao Qiang * 236*7aa1aa6eSZhao Qiang * uccf - (In) pointer to the fast UCC structure. 237*7aa1aa6eSZhao Qiang */ 238*7aa1aa6eSZhao Qiang void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf); 239*7aa1aa6eSZhao Qiang 240*7aa1aa6eSZhao Qiang u32 ucc_fast_get_qe_cr_subblock(int uccf_num); 241*7aa1aa6eSZhao Qiang 242*7aa1aa6eSZhao Qiang void ucc_fast_dump_regs(struct ucc_fast_private * uccf); 243*7aa1aa6eSZhao Qiang 244*7aa1aa6eSZhao Qiang #endif /* __UCC_FAST_H__ */ 245