xref: /openbmc/linux/include/media/i2c/adv7604.h (revision c13aca79ff3c4af5fd31a5b2743a90eba6e36a26)
1*ab15d248SHans Verkuil /* SPDX-License-Identifier: GPL-2.0-only */
2b5dcee22SMauro Carvalho Chehab /*
3b5dcee22SMauro Carvalho Chehab  * adv7604 - Analog Devices ADV7604 video decoder driver
4b5dcee22SMauro Carvalho Chehab  *
5b5dcee22SMauro Carvalho Chehab  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6b5dcee22SMauro Carvalho Chehab  */
7b5dcee22SMauro Carvalho Chehab 
8b5dcee22SMauro Carvalho Chehab #ifndef _ADV7604_
9b5dcee22SMauro Carvalho Chehab #define _ADV7604_
10b5dcee22SMauro Carvalho Chehab 
11b5dcee22SMauro Carvalho Chehab #include <linux/types.h>
12b5dcee22SMauro Carvalho Chehab 
13b5dcee22SMauro Carvalho Chehab /* Analog input muxing modes (AFE register 0x02, [2:0]) */
14b5dcee22SMauro Carvalho Chehab enum adv7604_ain_sel {
15b5dcee22SMauro Carvalho Chehab 	ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
16b5dcee22SMauro Carvalho Chehab 	ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
17b5dcee22SMauro Carvalho Chehab 	ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
18b5dcee22SMauro Carvalho Chehab 	ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
19b5dcee22SMauro Carvalho Chehab 	ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
20b5dcee22SMauro Carvalho Chehab };
21b5dcee22SMauro Carvalho Chehab 
22b5dcee22SMauro Carvalho Chehab /*
23b5dcee22SMauro Carvalho Chehab  * Bus rotation and reordering. This is used to specify component reordering on
24b5dcee22SMauro Carvalho Chehab  * the board and describes the components order on the bus when the ADV7604
25b5dcee22SMauro Carvalho Chehab  * outputs RGB.
26b5dcee22SMauro Carvalho Chehab  */
27b5dcee22SMauro Carvalho Chehab enum adv7604_bus_order {
28b5dcee22SMauro Carvalho Chehab 	ADV7604_BUS_ORDER_RGB,		/* No operation	*/
29b5dcee22SMauro Carvalho Chehab 	ADV7604_BUS_ORDER_GRB,		/* Swap 1-2	*/
30b5dcee22SMauro Carvalho Chehab 	ADV7604_BUS_ORDER_RBG,		/* Swap 2-3	*/
31b5dcee22SMauro Carvalho Chehab 	ADV7604_BUS_ORDER_BGR,		/* Swap 1-3	*/
32b5dcee22SMauro Carvalho Chehab 	ADV7604_BUS_ORDER_BRG,		/* Rotate right	*/
33b5dcee22SMauro Carvalho Chehab 	ADV7604_BUS_ORDER_GBR,		/* Rotate left	*/
34b5dcee22SMauro Carvalho Chehab };
35b5dcee22SMauro Carvalho Chehab 
36b5dcee22SMauro Carvalho Chehab /* Input Color Space (IO register 0x02, [7:4]) */
37b5dcee22SMauro Carvalho Chehab enum adv76xx_inp_color_space {
38b5dcee22SMauro Carvalho Chehab 	ADV76XX_INP_COLOR_SPACE_LIM_RGB = 0,
39b5dcee22SMauro Carvalho Chehab 	ADV76XX_INP_COLOR_SPACE_FULL_RGB = 1,
40b5dcee22SMauro Carvalho Chehab 	ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
41b5dcee22SMauro Carvalho Chehab 	ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
42b5dcee22SMauro Carvalho Chehab 	ADV76XX_INP_COLOR_SPACE_XVYCC_601 = 4,
43b5dcee22SMauro Carvalho Chehab 	ADV76XX_INP_COLOR_SPACE_XVYCC_709 = 5,
44b5dcee22SMauro Carvalho Chehab 	ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
45b5dcee22SMauro Carvalho Chehab 	ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
46b5dcee22SMauro Carvalho Chehab 	ADV76XX_INP_COLOR_SPACE_AUTO = 0xf,
47b5dcee22SMauro Carvalho Chehab };
48b5dcee22SMauro Carvalho Chehab 
49b5dcee22SMauro Carvalho Chehab /* Select output format (IO register 0x03, [4:2]) */
50b5dcee22SMauro Carvalho Chehab enum adv7604_op_format_mode_sel {
51b5dcee22SMauro Carvalho Chehab 	ADV7604_OP_FORMAT_MODE0 = 0x00,
52b5dcee22SMauro Carvalho Chehab 	ADV7604_OP_FORMAT_MODE1 = 0x04,
53b5dcee22SMauro Carvalho Chehab 	ADV7604_OP_FORMAT_MODE2 = 0x08,
54b5dcee22SMauro Carvalho Chehab };
55b5dcee22SMauro Carvalho Chehab 
56b5dcee22SMauro Carvalho Chehab enum adv76xx_drive_strength {
57b5dcee22SMauro Carvalho Chehab 	ADV76XX_DR_STR_MEDIUM_LOW = 1,
58b5dcee22SMauro Carvalho Chehab 	ADV76XX_DR_STR_MEDIUM_HIGH = 2,
59b5dcee22SMauro Carvalho Chehab 	ADV76XX_DR_STR_HIGH = 3,
60b5dcee22SMauro Carvalho Chehab };
61b5dcee22SMauro Carvalho Chehab 
62b5dcee22SMauro Carvalho Chehab /* INT1 Configuration (IO register 0x40, [1:0]) */
63b5dcee22SMauro Carvalho Chehab enum adv76xx_int1_config {
64b5dcee22SMauro Carvalho Chehab 	ADV76XX_INT1_CONFIG_OPEN_DRAIN,
65b5dcee22SMauro Carvalho Chehab 	ADV76XX_INT1_CONFIG_ACTIVE_LOW,
66b5dcee22SMauro Carvalho Chehab 	ADV76XX_INT1_CONFIG_ACTIVE_HIGH,
67b5dcee22SMauro Carvalho Chehab 	ADV76XX_INT1_CONFIG_DISABLED,
68b5dcee22SMauro Carvalho Chehab };
69b5dcee22SMauro Carvalho Chehab 
70b5dcee22SMauro Carvalho Chehab enum adv76xx_page {
71b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAGE_IO,
72b5dcee22SMauro Carvalho Chehab 	ADV7604_PAGE_AVLINK,
73b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAGE_CEC,
74b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAGE_INFOFRAME,
75b5dcee22SMauro Carvalho Chehab 	ADV7604_PAGE_ESDP,
76b5dcee22SMauro Carvalho Chehab 	ADV7604_PAGE_DPP,
77b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAGE_AFE,
78b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAGE_REP,
79b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAGE_EDID,
80b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAGE_HDMI,
81b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAGE_TEST,
82b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAGE_CP,
83b5dcee22SMauro Carvalho Chehab 	ADV7604_PAGE_VDP,
84b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAGE_MAX,
85b5dcee22SMauro Carvalho Chehab };
86b5dcee22SMauro Carvalho Chehab 
87b5dcee22SMauro Carvalho Chehab /* Platform dependent definition */
88b5dcee22SMauro Carvalho Chehab struct adv76xx_platform_data {
89b5dcee22SMauro Carvalho Chehab 	/* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
90b5dcee22SMauro Carvalho Chehab 	unsigned disable_pwrdnb:1;
91b5dcee22SMauro Carvalho Chehab 
92b5dcee22SMauro Carvalho Chehab 	/* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
93b5dcee22SMauro Carvalho Chehab 	unsigned disable_cable_det_rst:1;
94b5dcee22SMauro Carvalho Chehab 
95b5dcee22SMauro Carvalho Chehab 	int default_input;
96b5dcee22SMauro Carvalho Chehab 
97b5dcee22SMauro Carvalho Chehab 	/* Analog input muxing mode */
98b5dcee22SMauro Carvalho Chehab 	enum adv7604_ain_sel ain_sel;
99b5dcee22SMauro Carvalho Chehab 
100b5dcee22SMauro Carvalho Chehab 	/* Bus rotation and reordering */
101b5dcee22SMauro Carvalho Chehab 	enum adv7604_bus_order bus_order;
102b5dcee22SMauro Carvalho Chehab 
103b5dcee22SMauro Carvalho Chehab 	/* Select output format mode */
104b5dcee22SMauro Carvalho Chehab 	enum adv7604_op_format_mode_sel op_format_mode_sel;
105b5dcee22SMauro Carvalho Chehab 
106b5dcee22SMauro Carvalho Chehab 	/* Configuration of the INT1 pin */
107b5dcee22SMauro Carvalho Chehab 	enum adv76xx_int1_config int1_config;
108b5dcee22SMauro Carvalho Chehab 
109b5dcee22SMauro Carvalho Chehab 	/* IO register 0x02 */
110b5dcee22SMauro Carvalho Chehab 	unsigned alt_gamma:1;
111b5dcee22SMauro Carvalho Chehab 
112b5dcee22SMauro Carvalho Chehab 	/* IO register 0x05 */
113b5dcee22SMauro Carvalho Chehab 	unsigned blank_data:1;
114b5dcee22SMauro Carvalho Chehab 	unsigned insert_av_codes:1;
115b5dcee22SMauro Carvalho Chehab 	unsigned replicate_av_codes:1;
116b5dcee22SMauro Carvalho Chehab 
117b5dcee22SMauro Carvalho Chehab 	/* IO register 0x06 */
118b5dcee22SMauro Carvalho Chehab 	unsigned inv_vs_pol:1;
119b5dcee22SMauro Carvalho Chehab 	unsigned inv_hs_pol:1;
120b5dcee22SMauro Carvalho Chehab 	unsigned inv_llc_pol:1;
121b5dcee22SMauro Carvalho Chehab 
122b5dcee22SMauro Carvalho Chehab 	/* IO register 0x14 */
123b5dcee22SMauro Carvalho Chehab 	enum adv76xx_drive_strength dr_str_data;
124b5dcee22SMauro Carvalho Chehab 	enum adv76xx_drive_strength dr_str_clk;
125b5dcee22SMauro Carvalho Chehab 	enum adv76xx_drive_strength dr_str_sync;
126b5dcee22SMauro Carvalho Chehab 
127b5dcee22SMauro Carvalho Chehab 	/* IO register 0x30 */
128b5dcee22SMauro Carvalho Chehab 	unsigned output_bus_lsb_to_msb:1;
129b5dcee22SMauro Carvalho Chehab 
130b5dcee22SMauro Carvalho Chehab 	/* Free run */
131b5dcee22SMauro Carvalho Chehab 	unsigned hdmi_free_run_mode;
132b5dcee22SMauro Carvalho Chehab 
133b5dcee22SMauro Carvalho Chehab 	/* i2c addresses: 0 == use default */
134b5dcee22SMauro Carvalho Chehab 	u8 i2c_addresses[ADV76XX_PAGE_MAX];
135b5dcee22SMauro Carvalho Chehab };
136b5dcee22SMauro Carvalho Chehab 
137b5dcee22SMauro Carvalho Chehab enum adv76xx_pad {
138b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAD_HDMI_PORT_A = 0,
139b5dcee22SMauro Carvalho Chehab 	ADV7604_PAD_HDMI_PORT_B = 1,
140b5dcee22SMauro Carvalho Chehab 	ADV7604_PAD_HDMI_PORT_C = 2,
141b5dcee22SMauro Carvalho Chehab 	ADV7604_PAD_HDMI_PORT_D = 3,
142b5dcee22SMauro Carvalho Chehab 	ADV7604_PAD_VGA_RGB = 4,
143b5dcee22SMauro Carvalho Chehab 	ADV7604_PAD_VGA_COMP = 5,
144b5dcee22SMauro Carvalho Chehab 	/* The source pad is either 1 (ADV7611) or 6 (ADV7604) */
145b5dcee22SMauro Carvalho Chehab 	ADV7604_PAD_SOURCE = 6,
146b5dcee22SMauro Carvalho Chehab 	ADV7611_PAD_SOURCE = 1,
147b5dcee22SMauro Carvalho Chehab 	ADV76XX_PAD_MAX = 7,
148b5dcee22SMauro Carvalho Chehab };
149b5dcee22SMauro Carvalho Chehab 
150b5dcee22SMauro Carvalho Chehab #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE	(V4L2_CID_DV_CLASS_BASE + 0x1000)
151b5dcee22SMauro Carvalho Chehab #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL	(V4L2_CID_DV_CLASS_BASE + 0x1001)
152b5dcee22SMauro Carvalho Chehab #define V4L2_CID_ADV_RX_FREE_RUN_COLOR		(V4L2_CID_DV_CLASS_BASE + 0x1002)
153b5dcee22SMauro Carvalho Chehab 
154b5dcee22SMauro Carvalho Chehab /* notify events */
155b5dcee22SMauro Carvalho Chehab #define ADV76XX_HOTPLUG		1
156b5dcee22SMauro Carvalho Chehab 
157b5dcee22SMauro Carvalho Chehab #endif
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