1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 22bb69841SDavid S. Miller #ifndef __SUNGEM_PHY_H__ 32bb69841SDavid S. Miller #define __SUNGEM_PHY_H__ 42bb69841SDavid S. Miller 52bb69841SDavid S. Miller struct mii_phy; 62bb69841SDavid S. Miller 72bb69841SDavid S. Miller /* Operations supported by any kind of PHY */ 82bb69841SDavid S. Miller struct mii_phy_ops 92bb69841SDavid S. Miller { 102bb69841SDavid S. Miller int (*init)(struct mii_phy *phy); 112bb69841SDavid S. Miller int (*suspend)(struct mii_phy *phy); 122bb69841SDavid S. Miller int (*setup_aneg)(struct mii_phy *phy, u32 advertise); 132bb69841SDavid S. Miller int (*setup_forced)(struct mii_phy *phy, int speed, int fd); 142bb69841SDavid S. Miller int (*poll_link)(struct mii_phy *phy); 152bb69841SDavid S. Miller int (*read_link)(struct mii_phy *phy); 162bb69841SDavid S. Miller int (*enable_fiber)(struct mii_phy *phy, int autoneg); 172bb69841SDavid S. Miller }; 182bb69841SDavid S. Miller 192bb69841SDavid S. Miller /* Structure used to statically define an mii/gii based PHY */ 202bb69841SDavid S. Miller struct mii_phy_def 212bb69841SDavid S. Miller { 222bb69841SDavid S. Miller u32 phy_id; /* Concatenated ID1 << 16 | ID2 */ 232bb69841SDavid S. Miller u32 phy_id_mask; /* Significant bits */ 242bb69841SDavid S. Miller u32 features; /* Ethtool SUPPORTED_* defines */ 252bb69841SDavid S. Miller int magic_aneg; /* Autoneg does all speed test for us */ 262bb69841SDavid S. Miller const char* name; 272bb69841SDavid S. Miller const struct mii_phy_ops* ops; 282bb69841SDavid S. Miller }; 292bb69841SDavid S. Miller 302bb69841SDavid S. Miller enum { 312bb69841SDavid S. Miller BCM54XX_COPPER, 322bb69841SDavid S. Miller BCM54XX_FIBER, 332bb69841SDavid S. Miller BCM54XX_GBIC, 342bb69841SDavid S. Miller BCM54XX_SGMII, 352bb69841SDavid S. Miller BCM54XX_UNKNOWN, 362bb69841SDavid S. Miller }; 372bb69841SDavid S. Miller 382bb69841SDavid S. Miller /* An instance of a PHY, partially borrowed from mii_if_info */ 392bb69841SDavid S. Miller struct mii_phy 402bb69841SDavid S. Miller { 412bb69841SDavid S. Miller struct mii_phy_def* def; 422bb69841SDavid S. Miller u32 advertising; 432bb69841SDavid S. Miller int mii_id; 442bb69841SDavid S. Miller 452bb69841SDavid S. Miller /* 1: autoneg enabled, 0: disabled */ 462bb69841SDavid S. Miller int autoneg; 472bb69841SDavid S. Miller 482bb69841SDavid S. Miller /* forced speed & duplex (no autoneg) 492bb69841SDavid S. Miller * partner speed & duplex & pause (autoneg) 502bb69841SDavid S. Miller */ 512bb69841SDavid S. Miller int speed; 522bb69841SDavid S. Miller int duplex; 532bb69841SDavid S. Miller int pause; 542bb69841SDavid S. Miller 552bb69841SDavid S. Miller /* Provided by host chip */ 562bb69841SDavid S. Miller struct net_device *dev; 572bb69841SDavid S. Miller int (*mdio_read) (struct net_device *dev, int mii_id, int reg); 582bb69841SDavid S. Miller void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val); 592bb69841SDavid S. Miller void *platform_data; 602bb69841SDavid S. Miller }; 612bb69841SDavid S. Miller 622bb69841SDavid S. Miller /* Pass in a struct mii_phy with dev, mdio_read and mdio_write 632bb69841SDavid S. Miller * filled, the remaining fields will be filled on return 642bb69841SDavid S. Miller */ 6519e2f6feSDavid S. Miller extern int sungem_phy_probe(struct mii_phy *phy, int mii_id); 662bb69841SDavid S. Miller 672bb69841SDavid S. Miller 682bb69841SDavid S. Miller /* MII definitions missing from mii.h */ 692bb69841SDavid S. Miller 702bb69841SDavid S. Miller #define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */ 712bb69841SDavid S. Miller #define LPA_PAUSE 0x0400 722bb69841SDavid S. Miller 732bb69841SDavid S. Miller /* More PHY registers (model specific) */ 742bb69841SDavid S. Miller 752bb69841SDavid S. Miller /* MII BCM5201 MULTIPHY interrupt register */ 762bb69841SDavid S. Miller #define MII_BCM5201_INTERRUPT 0x1A 772bb69841SDavid S. Miller #define MII_BCM5201_INTERRUPT_INTENABLE 0x4000 782bb69841SDavid S. Miller 792bb69841SDavid S. Miller #define MII_BCM5201_AUXMODE2 0x1B 802bb69841SDavid S. Miller #define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008 812bb69841SDavid S. Miller 822bb69841SDavid S. Miller #define MII_BCM5201_MULTIPHY 0x1E 832bb69841SDavid S. Miller 842bb69841SDavid S. Miller /* MII BCM5201 MULTIPHY register bits */ 852bb69841SDavid S. Miller #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002 862bb69841SDavid S. Miller #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008 872bb69841SDavid S. Miller 882bb69841SDavid S. Miller /* MII BCM5221 Additional registers */ 892bb69841SDavid S. Miller #define MII_BCM5221_TEST 0x1f 902bb69841SDavid S. Miller #define MII_BCM5221_TEST_ENABLE_SHADOWS 0x0080 912bb69841SDavid S. Miller #define MII_BCM5221_SHDOW_AUX_STAT2 0x1b 922bb69841SDavid S. Miller #define MII_BCM5221_SHDOW_AUX_STAT2_APD 0x0020 932bb69841SDavid S. Miller #define MII_BCM5221_SHDOW_AUX_MODE4 0x1a 942bb69841SDavid S. Miller #define MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE 0x0001 952bb69841SDavid S. Miller #define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004 962bb69841SDavid S. Miller 972bb69841SDavid S. Miller /* MII BCM5241 Additional registers */ 982bb69841SDavid S. Miller #define MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR 0x0008 992bb69841SDavid S. Miller 1002bb69841SDavid S. Miller /* MII BCM5400 1000-BASET Control register */ 1012bb69841SDavid S. Miller #define MII_BCM5400_GB_CONTROL 0x09 1022bb69841SDavid S. Miller #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200 1032bb69841SDavid S. Miller 1042bb69841SDavid S. Miller /* MII BCM5400 AUXCONTROL register */ 1052bb69841SDavid S. Miller #define MII_BCM5400_AUXCONTROL 0x18 1062bb69841SDavid S. Miller #define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004 1072bb69841SDavid S. Miller 1082bb69841SDavid S. Miller /* MII BCM5400 AUXSTATUS register */ 1092bb69841SDavid S. Miller #define MII_BCM5400_AUXSTATUS 0x19 1102bb69841SDavid S. Miller #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700 1112bb69841SDavid S. Miller #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8 1122bb69841SDavid S. Miller 1132bb69841SDavid S. Miller /* 1000BT control (Marvell & BCM54xx at least) */ 1142bb69841SDavid S. Miller #define MII_1000BASETCONTROL 0x09 1152bb69841SDavid S. Miller #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 1162bb69841SDavid S. Miller #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 1172bb69841SDavid S. Miller 1182bb69841SDavid S. Miller /* Marvell 88E1011 PHY control */ 1192bb69841SDavid S. Miller #define MII_M1011_PHY_SPEC_CONTROL 0x10 1202bb69841SDavid S. Miller #define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20 1212bb69841SDavid S. Miller #define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40 1222bb69841SDavid S. Miller 1232bb69841SDavid S. Miller /* Marvell 88E1011 PHY status */ 1242bb69841SDavid S. Miller #define MII_M1011_PHY_SPEC_STATUS 0x11 1252bb69841SDavid S. Miller #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 1262bb69841SDavid S. Miller #define MII_M1011_PHY_SPEC_STATUS_100 0x4000 1272bb69841SDavid S. Miller #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 1282bb69841SDavid S. Miller #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 1292bb69841SDavid S. Miller #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 1302bb69841SDavid S. Miller #define MII_M1011_PHY_SPEC_STATUS_TX_PAUSE 0x0008 1312bb69841SDavid S. Miller #define MII_M1011_PHY_SPEC_STATUS_RX_PAUSE 0x0004 1322bb69841SDavid S. Miller 1332bb69841SDavid S. Miller #endif /* __SUNGEM_PHY_H__ */ 134