1*1802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2ec7ed770SAngelo Dureghello /* 3ec7ed770SAngelo Dureghello * Freescale DSPI controller driver 4ec7ed770SAngelo Dureghello * 5ec7ed770SAngelo Dureghello * Copyright (c) 2017 Angelo Dureghello <angelo@sysam.it> 6ec7ed770SAngelo Dureghello */ 7ec7ed770SAngelo Dureghello 8ec7ed770SAngelo Dureghello #ifndef SPI_FSL_DSPI_HEADER_H 9ec7ed770SAngelo Dureghello #define SPI_FSL_DSPI_HEADER_H 10ec7ed770SAngelo Dureghello 11ec7ed770SAngelo Dureghello /** 12ec7ed770SAngelo Dureghello * struct fsl_dspi_platform_data - platform data for the Freescale DSPI driver 13ec7ed770SAngelo Dureghello * @bus_num: board specific identifier for this DSPI driver. 14ec7ed770SAngelo Dureghello * @cs_num: number of chip selects supported by this DSPI driver. 15ec7ed770SAngelo Dureghello */ 16ec7ed770SAngelo Dureghello struct fsl_dspi_platform_data { 17ec7ed770SAngelo Dureghello u32 cs_num; 18ec7ed770SAngelo Dureghello u32 bus_num; 19ec7ed770SAngelo Dureghello u32 sck_cs_delay; 20ec7ed770SAngelo Dureghello u32 cs_sck_delay; 21ec7ed770SAngelo Dureghello }; 22ec7ed770SAngelo Dureghello 23ec7ed770SAngelo Dureghello #endif /* SPI_FSL_DSPI_HEADER_H */ 24