1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _LINUX_QCOM_GENI_SE 7 #define _LINUX_QCOM_GENI_SE 8 9 #include <linux/interconnect.h> 10 11 /** 12 * enum geni_se_xfer_mode: Transfer modes supported by Serial Engines 13 * 14 * @GENI_SE_INVALID: Invalid mode 15 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO 16 * by programmed IO method 17 * @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred 18 * with SE by DMAengine internal to SE 19 * @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine 20 * configured by a firmware residing on a GSI engine. This DMA name is 21 * interchangeably used as GSI or GPI which seem to imply the same DMAengine 22 */ 23 24 enum geni_se_xfer_mode { 25 GENI_SE_INVALID, 26 GENI_SE_FIFO, 27 GENI_SE_DMA, 28 GENI_GPI_DMA, 29 }; 30 31 /* Protocols supported by GENI Serial Engines */ 32 enum geni_se_protocol_type { 33 GENI_SE_NONE, 34 GENI_SE_SPI, 35 GENI_SE_UART, 36 GENI_SE_I2C, 37 GENI_SE_I3C, 38 }; 39 40 struct geni_wrapper; 41 struct clk; 42 43 enum geni_icc_path_index { 44 GENI_TO_CORE, 45 CPU_TO_GENI, 46 GENI_TO_DDR 47 }; 48 49 struct geni_icc_path { 50 struct icc_path *path; 51 unsigned int avg_bw; 52 }; 53 54 /** 55 * struct geni_se - GENI Serial Engine 56 * @base: Base Address of the Serial Engine's register block 57 * @dev: Pointer to the Serial Engine device 58 * @wrapper: Pointer to the parent QUP Wrapper core 59 * @clk: Handle to the core serial engine clock 60 * @num_clk_levels: Number of valid clock levels in clk_perf_tbl 61 * @clk_perf_tbl: Table of clock frequency input to serial engine clock 62 * @icc_paths: Array of ICC paths for SE 63 */ 64 struct geni_se { 65 void __iomem *base; 66 struct device *dev; 67 struct geni_wrapper *wrapper; 68 struct clk *clk; 69 unsigned int num_clk_levels; 70 unsigned long *clk_perf_tbl; 71 struct geni_icc_path icc_paths[3]; 72 }; 73 74 /* Common SE registers */ 75 #define GENI_FORCE_DEFAULT_REG 0x20 76 #define SE_GENI_STATUS 0x40 77 #define GENI_SER_M_CLK_CFG 0x48 78 #define GENI_SER_S_CLK_CFG 0x4c 79 #define GENI_IF_DISABLE_RO 0x64 80 #define GENI_FW_REVISION_RO 0x68 81 #define SE_GENI_CLK_SEL 0x7c 82 #define SE_GENI_DMA_MODE_EN 0x258 83 #define SE_GENI_M_CMD0 0x600 84 #define SE_GENI_M_CMD_CTRL_REG 0x604 85 #define SE_GENI_M_IRQ_STATUS 0x610 86 #define SE_GENI_M_IRQ_EN 0x614 87 #define SE_GENI_M_IRQ_CLEAR 0x618 88 #define SE_GENI_S_CMD0 0x630 89 #define SE_GENI_S_CMD_CTRL_REG 0x634 90 #define SE_GENI_S_IRQ_STATUS 0x640 91 #define SE_GENI_S_IRQ_EN 0x644 92 #define SE_GENI_S_IRQ_CLEAR 0x648 93 #define SE_GENI_TX_FIFOn 0x700 94 #define SE_GENI_RX_FIFOn 0x780 95 #define SE_GENI_TX_FIFO_STATUS 0x800 96 #define SE_GENI_RX_FIFO_STATUS 0x804 97 #define SE_GENI_TX_WATERMARK_REG 0x80c 98 #define SE_GENI_RX_WATERMARK_REG 0x810 99 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814 100 #define SE_GENI_IOS 0x908 101 #define SE_DMA_TX_IRQ_STAT 0xc40 102 #define SE_DMA_TX_IRQ_CLR 0xc44 103 #define SE_DMA_TX_FSM_RST 0xc58 104 #define SE_DMA_RX_IRQ_STAT 0xd40 105 #define SE_DMA_RX_IRQ_CLR 0xd44 106 #define SE_DMA_RX_LEN_IN 0xd54 107 #define SE_DMA_RX_FSM_RST 0xd58 108 #define SE_HW_PARAM_0 0xe24 109 #define SE_HW_PARAM_1 0xe28 110 111 /* GENI_FORCE_DEFAULT_REG fields */ 112 #define FORCE_DEFAULT BIT(0) 113 114 /* GENI_STATUS fields */ 115 #define M_GENI_CMD_ACTIVE BIT(0) 116 #define S_GENI_CMD_ACTIVE BIT(12) 117 118 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */ 119 #define SER_CLK_EN BIT(0) 120 #define CLK_DIV_MSK GENMASK(15, 4) 121 #define CLK_DIV_SHFT 4 122 123 /* GENI_IF_DISABLE_RO fields */ 124 #define FIFO_IF_DISABLE (BIT(0)) 125 126 /* GENI_FW_REVISION_RO fields */ 127 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8) 128 #define FW_REV_PROTOCOL_SHFT 8 129 130 /* GENI_CLK_SEL fields */ 131 #define CLK_SEL_MSK GENMASK(2, 0) 132 133 /* SE_GENI_DMA_MODE_EN */ 134 #define GENI_DMA_MODE_EN BIT(0) 135 136 /* GENI_M_CMD0 fields */ 137 #define M_OPCODE_MSK GENMASK(31, 27) 138 #define M_OPCODE_SHFT 27 139 #define M_PARAMS_MSK GENMASK(26, 0) 140 141 /* GENI_M_CMD_CTRL_REG */ 142 #define M_GENI_CMD_CANCEL BIT(2) 143 #define M_GENI_CMD_ABORT BIT(1) 144 #define M_GENI_DISABLE BIT(0) 145 146 /* GENI_S_CMD0 fields */ 147 #define S_OPCODE_MSK GENMASK(31, 27) 148 #define S_OPCODE_SHFT 27 149 #define S_PARAMS_MSK GENMASK(26, 0) 150 151 /* GENI_S_CMD_CTRL_REG */ 152 #define S_GENI_CMD_CANCEL BIT(2) 153 #define S_GENI_CMD_ABORT BIT(1) 154 #define S_GENI_DISABLE BIT(0) 155 156 /* GENI_M_IRQ_EN fields */ 157 #define M_CMD_DONE_EN BIT(0) 158 #define M_CMD_OVERRUN_EN BIT(1) 159 #define M_ILLEGAL_CMD_EN BIT(2) 160 #define M_CMD_FAILURE_EN BIT(3) 161 #define M_CMD_CANCEL_EN BIT(4) 162 #define M_CMD_ABORT_EN BIT(5) 163 #define M_TIMESTAMP_EN BIT(6) 164 #define M_RX_IRQ_EN BIT(7) 165 #define M_GP_SYNC_IRQ_0_EN BIT(8) 166 #define M_GP_IRQ_0_EN BIT(9) 167 #define M_GP_IRQ_1_EN BIT(10) 168 #define M_GP_IRQ_2_EN BIT(11) 169 #define M_GP_IRQ_3_EN BIT(12) 170 #define M_GP_IRQ_4_EN BIT(13) 171 #define M_GP_IRQ_5_EN BIT(14) 172 #define M_IO_DATA_DEASSERT_EN BIT(22) 173 #define M_IO_DATA_ASSERT_EN BIT(23) 174 #define M_RX_FIFO_RD_ERR_EN BIT(24) 175 #define M_RX_FIFO_WR_ERR_EN BIT(25) 176 #define M_RX_FIFO_WATERMARK_EN BIT(26) 177 #define M_RX_FIFO_LAST_EN BIT(27) 178 #define M_TX_FIFO_RD_ERR_EN BIT(28) 179 #define M_TX_FIFO_WR_ERR_EN BIT(29) 180 #define M_TX_FIFO_WATERMARK_EN BIT(30) 181 #define M_SEC_IRQ_EN BIT(31) 182 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ 183 M_IO_DATA_DEASSERT_EN | \ 184 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ 185 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ 186 M_TX_FIFO_WR_ERR_EN) 187 188 /* GENI_S_IRQ_EN fields */ 189 #define S_CMD_DONE_EN BIT(0) 190 #define S_CMD_OVERRUN_EN BIT(1) 191 #define S_ILLEGAL_CMD_EN BIT(2) 192 #define S_CMD_FAILURE_EN BIT(3) 193 #define S_CMD_CANCEL_EN BIT(4) 194 #define S_CMD_ABORT_EN BIT(5) 195 #define S_GP_SYNC_IRQ_0_EN BIT(8) 196 #define S_GP_IRQ_0_EN BIT(9) 197 #define S_GP_IRQ_1_EN BIT(10) 198 #define S_GP_IRQ_2_EN BIT(11) 199 #define S_GP_IRQ_3_EN BIT(12) 200 #define S_GP_IRQ_4_EN BIT(13) 201 #define S_GP_IRQ_5_EN BIT(14) 202 #define S_IO_DATA_DEASSERT_EN BIT(22) 203 #define S_IO_DATA_ASSERT_EN BIT(23) 204 #define S_RX_FIFO_RD_ERR_EN BIT(24) 205 #define S_RX_FIFO_WR_ERR_EN BIT(25) 206 #define S_RX_FIFO_WATERMARK_EN BIT(26) 207 #define S_RX_FIFO_LAST_EN BIT(27) 208 #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \ 209 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN) 210 211 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */ 212 #define WATERMARK_MSK GENMASK(5, 0) 213 214 /* GENI_TX_FIFO_STATUS fields */ 215 #define TX_FIFO_WC GENMASK(27, 0) 216 217 /* GENI_RX_FIFO_STATUS fields */ 218 #define RX_LAST BIT(31) 219 #define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28) 220 #define RX_LAST_BYTE_VALID_SHFT 28 221 #define RX_FIFO_WC_MSK GENMASK(24, 0) 222 223 /* SE_GENI_IOS fields */ 224 #define IO2_DATA_IN BIT(1) 225 #define RX_DATA_IN BIT(0) 226 227 /* SE_DMA_TX_IRQ_STAT Register fields */ 228 #define TX_DMA_DONE BIT(0) 229 #define TX_EOT BIT(1) 230 #define TX_SBE BIT(2) 231 #define TX_RESET_DONE BIT(3) 232 233 /* SE_DMA_RX_IRQ_STAT Register fields */ 234 #define RX_DMA_DONE BIT(0) 235 #define RX_EOT BIT(1) 236 #define RX_SBE BIT(2) 237 #define RX_RESET_DONE BIT(3) 238 #define RX_FLUSH_DONE BIT(4) 239 #define RX_DMA_PARITY_ERR BIT(5) 240 #define RX_DMA_BREAK GENMASK(8, 7) 241 #define RX_GENI_GP_IRQ GENMASK(10, 5) 242 #define RX_GENI_CANCEL_IRQ BIT(11) 243 #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12) 244 245 /* SE_HW_PARAM_0 fields */ 246 #define TX_FIFO_WIDTH_MSK GENMASK(29, 24) 247 #define TX_FIFO_WIDTH_SHFT 24 248 #define TX_FIFO_DEPTH_MSK GENMASK(21, 16) 249 #define TX_FIFO_DEPTH_SHFT 16 250 251 /* SE_HW_PARAM_1 fields */ 252 #define RX_FIFO_WIDTH_MSK GENMASK(29, 24) 253 #define RX_FIFO_WIDTH_SHFT 24 254 #define RX_FIFO_DEPTH_MSK GENMASK(21, 16) 255 #define RX_FIFO_DEPTH_SHFT 16 256 257 #define HW_VER_MAJOR_MASK GENMASK(31, 28) 258 #define HW_VER_MAJOR_SHFT 28 259 #define HW_VER_MINOR_MASK GENMASK(27, 16) 260 #define HW_VER_MINOR_SHFT 16 261 #define HW_VER_STEP_MASK GENMASK(15, 0) 262 263 #define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT) 264 #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT) 265 #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK) 266 267 /* QUP SE VERSION value for major number 2 and minor number 5 */ 268 #define QUP_SE_VERSION_2_5 0x20050000 269 270 /* 271 * Define bandwidth thresholds that cause the underlying Core 2X interconnect 272 * clock to run at the named frequency. These baseline values are recommended 273 * by the hardware team, and are not dynamically scaled with GENI bandwidth 274 * beyond basic on/off. 275 */ 276 #define CORE_2X_19_2_MHZ 960 277 #define CORE_2X_50_MHZ 2500 278 #define CORE_2X_100_MHZ 5000 279 #define CORE_2X_150_MHZ 7500 280 #define CORE_2X_200_MHZ 10000 281 #define CORE_2X_236_MHZ 16383 282 283 #define GENI_DEFAULT_BW Bps_to_icc(1000) 284 285 #if IS_ENABLED(CONFIG_QCOM_GENI_SE) 286 287 u32 geni_se_get_qup_hw_version(struct geni_se *se); 288 289 /** 290 * geni_se_read_proto() - Read the protocol configured for a serial engine 291 * @se: Pointer to the concerned serial engine. 292 * 293 * Return: Protocol value as configured in the serial engine. 294 */ 295 static inline u32 geni_se_read_proto(struct geni_se *se) 296 { 297 u32 val; 298 299 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); 300 301 return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT; 302 } 303 304 /** 305 * geni_se_setup_m_cmd() - Setup the primary sequencer 306 * @se: Pointer to the concerned serial engine. 307 * @cmd: Command/Operation to setup in the primary sequencer. 308 * @params: Parameter for the sequencer command. 309 * 310 * This function is used to configure the primary sequencer with the 311 * command and its associated parameters. 312 */ 313 static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params) 314 { 315 u32 m_cmd; 316 317 m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK); 318 writel(m_cmd, se->base + SE_GENI_M_CMD0); 319 } 320 321 /** 322 * geni_se_setup_s_cmd() - Setup the secondary sequencer 323 * @se: Pointer to the concerned serial engine. 324 * @cmd: Command/Operation to setup in the secondary sequencer. 325 * @params: Parameter for the sequencer command. 326 * 327 * This function is used to configure the secondary sequencer with the 328 * command and its associated parameters. 329 */ 330 static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params) 331 { 332 u32 s_cmd; 333 334 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0); 335 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK); 336 s_cmd |= (cmd << S_OPCODE_SHFT); 337 s_cmd |= (params & S_PARAMS_MSK); 338 writel(s_cmd, se->base + SE_GENI_S_CMD0); 339 } 340 341 /** 342 * geni_se_cancel_m_cmd() - Cancel the command configured in the primary 343 * sequencer 344 * @se: Pointer to the concerned serial engine. 345 * 346 * This function is used to cancel the currently configured command in the 347 * primary sequencer. 348 */ 349 static inline void geni_se_cancel_m_cmd(struct geni_se *se) 350 { 351 writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG); 352 } 353 354 /** 355 * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary 356 * sequencer 357 * @se: Pointer to the concerned serial engine. 358 * 359 * This function is used to cancel the currently configured command in the 360 * secondary sequencer. 361 */ 362 static inline void geni_se_cancel_s_cmd(struct geni_se *se) 363 { 364 writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG); 365 } 366 367 /** 368 * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer 369 * @se: Pointer to the concerned serial engine. 370 * 371 * This function is used to force abort the currently configured command in the 372 * primary sequencer. 373 */ 374 static inline void geni_se_abort_m_cmd(struct geni_se *se) 375 { 376 writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG); 377 } 378 379 /** 380 * geni_se_abort_s_cmd() - Abort the command configured in the secondary 381 * sequencer 382 * @se: Pointer to the concerned serial engine. 383 * 384 * This function is used to force abort the currently configured command in the 385 * secondary sequencer. 386 */ 387 static inline void geni_se_abort_s_cmd(struct geni_se *se) 388 { 389 writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG); 390 } 391 392 /** 393 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine 394 * @se: Pointer to the concerned serial engine. 395 * 396 * This function is used to get the depth i.e. number of elements in the 397 * TX fifo of the serial engine. 398 * 399 * Return: TX fifo depth in units of FIFO words. 400 */ 401 static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se) 402 { 403 u32 val; 404 405 val = readl_relaxed(se->base + SE_HW_PARAM_0); 406 407 return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT; 408 } 409 410 /** 411 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine 412 * @se: Pointer to the concerned serial engine. 413 * 414 * This function is used to get the width i.e. word size per element in the 415 * TX fifo of the serial engine. 416 * 417 * Return: TX fifo width in bits 418 */ 419 static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se) 420 { 421 u32 val; 422 423 val = readl_relaxed(se->base + SE_HW_PARAM_0); 424 425 return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT; 426 } 427 428 /** 429 * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine 430 * @se: Pointer to the concerned serial engine. 431 * 432 * This function is used to get the depth i.e. number of elements in the 433 * RX fifo of the serial engine. 434 * 435 * Return: RX fifo depth in units of FIFO words 436 */ 437 static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se) 438 { 439 u32 val; 440 441 val = readl_relaxed(se->base + SE_HW_PARAM_1); 442 443 return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT; 444 } 445 446 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr); 447 448 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode); 449 450 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words, 451 bool msb_to_lsb, bool tx_cfg, bool rx_cfg); 452 453 int geni_se_resources_off(struct geni_se *se); 454 455 int geni_se_resources_on(struct geni_se *se); 456 457 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl); 458 459 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq, 460 unsigned int *index, unsigned long *res_freq, 461 bool exact); 462 463 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len, 464 dma_addr_t *iova); 465 466 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len, 467 dma_addr_t *iova); 468 469 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); 470 471 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); 472 473 int geni_icc_get(struct geni_se *se, const char *icc_ddr); 474 475 int geni_icc_set_bw(struct geni_se *se); 476 void geni_icc_set_tag(struct geni_se *se, u32 tag); 477 478 int geni_icc_enable(struct geni_se *se); 479 480 int geni_icc_disable(struct geni_se *se); 481 #endif 482 #endif 483